[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / X64 / VirtualMemory.h

/** @file\r
  x64 Long Mode Virtual Memory Management Definitions\r
\r
  References:\r
    1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
    2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
    3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
    4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
\r
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
#ifndef _VIRTUAL_MEMORY_H_\r
#define _VIRTUAL_MEMORY_H_\r
\r
\r
#define SYS_CODE64_SEL 0x38\r
\r
\r
#pragma pack(1)\r
\r
typedef union {\r
  struct {\r
    UINT32  LimitLow    : 16;\r
    UINT32  BaseLow     : 16;\r
    UINT32  BaseMid     : 8;\r
    UINT32  Type        : 4;\r
    UINT32  System      : 1;\r
    UINT32  Dpl         : 2;\r
    UINT32  Present     : 1;\r
    UINT32  LimitHigh   : 4;\r
    UINT32  Software    : 1;\r
    UINT32  Reserved    : 1;\r
    UINT32  DefaultSize : 1;\r
    UINT32  Granularity : 1;\r
    UINT32  BaseHigh    : 8;\r
  } Bits;\r
  UINT64  Uint64;\r
} IA32_GDT;\r
\r
typedef struct {\r
  IA32_IDT_GATE_DESCRIPTOR  Ia32IdtEntry;\r
  UINT32                    Offset32To63;\r
  UINT32                    Reserved;\r
} X64_IDT_GATE_DESCRIPTOR;\r
\r
//\r
// Page-Map Level-4 Offset (PML4) and\r
// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
//\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Reserved:1;               // Reserved\r
    UINT64  MustBeZero:2;             // Must Be Zero\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_MAP_AND_DIRECTORY_POINTER;\r
\r
//\r
// Page Table Entry 4KB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  PAT:1;                    //\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_4K_ENTRY;\r
\r
//\r
// Page Table Entry 2MB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:8;             // Must be zero;\r
    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_ENTRY;\r
\r
//\r
// Page Table Entry 1GB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:17;            // Must be zero;\r
    UINT64  PageTableBaseAddress:22;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_1G_ENTRY;\r
\r
#pragma pack()\r
\r
#define CR0_WP                      BIT16\r
\r
#define IA32_PG_P                   BIT0\r
#define IA32_PG_RW                  BIT1\r
#define IA32_PG_PS                  BIT7\r
\r
#define PAGING_PAE_INDEX_MASK       0x1FF\r
\r
#define PAGING_4K_ADDRESS_MASK_64   0x000FFFFFFFFFF000ull\r
#define PAGING_2M_ADDRESS_MASK_64   0x000FFFFFFFE00000ull\r
#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
\r
#define PAGING_L1_ADDRESS_SHIFT     12\r
#define PAGING_L2_ADDRESS_SHIFT     21\r
#define PAGING_L3_ADDRESS_SHIFT     30\r
#define PAGING_L4_ADDRESS_SHIFT     39\r
\r
#define PAGING_PML4E_NUMBER         4\r
\r
#define PAGE_TABLE_POOL_ALIGNMENT   BASE_2MB\r
#define PAGE_TABLE_POOL_UNIT_SIZE   SIZE_2MB\r
#define PAGE_TABLE_POOL_UNIT_PAGES  EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
#define PAGE_TABLE_POOL_ALIGN_MASK  \\r
  (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
\r
typedef struct {\r
  VOID            *NextPool;\r
  UINTN           Offset;\r
  UINTN           FreePages;\r
} PAGE_TABLE_POOL;\r
\r
/**\r
  Enable Execute Disable Bit.\r
\r
**/\r
VOID\r
EnableExecuteDisableBit (\r
  VOID\r
  );\r
\r
/**\r
  Split 2M page to 4K.\r
\r
  @param[in]      PhysicalAddress       Start physical address the 2M page covered.\r
  @param[in, out] PageEntry2M           Pointer to 2M page entry.\r
  @param[in]      StackBase             Stack base address.\r
  @param[in]      StackSize             Stack size.\r
\r
**/\r
VOID\r
Split2MPageTo4K (\r
  IN EFI_PHYSICAL_ADDRESS               PhysicalAddress,\r
  IN OUT UINT64                         *PageEntry2M,\r
  IN EFI_PHYSICAL_ADDRESS               StackBase,\r
  IN UINTN                              StackSize\r
  );\r
\r
/**\r
  Allocates and fills in the Page Directory and Page Table Entries to\r
  establish a 1:1 Virtual to Physical mapping.\r
\r
  @param[in] StackBase  Stack base address.\r
  @param[in] StackSize  Stack size.\r
\r
  @return The address of 4 level page map.\r
\r
**/\r
UINTN\r
CreateIdentityMappingPageTables (\r
  IN EFI_PHYSICAL_ADDRESS   StackBase,\r
  IN UINTN                  StackSize\r
  );\r
\r
\r
/**\r
\r
  Fix up the vector number in the vector code.\r
\r
  @param VectorBase   Base address of the vector handler.\r
  @param VectorNum    Index of vector.\r
\r
**/\r
VOID\r
EFIAPI\r
AsmVectorFixup (\r
  VOID    *VectorBase,\r
  UINT8   VectorNum\r
  );\r
\r
\r
/**\r
\r
  Get the information of vector template.\r
\r
  @param TemplateBase   Base address of the template code.\r
\r
  @return               Size of the Template code.\r
\r
**/\r
UINTN\r
EFIAPI\r
AsmGetVectorTemplatInfo (\r
  OUT   VOID  **TemplateBase\r
  );\r
\r
/**\r
  Clear legacy memory located at the first 4K-page.\r
\r
  This function traverses the whole HOB list to check if memory from 0 to 4095\r
  exists and has not been allocated, and then clear it if so.\r
\r
  @param HobStart         The start of HobList passed to DxeCore.\r
\r
**/\r
VOID\r
ClearFirst4KPage (\r
  IN  VOID *HobStart\r
  );\r
\r
/**\r
  Return configure status of NULL pointer detection feature.\r
\r
  @return TRUE   NULL pointer detection feature is enabled\r
  @return FALSE  NULL pointer detection feature is disabled\r
**/\r
BOOLEAN\r
IsNullDetectionEnabled (\r
  VOID\r
  );\r
\r
/**\r
  Prevent the memory pages used for page table from been overwritten.\r
\r
  @param[in] PageTableBase    Base address of page table (CR3).\r
  @param[in] Level4Paging     Level 4 paging flag.\r
\r
**/\r
VOID\r
EnablePageTableProtection (\r
  IN  UINTN     PageTableBase,\r
  IN  BOOLEAN   Level4Paging\r
  );\r
\r
/**\r
  This API provides a way to allocate memory for page table.\r
\r
  This API can be called more than once to allocate memory for page tables.\r
\r
  Allocates the number of 4KB pages and returns a pointer to the allocated\r
  buffer. The buffer returned is aligned on a 4KB boundary.\r
\r
  If Pages is 0, then NULL is returned.\r
  If there is not enough memory remaining to satisfy the request, then NULL is\r
  returned.\r
\r
  @param  Pages                 The number of 4 KB pages to allocate.\r
\r
  @return A pointer to the allocated buffer or NULL if allocation fails.\r
\r
**/\r
VOID *\r
AllocatePageTableMemory (\r
  IN UINTN           Pages\r
  );\r
\r
#endif\r
Commit	Line	Data
f3b33289	1	/** @file\r
d1102dba	2	x64 Long Mode Virtual Memory Management Definitions\r
f3b33289	3	\r
f3b33289	4	References:\r
48557c65	5	1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
	6	2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
	7	3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
f3b33289	8	4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
f3b33289	9	\r
d1102dba	10	Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
5997daf7 LD	11	Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
5997daf7 LD	12	\r
cd5ebaa0	13	This program and the accompanying materials\r
f3b33289	14	are licensed and made available under the terms and conditions of the BSD License\r
	15	which accompanies this distribution. The full text of the license may be found at\r
	16	http://opensource.org/licenses/bsd-license.php\r
	17	\r
	18	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	19	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	20	\r
d1102dba	21	**/\r
f3b33289	22	#ifndef _VIRTUAL_MEMORY_H_\r
	23	#define _VIRTUAL_MEMORY_H_\r
	24	\r
	25	\r
	26	#define SYS_CODE64_SEL 0x38\r
	27	\r
5997daf7	28	\r
f3b33289	29	#pragma pack(1)\r
	30	\r
	31	typedef union {\r
	32	struct {\r
	33	UINT32 LimitLow : 16;\r
	34	UINT32 BaseLow : 16;\r
	35	UINT32 BaseMid : 8;\r
	36	UINT32 Type : 4;\r
	37	UINT32 System : 1;\r
	38	UINT32 Dpl : 2;\r
	39	UINT32 Present : 1;\r
	40	UINT32 LimitHigh : 4;\r
	41	UINT32 Software : 1;\r
	42	UINT32 Reserved : 1;\r
	43	UINT32 DefaultSize : 1;\r
	44	UINT32 Granularity : 1;\r
	45	UINT32 BaseHigh : 8;\r
	46	} Bits;\r
	47	UINT64 Uint64;\r
	48	} IA32_GDT;\r
	49	\r
	50	typedef struct {\r
	51	IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;\r
	52	UINT32 Offset32To63;\r
	53	UINT32 Reserved;\r
	54	} X64_IDT_GATE_DESCRIPTOR;\r
	55	\r
	56	//\r
	57	// Page-Map Level-4 Offset (PML4) and\r
	58	// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
	59	//\r
	60	\r
	61	typedef union {\r
	62	struct {\r
	63	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	64	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	65	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	66	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	67	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	68	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	69	UINT64 Reserved:1; // Reserved\r
	70	UINT64 MustBeZero:2; // Must Be Zero\r
	71	UINT64 Available:3; // Available for use by system software\r
	72	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
	73	UINT64 AvabilableHigh:11; // Available for use by system software\r
	74	UINT64 Nx:1; // No Execute bit\r
	75	} Bits;\r
	76	UINT64 Uint64;\r
	77	} PAGE_MAP_AND_DIRECTORY_POINTER;\r
	78	\r
5630cdfe SZ	79	//\r
	80	// Page Table Entry 4KB\r
	81	//\r
	82	typedef union {\r
	83	struct {\r
	84	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	85	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	86	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	87	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	88	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	89	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	90	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
	91	UINT64 PAT:1; //\r
	92	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	93	UINT64 Available:3; // Available for use by system software\r
	94	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
	95	UINT64 AvabilableHigh:11; // Available for use by system software\r
	96	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
	97	} Bits;\r
	98	UINT64 Uint64;\r
	99	} PAGE_TABLE_4K_ENTRY;\r
	100	\r
f3b33289	101	//\r
	102	// Page Table Entry 2MB\r
	103	//\r
	104	typedef union {\r
	105	struct {\r
	106	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	107	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	108	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	109	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	110	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	111	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	112	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
d1102dba	113	UINT64 MustBe1:1; // Must be 1\r
f3b33289	114	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	115	UINT64 Available:3; // Available for use by system software\r
	116	UINT64 PAT:1; //\r
	117	UINT64 MustBeZero:8; // Must be zero;\r
	118	UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
	119	UINT64 AvabilableHigh:11; // Available for use by system software\r
	120	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
	121	} Bits;\r
	122	UINT64 Uint64;\r
	123	} PAGE_TABLE_ENTRY;\r
	124	\r
c56b6566 JY	125	//\r
	126	// Page Table Entry 1GB\r
	127	//\r
	128	typedef union {\r
	129	struct {\r
	130	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	131	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	132	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	133	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	134	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	135	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	136	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
d1102dba	137	UINT64 MustBe1:1; // Must be 1\r
c56b6566 JY	138	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
	139	UINT64 Available:3; // Available for use by system software\r
	140	UINT64 PAT:1; //\r
	141	UINT64 MustBeZero:17; // Must be zero;\r
	142	UINT64 PageTableBaseAddress:22; // Page Table Base Address\r
	143	UINT64 AvabilableHigh:11; // Available for use by system software\r
	144	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
	145	} Bits;\r
	146	UINT64 Uint64;\r
	147	} PAGE_TABLE_1G_ENTRY;\r
	148	\r
f3b33289	149	#pragma pack()\r
f3b33289	150	\r
2ac1730b JW	151	#define CR0_WP BIT16\r
2ac1730b JW	152	\r
5630cdfe SZ	153	#define IA32_PG_P BIT0\r
5630cdfe SZ	154	#define IA32_PG_RW BIT1\r
2ac1730b JW	155	#define IA32_PG_PS BIT7\r
	156	\r
	157	#define PAGING_PAE_INDEX_MASK 0x1FF\r
5630cdfe	158	\r
2ac1730b JW	159	#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
2ac1730b JW	160	#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
5997daf7 LD	161	#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
5997daf7 LD	162	\r
2ac1730b JW	163	#define PAGING_L1_ADDRESS_SHIFT 12\r
	164	#define PAGING_L2_ADDRESS_SHIFT 21\r
	165	#define PAGING_L3_ADDRESS_SHIFT 30\r
	166	#define PAGING_L4_ADDRESS_SHIFT 39\r
	167	\r
	168	#define PAGING_PML4E_NUMBER 4\r
	169	\r
	170	#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB\r
	171	#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB\r
	172	#define PAGE_TABLE_POOL_UNIT_PAGES EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
	173	#define PAGE_TABLE_POOL_ALIGN_MASK \\r
	174	(~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
	175	\r
	176	typedef struct {\r
	177	VOID *NextPool;\r
	178	UINTN Offset;\r
	179	UINTN FreePages;\r
	180	} PAGE_TABLE_POOL;\r
	181	\r
5630cdfe SZ	182	/**\r
	183	Enable Execute Disable Bit.\r
	184	\r
	185	**/\r
	186	VOID\r
	187	EnableExecuteDisableBit (\r
	188	VOID\r
	189	);\r
	190	\r
	191	/**\r
	192	Split 2M page to 4K.\r
	193	\r
	194	@param[in] PhysicalAddress Start physical address the 2M page covered.\r
	195	@param[in, out] PageEntry2M Pointer to 2M page entry.\r
	196	@param[in] StackBase Stack base address.\r
	197	@param[in] StackSize Stack size.\r
	198	\r
	199	**/\r
	200	VOID\r
	201	Split2MPageTo4K (\r
	202	IN EFI_PHYSICAL_ADDRESS PhysicalAddress,\r
	203	IN OUT UINT64 *PageEntry2M,\r
	204	IN EFI_PHYSICAL_ADDRESS StackBase,\r
	205	IN UINTN StackSize\r
	206	);\r
f3b33289	207	\r
f3b33289	208	/**\r
	209	Allocates and fills in the Page Directory and Page Table Entries to\r
	210	establish a 1:1 Virtual to Physical mapping.\r
	211	\r
5630cdfe SZ	212	@param[in] StackBase Stack base address.\r
5630cdfe SZ	213	@param[in] StackSize Stack size.\r
f3b33289	214	\r
48557c65	215	@return The address of 4 level page map.\r
f3b33289	216	\r
	217	**/\r
	218	UINTN\r
	219	CreateIdentityMappingPageTables (\r
5630cdfe SZ	220	IN EFI_PHYSICAL_ADDRESS StackBase,\r
5630cdfe SZ	221	IN UINTN StackSize\r
f3b33289	222	);\r
	223	\r
	224	\r
f3b33289	225	/**\r
d1102dba	226	\r
f3b33289	227	Fix up the vector number in the vector code.\r
d1102dba	228	\r
f3b33289	229	@param VectorBase Base address of the vector handler.\r
f3b33289	230	@param VectorNum Index of vector.\r
	231	\r
	232	**/\r
	233	VOID\r
	234	EFIAPI\r
	235	AsmVectorFixup (\r
	236	VOID *VectorBase,\r
	237	UINT8 VectorNum\r
	238	);\r
	239	\r
	240	\r
f3b33289	241	/**\r
d1102dba	242	\r
f3b33289	243	Get the information of vector template.\r
d1102dba	244	\r
f3b33289	245	@param TemplateBase Base address of the template code.\r
d1102dba	246	\r
f3b33289	247	@return Size of the Template code.\r
	248	\r
	249	**/\r
	250	UINTN\r
	251	EFIAPI\r
	252	AsmGetVectorTemplatInfo (\r
	253	OUT VOID **TemplateBase\r
	254	);\r
	255	\r
ac733f31 SZ	256	/**\r
	257	Clear legacy memory located at the first 4K-page.\r
	258	\r
	259	This function traverses the whole HOB list to check if memory from 0 to 4095\r
	260	exists and has not been allocated, and then clear it if so.\r
	261	\r
	262	@param HobStart The start of HobList passed to DxeCore.\r
	263	\r
	264	**/\r
	265	VOID\r
	266	ClearFirst4KPage (\r
	267	IN VOID *HobStart\r
	268	);\r
	269	\r
	270	/**\r
	271	Return configure status of NULL pointer detection feature.\r
	272	\r
	273	@return TRUE NULL pointer detection feature is enabled\r
	274	@return FALSE NULL pointer detection feature is disabled\r
	275	**/\r
	276	BOOLEAN\r
	277	IsNullDetectionEnabled (\r
	278	VOID\r
	279	);\r
f3b33289	280	\r
2ac1730b JW	281	/**\r
	282	Prevent the memory pages used for page table from been overwritten.\r
	283	\r
	284	@param[in] PageTableBase Base address of page table (CR3).\r
	285	@param[in] Level4Paging Level 4 paging flag.\r
	286	\r
	287	**/\r
	288	VOID\r
	289	EnablePageTableProtection (\r
	290	IN UINTN PageTableBase,\r
	291	IN BOOLEAN Level4Paging\r
	292	);\r
	293	\r
	294	/**\r
	295	This API provides a way to allocate memory for page table.\r
	296	\r
	297	This API can be called more than once to allocate memory for page tables.\r
	298	\r
	299	Allocates the number of 4KB pages and returns a pointer to the allocated\r
	300	buffer. The buffer returned is aligned on a 4KB boundary.\r
	301	\r
	302	If Pages is 0, then NULL is returned.\r
	303	If there is not enough memory remaining to satisfy the request, then NULL is\r
	304	returned.\r
	305	\r
	306	@param Pages The number of 4 KB pages to allocate.\r
	307	\r
	308	@return A pointer to the allocated buffer or NULL if allocation fails.\r
	309	\r
	310	**/\r
	311	VOID *\r
	312	AllocatePageTableMemory (\r
	313	IN UINTN Pages\r
	314	);\r
	315	\r
d1102dba	316	#endif\r