| 192f6d4c |
1 | //++\r |
| 2 | // Copyright (c) 2006, Intel Corporation \r |
| 3 | // All rights reserved. This program and the accompanying materials \r |
| 4 | // are licensed and made available under the terms and conditions of the BSD License \r |
| 5 | // which accompanies this distribution. The full text of the license may be found at \r |
| 6 | // http://opensource.org/licenses/bsd-license.php \r |
| 7 | // \r |
| 8 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 9 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 10 | // \r |
| 11 | // Module Name:\r |
| 12 | // \r |
| 13 | // IpfCpuCore.i\r |
| 14 | //\r |
| 15 | // Abstract:\r |
| 16 | // IPF CPU definitions\r |
| 17 | //\r |
| 18 | //--\r |
| 19 | \r |
| 20 | #ifndef _IPF_CPU_CORE_\r |
| 21 | #define _IPF_CPU_CORE_\r |
| 22 | \r |
| 192f6d4c |
23 | #define PEI_BSP_STORE_SIZE 0x4000\r |
| 24 | #define ResetFn 0x00\r |
| 25 | #define MachineCheckFn 0x01\r |
| 26 | #define InitFn 0x02\r |
| 27 | #define RecoveryFn 0x03\r |
| 28 | #define GuardBand 0x10 \r |
| 29 | \r |
| 30 | //\r |
| 31 | // Define hardware RSE Configuration Register\r |
| 32 | //\r |
| 33 | \r |
| 34 | //\r |
| 35 | // RS Configuration (RSC) bit field positions\r |
| 36 | //\r |
| 37 | #define RSC_MODE 0\r |
| 38 | #define RSC_PL 2\r |
| 39 | #define RSC_BE 4\r |
| 40 | //\r |
| 41 | // RSC bits 5-15 reserved\r |
| 42 | //\r |
| 43 | #define RSC_MBZ0 5\r |
| 44 | #define RSC_MBZ0_V 0x3ff\r |
| 45 | #define RSC_LOADRS 16\r |
| 46 | #define RSC_LOADRS_LEN 14\r |
| 47 | //\r |
| 48 | // RSC bits 30-63 reserved\r |
| 49 | //\r |
| 50 | #define RSC_MBZ1 30\r |
| 51 | #define RSC_MBZ1_V 0x3ffffffffULL\r |
| 52 | \r |
| 53 | //\r |
| 54 | // RSC modes\r |
| 55 | //\r |
| 56 | \r |
| 57 | //\r |
| 58 | // Lazy\r |
| 59 | //\r |
| 60 | #define RSC_MODE_LY (0x0)\r |
| 61 | //\r |
| 62 | // Store intensive\r |
| 63 | //\r |
| 64 | #define RSC_MODE_SI (0x1)\r |
| 65 | //\r |
| 66 | // Load intensive\r |
| 67 | //\r |
| 68 | #define RSC_MODE_LI (0x2)\r |
| 69 | //\r |
| 70 | // Eager\r |
| 71 | //\r |
| 72 | #define RSC_MODE_EA (0x3)\r |
| 73 | \r |
| 74 | //\r |
| 75 | // RSC Endian bit values\r |
| 76 | //\r |
| 77 | #define RSC_BE_LITTLE 0\r |
| 78 | #define RSC_BE_BIG 1\r |
| 79 | \r |
| 80 | //\r |
| 81 | // RSC while in kernel: enabled, little endian, pl = 0, eager mode\r |
| 82 | //\r |
| 83 | #define RSC_KERNEL ((RSC_MODE_EA<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))\r |
| 84 | //\r |
| 85 | // Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode\r |
| 86 | //\r |
| 87 | #define RSC_KERNEL_LAZ ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))\r |
| 88 | //\r |
| 89 | // RSE disabled: disabled, pl = 0, little endian, eager mode\r |
| 90 | //\r |
| 91 | #define RSC_KERNEL_DISABLED ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))\r |
| 92 | \r |
| 93 | #endif\r |
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