MdeModulePkg/PciHostBridgeLib.h: add address Translation
[mirror_edk2.git] / MdeModulePkg / Include / Library / PciHostBridgeLib.h
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1/** @file\r
2 PCI Host Bridge Library consumed by PciHostBridgeDxe driver returning\r
3 the platform specific information about the PCI Host Bridge.\r
4\r
5 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
6 This program and the accompanying materials are\r
7 licensed and made available under the terms and conditions of\r
8 the BSD License which accompanies this distribution. The full\r
9 text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php.\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16#ifndef __PCI_HOST_BRIDGE_LIB_H__\r
17#define __PCI_HOST_BRIDGE_LIB_H__\r
18\r
19//\r
20// (Base > Limit) indicates an aperture is not available.\r
21//\r
22typedef struct {\r
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23 //\r
24 // Base and Limit are the device address instead of host address when\r
25 // Translation is not zero\r
26 //\r
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27 UINT64 Base;\r
28 UINT64 Limit;\r
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29 //\r
30 // According to UEFI 2.7, Device Address = Host Address + Translation,\r
31 // so Translation = Device Address - Host Address.\r
32 // On platforms where Translation is not zero, the subtraction is probably to\r
33 // be performed with UINT64 wrap-around semantics, for we may translate an\r
34 // above-4G host address into a below-4G device address for legacy PCIe device\r
35 // compatibility.\r
36 //\r
37 // NOTE: The alignment of Translation is required to be larger than any BAR\r
38 // alignment in the same root bridge, so that the same alignment can be\r
39 // applied to both device address and host address, which simplifies the\r
40 // situation and makes the current resource allocation code in generic PCI\r
41 // host bridge driver still work.\r
42 //\r
43 UINT64 Translation;\r
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44} PCI_ROOT_BRIDGE_APERTURE;\r
45\r
46typedef struct {\r
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47 UINT32 Segment; ///< Segment number.\r
48 UINT64 Supports; ///< Supported attributes.\r
49 ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
50 ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
51 UINT64 Attributes; ///< Initial attributes.\r
52 ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
53 ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
54 BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.\r
55 ///< Set to TRUE when root bridge supports DMA above 4GB memory.\r
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56 BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root bridge supports\r
57 ///< Extended (4096-byte) Configuration Space.\r
58 ///< When TRUE, the root bridge supports\r
59 ///< 256-byte Configuration Space only.\r
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60 BOOLEAN ResourceAssigned; ///< Resource assignment status of the root bridge.\r
61 ///< Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned.\r
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62 UINT64 AllocationAttributes; ///< Allocation attributes.\r
63 ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and\r
64 ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()\r
65 ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
66 PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can be used by the root bridge.\r
67 PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be used by the root bridge.\r
68 PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below 4GB which can be used by the root bridge.\r
69 PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above 4GB which can be used by the root bridge.\r
70 PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.\r
71 PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.\r
72 EFI_DEVICE_PATH_PROTOCOL *DevicePath; ///< Device path.\r
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73} PCI_ROOT_BRIDGE;\r
74\r
75/**\r
76 Return all the root bridge instances in an array.\r
77\r
78 @param Count Return the count of root bridge instances.\r
79\r
80 @return All the root bridge instances in an array.\r
81 The array should be passed into PciHostBridgeFreeRootBridges()\r
82 when it's not used.\r
83**/\r
84PCI_ROOT_BRIDGE *\r
85EFIAPI\r
86PciHostBridgeGetRootBridges (\r
87 UINTN *Count\r
88 );\r
89\r
90/**\r
91 Free the root bridge instances array returned from PciHostBridgeGetRootBridges().\r
92\r
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93 @param Bridges The root bridge instances array.\r
94 @param Count The count of the array.\r
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95**/\r
96VOID\r
97EFIAPI\r
98PciHostBridgeFreeRootBridges (\r
99 PCI_ROOT_BRIDGE *Bridges,\r
100 UINTN Count\r
101 );\r
102\r
103/**\r
104 Inform the platform that the resource conflict happens.\r
105\r
106 @param HostBridgeHandle Handle of the Host Bridge.\r
107 @param Configuration Pointer to PCI I/O and PCI memory resource descriptors.\r
108 The Configuration contains the resources for all the\r
109 root bridges. The resource for each root bridge is\r
110 terminated with END descriptor and an additional END\r
111 is appended indicating the end of the entire resources.\r
112 The resource descriptor field values follow the description\r
113 in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SubmitResources().\r
114**/\r
115VOID\r
116EFIAPI\r
117PciHostBridgeResourceConflict (\r
118 EFI_HANDLE HostBridgeHandle,\r
119 VOID *Configuration\r
120 );\r
121\r
122#endif\r