[mirror_edk2.git] / MdeModulePkg / Universal / Acpi / BootScriptExecutorDxe / X64 / SetIdtEntry.c

/** @file\r
  Set a IDT entry for debug purpose\r
\r
  Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform\r
\r
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
#include "ScriptExecute.h"\r
\r
//\r
// 8 extra pages for PF handler.\r
//\r
#define EXTRA_PAGE_TABLE_PAGES      8\r
\r
#define IA32_PG_P                   BIT0\r
#define IA32_PG_RW                  BIT1\r
#define IA32_PG_PS                  BIT7\r
\r
UINT64                              mPhyMask;\r
VOID                                *mOriginalHandler;\r
UINTN                               mPageFaultBuffer;\r
UINTN                               mPageFaultIndex = 0;\r
//\r
// Store the uplink information for each page being used.\r
//\r
UINT64                              *mPageFaultUplink[EXTRA_PAGE_TABLE_PAGES];\r
\r
/**\r
  Page fault handler.\r
\r
**/\r
VOID\r
EFIAPI\r
PageFaultHandlerHook (\r
  VOID\r
  );\r
\r
/**\r
  Hook IDT with our page fault handler so that the on-demand paging works on page fault.\r
\r
  @param  IdtEntry  a pointer to IDT entry\r
\r
**/\r
VOID\r
HookPageFaultHandler (\r
  IN IA32_IDT_GATE_DESCRIPTOR                   *IdtEntry\r
  )\r
{\r
  UINT32         RegEax;\r
  UINT8          PhysicalAddressBits;\r
  UINTN          PageFaultHandlerHookAddress;\r
\r
  AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
  if (RegEax >= 0x80000008) {\r
    AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
    PhysicalAddressBits = (UINT8) RegEax;\r
  } else {\r
    PhysicalAddressBits = 36;\r
  }\r
  mPhyMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r
  mPhyMask &= (1ull << 48) - SIZE_4KB;\r
\r
  //\r
  // Set Page Fault entry to catch >4G access\r
  //\r
  PageFaultHandlerHookAddress = (UINTN)PageFaultHandlerHook;\r
  mOriginalHandler = (VOID *)(UINTN)(LShiftU64 (IdtEntry->Bits.OffsetUpper, 32) + IdtEntry->Bits.OffsetLow + (IdtEntry->Bits.OffsetHigh << 16));\r
  IdtEntry->Bits.OffsetLow      = (UINT16)PageFaultHandlerHookAddress;\r
  IdtEntry->Bits.Selector       = (UINT16)AsmReadCs ();\r
  IdtEntry->Bits.Reserved_0     = 0;\r
  IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
  IdtEntry->Bits.OffsetHigh     = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
  IdtEntry->Bits.OffsetUpper    = (UINT32)(PageFaultHandlerHookAddress >> 32);\r
  IdtEntry->Bits.Reserved_1     = 0;\r
\r
  if (mPage1GSupport) {\r
    mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(2);\r
  }else {\r
    mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(6);\r
  }\r
  ZeroMem (mPageFaultUplink, sizeof (mPageFaultUplink));\r
}\r
\r
/**\r
  The function will check if current waking vector is long mode.\r
\r
  @param  AcpiS3Context                 a pointer to a structure of ACPI_S3_CONTEXT\r
\r
  @retval TRUE   Current context need long mode waking vector.\r
  @retval FALSE  Current context need not long mode waking vector.\r
**/\r
BOOLEAN\r
IsLongModeWakingVector (\r
  IN ACPI_S3_CONTEXT                *AcpiS3Context\r
  )\r
{\r
  EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE  *Facs;\r
\r
  Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable));\r
  if ((Facs == NULL) ||\r
      (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ||\r
      ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {\r
    // Something wrong with FACS\r
    return FALSE;\r
  }\r
  if (Facs->XFirmwareWakingVector != 0) {\r
    if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&\r
        ((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&\r
        ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {\r
      // Both BIOS and OS wants 64bit vector\r
      if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
        return TRUE;\r
      }\r
    }\r
  }\r
  return FALSE;\r
}\r
\r
/**\r
  Set a IDT entry for interrupt vector 3 for debug purpose.\r
\r
  @param  AcpiS3Context  a pointer to a structure of ACPI_S3_CONTEXT\r
\r
**/\r
VOID\r
SetIdtEntry (\r
  IN ACPI_S3_CONTEXT     *AcpiS3Context\r
  )\r
{\r
  IA32_IDT_GATE_DESCRIPTOR                      *IdtEntry;\r
  IA32_DESCRIPTOR                               *IdtDescriptor;\r
  UINTN                                         S3DebugBuffer;\r
  EFI_STATUS                                    Status;\r
\r
  //\r
  // Restore IDT for debug\r
  //\r
  IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);\r
  AsmWriteIdtr (IdtDescriptor);\r
\r
  //\r
  // Setup the default CPU exception handlers\r
  //\r
  Status = InitializeCpuExceptionHandlers (NULL);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  DEBUG_CODE (\r
    //\r
    // Update IDT entry INT3 if the instruction is valid in it\r
    //\r
    S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);\r
    if (*(UINTN *)S3DebugBuffer != (UINTN) -1) {\r
      IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
      IdtEntry->Bits.OffsetLow      = (UINT16)S3DebugBuffer;\r
      IdtEntry->Bits.Selector       = (UINT16)AsmReadCs ();\r
      IdtEntry->Bits.Reserved_0     = 0;\r
      IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
      IdtEntry->Bits.OffsetHigh     = (UINT16)(S3DebugBuffer >> 16);\r
      IdtEntry->Bits.OffsetUpper    = (UINT32)(S3DebugBuffer >> 32);\r
      IdtEntry->Bits.Reserved_1     = 0;\r
    }\r
  );\r
\r
  //\r
  // If both BIOS and OS wants long mode waking vector,\r
  // S3ResumePei should have established 1:1 Virtual to Physical identity mapping page table,\r
  // no need to hook page fault handler.\r
  //\r
  if (!IsLongModeWakingVector (AcpiS3Context)) {\r
    IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
    HookPageFaultHandler (IdtEntry);\r
  }\r
}\r
\r
/**\r
  Acquire page for page fault.\r
\r
  @param[in, out] Uplink        Pointer to up page table entry.\r
\r
**/\r
VOID\r
AcquirePage (\r
  IN OUT UINT64                 *Uplink\r
  )\r
{\r
  UINTN             Address;\r
\r
  Address = mPageFaultBuffer + EFI_PAGES_TO_SIZE (mPageFaultIndex);\r
  ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1));\r
\r
  //\r
  // Cut the previous uplink if it exists and wasn't overwritten.\r
  //\r
  if ((mPageFaultUplink[mPageFaultIndex] != NULL) &&\r
     ((*mPageFaultUplink[mPageFaultIndex] & ~mAddressEncMask & mPhyMask) == Address)) {\r
    *mPageFaultUplink[mPageFaultIndex] = 0;\r
  }\r
\r
  //\r
  // Link & Record the current uplink.\r
  //\r
  *Uplink = Address | mAddressEncMask | IA32_PG_P | IA32_PG_RW;\r
  mPageFaultUplink[mPageFaultIndex] = Uplink;\r
\r
  mPageFaultIndex = (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;\r
}\r
\r
/**\r
  The page fault handler that on-demand read >4G memory/MMIO.\r
\r
  @retval TRUE     The page fault is correctly handled.\r
  @retval FALSE    The page fault is not handled and is passed through to original handler.\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
PageFaultHandler (\r
  VOID\r
  )\r
{\r
  UINT64         *PageTable;\r
  UINT64         PFAddress;\r
  UINTN          PTIndex;\r
\r
  PFAddress = AsmReadCr2 ();\r
  DEBUG ((DEBUG_INFO, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));\r
\r
  if (PFAddress >= mPhyMask + SIZE_4KB) {\r
    return FALSE;\r
  }\r
  PFAddress &= mPhyMask;\r
\r
  PageTable = (UINT64*)(UINTN)(AsmReadCr3 () & mPhyMask);\r
\r
  PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
  // PML4E\r
  if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
    AcquirePage (&PageTable[PTIndex]);\r
  }\r
  PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
  PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
  // PDPTE\r
  if (mPage1GSupport) {\r
    PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
  } else {\r
    if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
      AcquirePage (&PageTable[PTIndex]);\r
    }\r
    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
    PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
    // PD\r
    PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
  }\r
\r
  return TRUE;\r
}\r
Commit	Line	Data
be46cd5f	1	/** @file\r
	2	Set a IDT entry for debug purpose\r
	3	\r
	4	Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform\r
	5	\r
306a5836	6	Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
ab1a5a58 LD	7	Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
ab1a5a58 LD	8	\r
be46cd5f	9	\r
	10	This program and the accompanying materials\r
	11	are licensed and made available under the terms and conditions of the BSD License\r
	12	which accompanies this distribution. The full text of the license may be found at\r
	13	http://opensource.org/licenses/bsd-license.php\r
	14	\r
	15	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	16	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	17	\r
	18	**/\r
	19	#include "ScriptExecute.h"\r
d0bf5623	20	\r
c6368abc SZ	21	//\r
	22	// 8 extra pages for PF handler.\r
	23	//\r
	24	#define EXTRA_PAGE_TABLE_PAGES 8\r
	25	\r
d0bf5623 JY	26	#define IA32_PG_P BIT0\r
	27	#define IA32_PG_RW BIT1\r
	28	#define IA32_PG_PS BIT7\r
	29	\r
c6368abc SZ	30	UINT64 mPhyMask;\r
	31	VOID *mOriginalHandler;\r
	32	UINTN mPageFaultBuffer;\r
	33	UINTN mPageFaultIndex = 0;\r
	34	//\r
	35	// Store the uplink information for each page being used.\r
	36	//\r
	37	UINT64 *mPageFaultUplink[EXTRA_PAGE_TABLE_PAGES];\r
d0bf5623	38	\r
54e27ada JY	39	/**\r
	40	Page fault handler.\r
	41	\r
	42	**/\r
d0bf5623 JY	43	VOID\r
	44	EFIAPI\r
	45	PageFaultHandlerHook (\r
	46	VOID\r
	47	);\r
	48	\r
54e27ada JY	49	/**\r
	50	Hook IDT with our page fault handler so that the on-demand paging works on page fault.\r
	51	\r
	52	@param IdtEntry a pointer to IDT entry\r
	53	\r
	54	**/\r
d0bf5623 JY	55	VOID\r
d0bf5623 JY	56	HookPageFaultHandler (\r
68cc1ba3	57	IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry\r
d0bf5623 JY	58	)\r
	59	{\r
	60	UINT32 RegEax;\r
59cc677c	61	UINT8 PhysicalAddressBits;\r
73f0127f	62	UINTN PageFaultHandlerHookAddress;\r
d0bf5623	63	\r
59cc677c SZ	64	AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
	65	if (RegEax >= 0x80000008) {\r
	66	AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
	67	PhysicalAddressBits = (UINT8) RegEax;\r
	68	} else {\r
	69	PhysicalAddressBits = 36;\r
d0bf5623	70	}\r
59cc677c SZ	71	mPhyMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r
59cc677c SZ	72	mPhyMask &= (1ull << 48) - SIZE_4KB;\r
d0bf5623 JY	73	\r
	74	//\r
	75	// Set Page Fault entry to catch >4G access\r
	76	//\r
73f0127f	77	PageFaultHandlerHookAddress = (UINTN)PageFaultHandlerHook;\r
68cc1ba3	78	mOriginalHandler = (VOID *)(UINTN)(LShiftU64 (IdtEntry->Bits.OffsetUpper, 32) + IdtEntry->Bits.OffsetLow + (IdtEntry->Bits.OffsetHigh << 16));\r
73f0127f	79	IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;\r
68cc1ba3 SZ	80	IdtEntry->Bits.Selector = (UINT16)AsmReadCs ();\r
	81	IdtEntry->Bits.Reserved_0 = 0;\r
	82	IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
73f0127f SZ	83	IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
73f0127f SZ	84	IdtEntry->Bits.OffsetUpper = (UINT32)(PageFaultHandlerHookAddress >> 32);\r
68cc1ba3	85	IdtEntry->Bits.Reserved_1 = 0;\r
d0bf5623 JY	86	\r
d0bf5623 JY	87	if (mPage1GSupport) {\r
c6368abc	88	mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(2);\r
d0bf5623	89	}else {\r
c6368abc SZ	90	mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(6);\r
	91	}\r
	92	ZeroMem (mPageFaultUplink, sizeof (mPageFaultUplink));\r
	93	}\r
	94	\r
	95	/**\r
	96	The function will check if current waking vector is long mode.\r
	97	\r
	98	@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT\r
	99	\r
	100	@retval TRUE Current context need long mode waking vector.\r
	101	@retval FALSE Current context need not long mode waking vector.\r
	102	**/\r
	103	BOOLEAN\r
	104	IsLongModeWakingVector (\r
	105	IN ACPI_S3_CONTEXT *AcpiS3Context\r
	106	)\r
	107	{\r
	108	EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *Facs;\r
	109	\r
	110	Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable));\r
	111	if ((Facs == NULL) \|\|\r
	112	(Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) \|\|\r
	113	((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {\r
	114	// Something wrong with FACS\r
	115	return FALSE;\r
	116	}\r
	117	if (Facs->XFirmwareWakingVector != 0) {\r
	118	if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&\r
	119	((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&\r
306a5836	120	((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {\r
c6368abc SZ	121	// Both BIOS and OS wants 64bit vector\r
	122	if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
	123	return TRUE;\r
	124	}\r
	125	}\r
d0bf5623	126	}\r
c6368abc	127	return FALSE;\r
d0bf5623 JY	128	}\r
d0bf5623 JY	129	\r
be46cd5f	130	/**\r
	131	Set a IDT entry for interrupt vector 3 for debug purpose.\r
	132	\r
	133	@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT\r
	134	\r
	135	**/\r
	136	VOID\r
	137	SetIdtEntry (\r
	138	IN ACPI_S3_CONTEXT *AcpiS3Context\r
	139	)\r
	140	{\r
68cc1ba3	141	IA32_IDT_GATE_DESCRIPTOR *IdtEntry;\r
be46cd5f	142	IA32_DESCRIPTOR *IdtDescriptor;\r
be46cd5f	143	UINTN S3DebugBuffer;\r
57f360f2	144	EFI_STATUS Status;\r
be46cd5f	145	\r
	146	//\r
	147	// Restore IDT for debug\r
	148	//\r
	149	IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);\r
1e172d6b	150	AsmWriteIdtr (IdtDescriptor);\r
	151	\r
	152	//\r
	153	// Setup the default CPU exception handlers\r
	154	//\r
57f360f2 JF	155	Status = InitializeCpuExceptionHandlers (NULL);\r
57f360f2 JF	156	ASSERT_EFI_ERROR (Status);\r
1e172d6b	157	\r
f4a25e81	158	DEBUG_CODE (\r
	159	//\r
	160	// Update IDT entry INT3 if the instruction is valid in it\r
	161	//\r
	162	S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);\r
	163	if ((UINTN )S3DebugBuffer != (UINTN) -1) {\r
68cc1ba3 SZ	164	IdtEntry = (IA32_IDT_GATE_DESCRIPTOR )(IdtDescriptor->Base + (3 sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
	165	IdtEntry->Bits.OffsetLow = (UINT16)S3DebugBuffer;\r
	166	IdtEntry->Bits.Selector = (UINT16)AsmReadCs ();\r
	167	IdtEntry->Bits.Reserved_0 = 0;\r
	168	IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
	169	IdtEntry->Bits.OffsetHigh = (UINT16)(S3DebugBuffer >> 16);\r
	170	IdtEntry->Bits.OffsetUpper = (UINT32)(S3DebugBuffer >> 32);\r
	171	IdtEntry->Bits.Reserved_1 = 0;\r
f4a25e81	172	}\r
f4a25e81	173	);\r
be46cd5f	174	\r
c6368abc SZ	175	//\r
	176	// If both BIOS and OS wants long mode waking vector,\r
	177	// S3ResumePei should have established 1:1 Virtual to Physical identity mapping page table,\r
	178	// no need to hook page fault handler.\r
	179	//\r
	180	if (!IsLongModeWakingVector (AcpiS3Context)) {\r
	181	IdtEntry = (IA32_IDT_GATE_DESCRIPTOR )(IdtDescriptor->Base + (14 sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
	182	HookPageFaultHandler (IdtEntry);\r
	183	}\r
d0bf5623 JY	184	}\r
d0bf5623 JY	185	\r
54e27ada	186	/**\r
c6368abc	187	Acquire page for page fault.\r
54e27ada	188	\r
c6368abc	189	@param[in, out] Uplink Pointer to up page table entry.\r
54e27ada	190	\r
54e27ada	191	**/\r
c6368abc SZ	192	VOID\r
	193	AcquirePage (\r
	194	IN OUT UINT64 *Uplink\r
d0bf5623 JY	195	)\r
d0bf5623 JY	196	{\r
c6368abc SZ	197	UINTN Address;\r
	198	\r
	199	Address = mPageFaultBuffer + EFI_PAGES_TO_SIZE (mPageFaultIndex);\r
	200	ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1));\r
	201	\r
	202	//\r
	203	// Cut the previous uplink if it exists and wasn't overwritten.\r
	204	//\r
ab1a5a58 LD	205	if ((mPageFaultUplink[mPageFaultIndex] != NULL) &&\r
ab1a5a58 LD	206	((*mPageFaultUplink[mPageFaultIndex] & ~mAddressEncMask & mPhyMask) == Address)) {\r
c6368abc SZ	207	*mPageFaultUplink[mPageFaultIndex] = 0;\r
	208	}\r
	209	\r
	210	//\r
	211	// Link & Record the current uplink.\r
	212	//\r
ab1a5a58	213	*Uplink = Address \| mAddressEncMask \| IA32_PG_P \| IA32_PG_RW;\r
c6368abc SZ	214	mPageFaultUplink[mPageFaultIndex] = Uplink;\r
	215	\r
	216	mPageFaultIndex = (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;\r
be46cd5f	217	}\r
be46cd5f	218	\r
54e27ada JY	219	/**\r
54e27ada JY	220	The page fault handler that on-demand read >4G memory/MMIO.\r
d1102dba	221	\r
54e27ada JY	222	@retval TRUE The page fault is correctly handled.\r
	223	@retval FALSE The page fault is not handled and is passed through to original handler.\r
	224	\r
	225	**/\r
d0bf5623 JY	226	BOOLEAN\r
	227	EFIAPI\r
	228	PageFaultHandler (\r
	229	VOID\r
	230	)\r
	231	{\r
	232	UINT64 *PageTable;\r
	233	UINT64 PFAddress;\r
	234	UINTN PTIndex;\r
	235	\r
	236	PFAddress = AsmReadCr2 ();\r
558f58e3	237	DEBUG ((DEBUG_INFO, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));\r
d0bf5623 JY	238	\r
	239	if (PFAddress >= mPhyMask + SIZE_4KB) {\r
	240	return FALSE;\r
	241	}\r
	242	PFAddress &= mPhyMask;\r
	243	\r
	244	PageTable = (UINT64*)(UINTN)(AsmReadCr3 () & mPhyMask);\r
	245	\r
	246	PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
	247	// PML4E\r
	248	if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
c6368abc	249	AcquirePage (&PageTable[PTIndex]);\r
d0bf5623	250	}\r
ab1a5a58	251	PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
d0bf5623 JY	252	PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
	253	// PDPTE\r
	254	if (mPage1GSupport) {\r
ab1a5a58	255	PageTable[PTIndex] = ((PFAddress \| mAddressEncMask) & ~((1ull << 30) - 1)) \| IA32_PG_P \| IA32_PG_RW \| IA32_PG_PS;\r
d0bf5623 JY	256	} else {\r
d0bf5623 JY	257	if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
c6368abc	258	AcquirePage (&PageTable[PTIndex]);\r
d0bf5623	259	}\r
ab1a5a58	260	PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
d0bf5623 JY	261	PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
d0bf5623 JY	262	// PD\r
ab1a5a58	263	PageTable[PTIndex] = ((PFAddress \| mAddressEncMask) & ~((1ull << 21) - 1)) \| IA32_PG_P \| IA32_PG_RW \| IA32_PG_PS;\r
d0bf5623 JY	264	}\r
	265	\r
	266	return TRUE;\r
	267	}\r