[mirror_edk2.git] / MdeModulePkg / Universal / Acpi / BootScriptExecutorDxe / X64 / SetIdtEntry.c

/** @file\r
  Set a IDT entry for debug purpose\r
\r
  Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform\r
\r
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#include "ScriptExecute.h"\r
\r
//\r
// 8 extra pages for PF handler.\r
//\r
#define EXTRA_PAGE_TABLE_PAGES      8\r
\r
#define IA32_PG_P                   BIT0\r
#define IA32_PG_RW                  BIT1\r
#define IA32_PG_PS                  BIT7\r
\r
UINT64                              mPhyMask;\r
VOID                                *mOriginalHandler;\r
UINTN                               mPageFaultBuffer;\r
UINTN                               mPageFaultIndex = 0;\r
//\r
// Store the uplink information for each page being used.\r
//\r
UINT64                              *mPageFaultUplink[EXTRA_PAGE_TABLE_PAGES];\r
\r
/**\r
  Page fault handler.\r
\r
**/\r
VOID\r
EFIAPI\r
PageFaultHandlerHook (\r
  VOID\r
  );\r
\r
/**\r
  Hook IDT with our page fault handler so that the on-demand paging works on page fault.\r
\r
  @param  IdtEntry  a pointer to IDT entry\r
\r
**/\r
VOID\r
HookPageFaultHandler (\r
  IN IA32_IDT_GATE_DESCRIPTOR                   *IdtEntry\r
  )\r
{\r
  UINT32         RegEax;\r
  UINT8          PhysicalAddressBits;\r
  UINTN          PageFaultHandlerHookAddress;\r
\r
  AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
  if (RegEax >= 0x80000008) {\r
    AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
    PhysicalAddressBits = (UINT8) RegEax;\r
  } else {\r
    PhysicalAddressBits = 36;\r
  }\r
  mPhyMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r
  mPhyMask &= (1ull << 48) - SIZE_4KB;\r
\r
  //\r
  // Set Page Fault entry to catch >4G access\r
  //\r
  PageFaultHandlerHookAddress = (UINTN)PageFaultHandlerHook;\r
  mOriginalHandler = (VOID *)(UINTN)(LShiftU64 (IdtEntry->Bits.OffsetUpper, 32) + IdtEntry->Bits.OffsetLow + (IdtEntry->Bits.OffsetHigh << 16));\r
  IdtEntry->Bits.OffsetLow      = (UINT16)PageFaultHandlerHookAddress;\r
  IdtEntry->Bits.Selector       = (UINT16)AsmReadCs ();\r
  IdtEntry->Bits.Reserved_0     = 0;\r
  IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
  IdtEntry->Bits.OffsetHigh     = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
  IdtEntry->Bits.OffsetUpper    = (UINT32)(PageFaultHandlerHookAddress >> 32);\r
  IdtEntry->Bits.Reserved_1     = 0;\r
\r
  if (mPage1GSupport) {\r
    mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(2);\r
  }else {\r
    mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(6);\r
  }\r
  ZeroMem (mPageFaultUplink, sizeof (mPageFaultUplink));\r
}\r
\r
/**\r
  The function will check if current waking vector is long mode.\r
\r
  @param  AcpiS3Context                 a pointer to a structure of ACPI_S3_CONTEXT\r
\r
  @retval TRUE   Current context need long mode waking vector.\r
  @retval FALSE  Current context need not long mode waking vector.\r
**/\r
BOOLEAN\r
IsLongModeWakingVector (\r
  IN ACPI_S3_CONTEXT                *AcpiS3Context\r
  )\r
{\r
  EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE  *Facs;\r
\r
  Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable));\r
  if ((Facs == NULL) ||\r
      (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ||\r
      ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {\r
    // Something wrong with FACS\r
    return FALSE;\r
  }\r
  if (Facs->XFirmwareWakingVector != 0) {\r
    if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&\r
        ((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&\r
        ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {\r
      // Both BIOS and OS wants 64bit vector\r
      if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
        return TRUE;\r
      }\r
    }\r
  }\r
  return FALSE;\r
}\r
\r
/**\r
  Set a IDT entry for interrupt vector 3 for debug purpose.\r
\r
  @param  AcpiS3Context  a pointer to a structure of ACPI_S3_CONTEXT\r
\r
**/\r
VOID\r
SetIdtEntry (\r
  IN ACPI_S3_CONTEXT     *AcpiS3Context\r
  )\r
{\r
  IA32_IDT_GATE_DESCRIPTOR                      *IdtEntry;\r
  IA32_DESCRIPTOR                               *IdtDescriptor;\r
  UINTN                                         S3DebugBuffer;\r
  EFI_STATUS                                    Status;\r
\r
  //\r
  // Restore IDT for debug\r
  //\r
  IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);\r
  AsmWriteIdtr (IdtDescriptor);\r
\r
  //\r
  // Setup the default CPU exception handlers\r
  //\r
  Status = InitializeCpuExceptionHandlers (NULL);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  DEBUG_CODE (\r
    //\r
    // Update IDT entry INT3 if the instruction is valid in it\r
    //\r
    S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);\r
    if (*(UINTN *)S3DebugBuffer != (UINTN) -1) {\r
      IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
      IdtEntry->Bits.OffsetLow      = (UINT16)S3DebugBuffer;\r
      IdtEntry->Bits.Selector       = (UINT16)AsmReadCs ();\r
      IdtEntry->Bits.Reserved_0     = 0;\r
      IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
      IdtEntry->Bits.OffsetHigh     = (UINT16)(S3DebugBuffer >> 16);\r
      IdtEntry->Bits.OffsetUpper    = (UINT32)(S3DebugBuffer >> 32);\r
      IdtEntry->Bits.Reserved_1     = 0;\r
    }\r
  );\r
\r
  //\r
  // If both BIOS and OS wants long mode waking vector,\r
  // S3ResumePei should have established 1:1 Virtual to Physical identity mapping page table,\r
  // no need to hook page fault handler.\r
  //\r
  if (!IsLongModeWakingVector (AcpiS3Context)) {\r
    IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
    HookPageFaultHandler (IdtEntry);\r
  }\r
}\r
\r
/**\r
  Acquire page for page fault.\r
\r
  @param[in, out] Uplink        Pointer to up page table entry.\r
\r
**/\r
VOID\r
AcquirePage (\r
  IN OUT UINT64                 *Uplink\r
  )\r
{\r
  UINTN             Address;\r
\r
  Address = mPageFaultBuffer + EFI_PAGES_TO_SIZE (mPageFaultIndex);\r
  ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1));\r
\r
  //\r
  // Cut the previous uplink if it exists and wasn't overwritten.\r
  //\r
  if ((mPageFaultUplink[mPageFaultIndex] != NULL) &&\r
     ((*mPageFaultUplink[mPageFaultIndex] & ~mAddressEncMask & mPhyMask) == Address)) {\r
    *mPageFaultUplink[mPageFaultIndex] = 0;\r
  }\r
\r
  //\r
  // Link & Record the current uplink.\r
  //\r
  *Uplink = Address | mAddressEncMask | IA32_PG_P | IA32_PG_RW;\r
  mPageFaultUplink[mPageFaultIndex] = Uplink;\r
\r
  mPageFaultIndex = (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;\r
}\r
\r
/**\r
  The page fault handler that on-demand read >4G memory/MMIO.\r
\r
  @retval TRUE     The page fault is correctly handled.\r
  @retval FALSE    The page fault is not handled and is passed through to original handler.\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
PageFaultHandler (\r
  VOID\r
  )\r
{\r
  UINT64         *PageTable;\r
  UINT64         PFAddress;\r
  UINTN          PTIndex;\r
\r
  PFAddress = AsmReadCr2 ();\r
  DEBUG ((DEBUG_INFO, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));\r
\r
  if (PFAddress >= mPhyMask + SIZE_4KB) {\r
    return FALSE;\r
  }\r
  PFAddress &= mPhyMask;\r
\r
  PageTable = (UINT64*)(UINTN)(AsmReadCr3 () & mPhyMask);\r
\r
  PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
  // PML4E\r
  if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
    AcquirePage (&PageTable[PTIndex]);\r
  }\r
  PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
  PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
  // PDPTE\r
  if (mPage1GSupport) {\r
    PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
  } else {\r
    if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
      AcquirePage (&PageTable[PTIndex]);\r
    }\r
    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
    PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
    // PD\r
    PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;\r
  }\r
\r
  return TRUE;\r
}\r
Commit	Line	Data
be46cd5f	1	/** @file\r
	2	Set a IDT entry for debug purpose\r
	3	\r
	4	Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform\r
	5	\r
306a5836	6	Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
ab1a5a58 LD	7	Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
ab1a5a58 LD	8	\r
be46cd5f	9	\r
9d510e61	10	SPDX-License-Identifier: BSD-2-Clause-Patent\r
be46cd5f	11	\r
	12	**/\r
	13	#include "ScriptExecute.h"\r
d0bf5623	14	\r
c6368abc SZ	15	//\r
	16	// 8 extra pages for PF handler.\r
	17	//\r
	18	#define EXTRA_PAGE_TABLE_PAGES 8\r
	19	\r
d0bf5623 JY	20	#define IA32_PG_P BIT0\r
	21	#define IA32_PG_RW BIT1\r
	22	#define IA32_PG_PS BIT7\r
	23	\r
c6368abc SZ	24	UINT64 mPhyMask;\r
	25	VOID *mOriginalHandler;\r
	26	UINTN mPageFaultBuffer;\r
	27	UINTN mPageFaultIndex = 0;\r
	28	//\r
	29	// Store the uplink information for each page being used.\r
	30	//\r
	31	UINT64 *mPageFaultUplink[EXTRA_PAGE_TABLE_PAGES];\r
d0bf5623	32	\r
54e27ada JY	33	/**\r
	34	Page fault handler.\r
	35	\r
	36	**/\r
d0bf5623 JY	37	VOID\r
	38	EFIAPI\r
	39	PageFaultHandlerHook (\r
	40	VOID\r
	41	);\r
	42	\r
54e27ada JY	43	/**\r
	44	Hook IDT with our page fault handler so that the on-demand paging works on page fault.\r
	45	\r
	46	@param IdtEntry a pointer to IDT entry\r
	47	\r
	48	**/\r
d0bf5623 JY	49	VOID\r
d0bf5623 JY	50	HookPageFaultHandler (\r
68cc1ba3	51	IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry\r
d0bf5623 JY	52	)\r
	53	{\r
	54	UINT32 RegEax;\r
59cc677c	55	UINT8 PhysicalAddressBits;\r
73f0127f	56	UINTN PageFaultHandlerHookAddress;\r
d0bf5623	57	\r
59cc677c SZ	58	AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
	59	if (RegEax >= 0x80000008) {\r
	60	AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
	61	PhysicalAddressBits = (UINT8) RegEax;\r
	62	} else {\r
	63	PhysicalAddressBits = 36;\r
d0bf5623	64	}\r
59cc677c SZ	65	mPhyMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r
59cc677c SZ	66	mPhyMask &= (1ull << 48) - SIZE_4KB;\r
d0bf5623 JY	67	\r
	68	//\r
	69	// Set Page Fault entry to catch >4G access\r
	70	//\r
73f0127f	71	PageFaultHandlerHookAddress = (UINTN)PageFaultHandlerHook;\r
68cc1ba3	72	mOriginalHandler = (VOID *)(UINTN)(LShiftU64 (IdtEntry->Bits.OffsetUpper, 32) + IdtEntry->Bits.OffsetLow + (IdtEntry->Bits.OffsetHigh << 16));\r
73f0127f	73	IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;\r
68cc1ba3 SZ	74	IdtEntry->Bits.Selector = (UINT16)AsmReadCs ();\r
	75	IdtEntry->Bits.Reserved_0 = 0;\r
	76	IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
73f0127f SZ	77	IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
73f0127f SZ	78	IdtEntry->Bits.OffsetUpper = (UINT32)(PageFaultHandlerHookAddress >> 32);\r
68cc1ba3	79	IdtEntry->Bits.Reserved_1 = 0;\r
d0bf5623 JY	80	\r
d0bf5623 JY	81	if (mPage1GSupport) {\r
c6368abc	82	mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(2);\r
d0bf5623	83	}else {\r
c6368abc SZ	84	mPageFaultBuffer = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(6);\r
	85	}\r
	86	ZeroMem (mPageFaultUplink, sizeof (mPageFaultUplink));\r
	87	}\r
	88	\r
	89	/**\r
	90	The function will check if current waking vector is long mode.\r
	91	\r
	92	@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT\r
	93	\r
	94	@retval TRUE Current context need long mode waking vector.\r
	95	@retval FALSE Current context need not long mode waking vector.\r
	96	**/\r
	97	BOOLEAN\r
	98	IsLongModeWakingVector (\r
	99	IN ACPI_S3_CONTEXT *AcpiS3Context\r
	100	)\r
	101	{\r
	102	EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *Facs;\r
	103	\r
	104	Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable));\r
	105	if ((Facs == NULL) \|\|\r
	106	(Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) \|\|\r
	107	((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {\r
	108	// Something wrong with FACS\r
	109	return FALSE;\r
	110	}\r
	111	if (Facs->XFirmwareWakingVector != 0) {\r
	112	if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&\r
	113	((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&\r
306a5836	114	((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {\r
c6368abc SZ	115	// Both BIOS and OS wants 64bit vector\r
	116	if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
	117	return TRUE;\r
	118	}\r
	119	}\r
d0bf5623	120	}\r
c6368abc	121	return FALSE;\r
d0bf5623 JY	122	}\r
d0bf5623 JY	123	\r
be46cd5f	124	/**\r
	125	Set a IDT entry for interrupt vector 3 for debug purpose.\r
	126	\r
	127	@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT\r
	128	\r
	129	**/\r
	130	VOID\r
	131	SetIdtEntry (\r
	132	IN ACPI_S3_CONTEXT *AcpiS3Context\r
	133	)\r
	134	{\r
68cc1ba3	135	IA32_IDT_GATE_DESCRIPTOR *IdtEntry;\r
be46cd5f	136	IA32_DESCRIPTOR *IdtDescriptor;\r
be46cd5f	137	UINTN S3DebugBuffer;\r
57f360f2	138	EFI_STATUS Status;\r
be46cd5f	139	\r
	140	//\r
	141	// Restore IDT for debug\r
	142	//\r
	143	IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);\r
1e172d6b	144	AsmWriteIdtr (IdtDescriptor);\r
	145	\r
	146	//\r
	147	// Setup the default CPU exception handlers\r
	148	//\r
57f360f2 JF	149	Status = InitializeCpuExceptionHandlers (NULL);\r
57f360f2 JF	150	ASSERT_EFI_ERROR (Status);\r
1e172d6b	151	\r
f4a25e81	152	DEBUG_CODE (\r
	153	//\r
	154	// Update IDT entry INT3 if the instruction is valid in it\r
	155	//\r
	156	S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);\r
	157	if ((UINTN )S3DebugBuffer != (UINTN) -1) {\r
68cc1ba3 SZ	158	IdtEntry = (IA32_IDT_GATE_DESCRIPTOR )(IdtDescriptor->Base + (3 sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
	159	IdtEntry->Bits.OffsetLow = (UINT16)S3DebugBuffer;\r
	160	IdtEntry->Bits.Selector = (UINT16)AsmReadCs ();\r
	161	IdtEntry->Bits.Reserved_0 = 0;\r
	162	IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
	163	IdtEntry->Bits.OffsetHigh = (UINT16)(S3DebugBuffer >> 16);\r
	164	IdtEntry->Bits.OffsetUpper = (UINT32)(S3DebugBuffer >> 32);\r
	165	IdtEntry->Bits.Reserved_1 = 0;\r
f4a25e81	166	}\r
f4a25e81	167	);\r
be46cd5f	168	\r
c6368abc SZ	169	//\r
	170	// If both BIOS and OS wants long mode waking vector,\r
	171	// S3ResumePei should have established 1:1 Virtual to Physical identity mapping page table,\r
	172	// no need to hook page fault handler.\r
	173	//\r
	174	if (!IsLongModeWakingVector (AcpiS3Context)) {\r
	175	IdtEntry = (IA32_IDT_GATE_DESCRIPTOR )(IdtDescriptor->Base + (14 sizeof (IA32_IDT_GATE_DESCRIPTOR)));\r
	176	HookPageFaultHandler (IdtEntry);\r
	177	}\r
d0bf5623 JY	178	}\r
d0bf5623 JY	179	\r
54e27ada	180	/**\r
c6368abc	181	Acquire page for page fault.\r
54e27ada	182	\r
c6368abc	183	@param[in, out] Uplink Pointer to up page table entry.\r
54e27ada	184	\r
54e27ada	185	**/\r
c6368abc SZ	186	VOID\r
	187	AcquirePage (\r
	188	IN OUT UINT64 *Uplink\r
d0bf5623 JY	189	)\r
d0bf5623 JY	190	{\r
c6368abc SZ	191	UINTN Address;\r
	192	\r
	193	Address = mPageFaultBuffer + EFI_PAGES_TO_SIZE (mPageFaultIndex);\r
	194	ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1));\r
	195	\r
	196	//\r
	197	// Cut the previous uplink if it exists and wasn't overwritten.\r
	198	//\r
ab1a5a58 LD	199	if ((mPageFaultUplink[mPageFaultIndex] != NULL) &&\r
ab1a5a58 LD	200	((*mPageFaultUplink[mPageFaultIndex] & ~mAddressEncMask & mPhyMask) == Address)) {\r
c6368abc SZ	201	*mPageFaultUplink[mPageFaultIndex] = 0;\r
	202	}\r
	203	\r
	204	//\r
	205	// Link & Record the current uplink.\r
	206	//\r
ab1a5a58	207	*Uplink = Address \| mAddressEncMask \| IA32_PG_P \| IA32_PG_RW;\r
c6368abc SZ	208	mPageFaultUplink[mPageFaultIndex] = Uplink;\r
	209	\r
	210	mPageFaultIndex = (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;\r
be46cd5f	211	}\r
be46cd5f	212	\r
54e27ada JY	213	/**\r
54e27ada JY	214	The page fault handler that on-demand read >4G memory/MMIO.\r
d1102dba	215	\r
54e27ada JY	216	@retval TRUE The page fault is correctly handled.\r
	217	@retval FALSE The page fault is not handled and is passed through to original handler.\r
	218	\r
	219	**/\r
d0bf5623 JY	220	BOOLEAN\r
	221	EFIAPI\r
	222	PageFaultHandler (\r
	223	VOID\r
	224	)\r
	225	{\r
	226	UINT64 *PageTable;\r
	227	UINT64 PFAddress;\r
	228	UINTN PTIndex;\r
	229	\r
	230	PFAddress = AsmReadCr2 ();\r
558f58e3	231	DEBUG ((DEBUG_INFO, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));\r
d0bf5623 JY	232	\r
	233	if (PFAddress >= mPhyMask + SIZE_4KB) {\r
	234	return FALSE;\r
	235	}\r
	236	PFAddress &= mPhyMask;\r
	237	\r
	238	PageTable = (UINT64*)(UINTN)(AsmReadCr3 () & mPhyMask);\r
	239	\r
	240	PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
	241	// PML4E\r
	242	if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
c6368abc	243	AcquirePage (&PageTable[PTIndex]);\r
d0bf5623	244	}\r
ab1a5a58	245	PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
d0bf5623 JY	246	PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
	247	// PDPTE\r
	248	if (mPage1GSupport) {\r
ab1a5a58	249	PageTable[PTIndex] = ((PFAddress \| mAddressEncMask) & ~((1ull << 30) - 1)) \| IA32_PG_P \| IA32_PG_RW \| IA32_PG_PS;\r
d0bf5623 JY	250	} else {\r
d0bf5623 JY	251	if ((PageTable[PTIndex] & IA32_PG_P) == 0) {\r
c6368abc	252	AcquirePage (&PageTable[PTIndex]);\r
d0bf5623	253	}\r
ab1a5a58	254	PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);\r
d0bf5623 JY	255	PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
d0bf5623 JY	256	// PD\r
ab1a5a58	257	PageTable[PTIndex] = ((PFAddress \| mAddressEncMask) & ~((1ull << 21) - 1)) \| IA32_PG_P \| IA32_PG_RW \| IA32_PG_PS;\r
d0bf5623 JY	258	}\r
	259	\r
	260	return TRUE;\r
	261	}\r