projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| da58b0db | 1 | /** @file\r |
| 2 | \r | |
| d1102dba | 3 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| da58b0db | 4 | \r |
| 9d510e61 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| da58b0db | 6 | \r |
| 7 | **/\r | |
| 8 | \r | |
| 9 | #ifndef _CAPSULE_PEIM_H_\r | |
| 10 | #define _CAPSULE_PEIM_H_\r | |
| 11 | \r | |
| 12 | #include <PiPei.h>\r | |
| 13 | #include <Uefi/UefiSpec.h>\r | |
| 14 | \r | |
| 15 | #include <Ppi/Capsule.h>\r | |
| ab7017fe | 16 | #include <Ppi/LoadFile.h>\r |
| da58b0db | 17 | #include <Ppi/ReadOnlyVariable2.h>\r |
| 18 | #include <Guid/CapsuleVendor.h>\r | |
| 19 | \r | |
| 359cb1a3 | 20 | #include <Library/BaseLib.h>\r |
| da58b0db | 21 | #include <Library/DebugLib.h>\r |
| 22 | #include <Library/PeimEntryPoint.h>\r | |
| 23 | #include <Library/PeiServicesLib.h>\r | |
| 24 | #include <Library/BaseMemoryLib.h>\r | |
| 25 | #include <Library/HobLib.h>\r | |
| 26 | #include <Library/PeiServicesTablePointerLib.h>\r | |
| 27 | #include <Library/PrintLib.h>\r | |
| ab7017fe | 28 | #include <Library/PeCoffLib.h>\r |
| 29 | #include <Library/PeCoffGetEntryPointLib.h>\r | |
| 30 | #include <Library/PcdLib.h>\r | |
| 31 | #include <Library/ReportStatusCodeLib.h>\r | |
| 933d80a1 | 32 | #include <Library/DebugAgentLib.h>\r |
| ab7017fe | 33 | #include <IndustryStandard/PeImage.h>\r |
| 34 | #include "Common/CommonHeader.h"\r | |
| 35 | \r | |
| d1102dba | 36 | #ifdef MDE_CPU_IA32\r |
| 4e4f13d2 | 37 | \r |
| ab7017fe | 38 | #pragma pack(1)\r |
| da58b0db | 39 | \r |
| 40 | //\r | |
| ab7017fe | 41 | // Page-Map Level-4 Offset (PML4) and\r |
| 42 | // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r | |
| da58b0db | 43 | //\r |
| ab7017fe | 44 | \r |
| 45 | typedef union {\r | |
| 46 | struct {\r | |
| 47 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
| 48 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
| 49 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
| 50 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
| 51 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
| 52 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
| 53 | UINT64 Reserved:1; // Reserved\r | |
| 54 | UINT64 MustBeZero:2; // Must Be Zero\r | |
| 55 | UINT64 Available:3; // Available for use by system software\r | |
| 56 | UINT64 PageTableBaseAddress:40; // Page Table Base Address\r | |
| 57 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
| 58 | UINT64 Nx:1; // No Execute bit\r | |
| 59 | } Bits;\r | |
| 60 | UINT64 Uint64;\r | |
| 61 | } PAGE_MAP_AND_DIRECTORY_POINTER;\r | |
| da58b0db | 62 | \r |
| 63 | //\r | |
| ab7017fe | 64 | // Page Table Entry 2MB\r |
| da58b0db | 65 | //\r |
| ab7017fe | 66 | typedef union {\r |
| 67 | struct {\r | |
| 68 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
| 69 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
| 70 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
| 71 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
| 72 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
| 73 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
| 74 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
| d1102dba | 75 | UINT64 MustBe1:1; // Must be 1\r |
| ab7017fe | 76 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r |
| 77 | UINT64 Available:3; // Available for use by system software\r | |
| 78 | UINT64 PAT:1; //\r | |
| 79 | UINT64 MustBeZero:8; // Must be zero;\r | |
| 80 | UINT64 PageTableBaseAddress:31; // Page Table Base Address\r | |
| 81 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
| 82 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
| 83 | } Bits;\r | |
| 84 | UINT64 Uint64;\r | |
| 85 | } PAGE_TABLE_ENTRY;\r | |
| da58b0db | 86 | \r |
| c56b6566 JY |
87 | //\r |
| 88 | // Page Table Entry 1GB\r | |
| 89 | //\r | |
| 90 | typedef union {\r | |
| 91 | struct {\r | |
| 92 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
| 93 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
| 94 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
| 95 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
| 96 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
| 97 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
| 98 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
| d1102dba | 99 | UINT64 MustBe1:1; // Must be 1\r |
| c56b6566 JY |
100 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r |
| 101 | UINT64 Available:3; // Available for use by system software\r | |
| 102 | UINT64 PAT:1; //\r | |
| 103 | UINT64 MustBeZero:17; // Must be zero;\r | |
| 104 | UINT64 PageTableBaseAddress:22; // Page Table Base Address\r | |
| 105 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
| 106 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
| 107 | } Bits;\r | |
| 108 | UINT64 Uint64;\r | |
| 109 | } PAGE_TABLE_1G_ENTRY;\r | |
| 110 | \r | |
| ab7017fe | 111 | #pragma pack()\r |
| da58b0db | 112 | \r |
| ab7017fe | 113 | typedef\r |
| 114 | EFI_STATUS\r | |
| 115 | (*COALESCE_ENTRY) (\r | |
| ed3ff1ac SZ |
116 | SWITCH_32_TO_64_CONTEXT *EntrypointContext,\r |
| 117 | SWITCH_64_TO_32_CONTEXT *ReturnContext\r | |
| ab7017fe | 118 | );\r |
| da58b0db | 119 | \r |
| 120 | #endif\r | |
| 4e4f13d2 | 121 | \r |
| 122 | #endif\r |