[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Acpi50.h

/** @file\r
  ACPI 5.0 definitions from the ACPI Specification Revision 5.0a November 13, 2013.\r
\r
  Copyright (c) 2014 Hewlett-Packard Development Company, L.P.<BR>\r
  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#ifndef _ACPI_5_0_H_\r
#define _ACPI_5_0_H_\r
\r
#include <IndustryStandard/Acpi40.h>\r
\r
//\r
// Define for Descriptor\r
//\r
#define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME                      0x0A\r
#define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME                0x0C\r
#define ACPI_LARGE_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR_NAME  0x0E\r
\r
#define ACPI_FIXED_DMA_DESCRIPTOR                      0x55\r
#define ACPI_GPIO_CONNECTION_DESCRIPTOR                0x8C\r
#define ACPI_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR  0x8E\r
\r
#pragma pack(1)\r
\r
///\r
/// Generic DMA Descriptor.\r
///\r
typedef PACKED struct {\r
  ACPI_SMALL_RESOURCE_HEADER    Header;\r
  UINT16                        DmaRequestLine;\r
  UINT16                        DmaChannel;\r
  UINT8                         DmaTransferWidth;\r
} EFI_ACPI_FIXED_DMA_DESCRIPTOR;\r
\r
///\r
/// GPIO Connection Descriptor\r
///\r
typedef PACKED struct {\r
  ACPI_LARGE_RESOURCE_HEADER    Header;\r
  UINT8                         RevisionId;\r
  UINT8                         ConnectionType;\r
  UINT16                        GeneralFlags;\r
  UINT16                        InterruptFlags;\r
  UINT8                         PinConfiguration;\r
  UINT16                        OutputDriveStrength;\r
  UINT16                        DebounceTimeout;\r
  UINT16                        PinTableOffset;\r
  UINT8                         ResourceSourceIndex;\r
  UINT16                        ResourceSourceNameOffset;\r
  UINT16                        VendorDataOffset;\r
  UINT16                        VendorDataLength;\r
} EFI_ACPI_GPIO_CONNECTION_DESCRIPTOR;\r
\r
#define EFI_ACPI_GPIO_CONNECTION_TYPE_INTERRUPT  0x0\r
#define EFI_ACPI_GPIO_CONNECTION_TYPE_IO         0x1\r
\r
///\r
/// Serial Bus Resource Descriptor (Generic)\r
///\r
typedef PACKED struct {\r
  ACPI_LARGE_RESOURCE_HEADER    Header;\r
  UINT8                         RevisionId;\r
  UINT8                         ResourceSourceIndex;\r
  UINT8                         SerialBusType;\r
  UINT8                         GeneralFlags;\r
  UINT16                        TypeSpecificFlags;\r
  UINT8                         TypeSpecificRevisionId;\r
  UINT16                        TypeDataLength;\r
  // Type specific data\r
} EFI_ACPI_SERIAL_BUS_RESOURCE_DESCRIPTOR;\r
\r
#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_I2C   0x1\r
#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_SPI   0x2\r
#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_UART  0x3\r
\r
///\r
/// Serial Bus Resource Descriptor (I2C)\r
///\r
typedef PACKED struct {\r
  ACPI_LARGE_RESOURCE_HEADER    Header;\r
  UINT8                         RevisionId;\r
  UINT8                         ResourceSourceIndex;\r
  UINT8                         SerialBusType;\r
  UINT8                         GeneralFlags;\r
  UINT16                        TypeSpecificFlags;\r
  UINT8                         TypeSpecificRevisionId;\r
  UINT16                        TypeDataLength;\r
  UINT32                        ConnectionSpeed;\r
  UINT16                        SlaveAddress;\r
} EFI_ACPI_SERIAL_BUS_RESOURCE_I2C_DESCRIPTOR;\r
\r
///\r
/// Serial Bus Resource Descriptor (SPI)\r
///\r
typedef PACKED struct {\r
  ACPI_LARGE_RESOURCE_HEADER    Header;\r
  UINT8                         RevisionId;\r
  UINT8                         ResourceSourceIndex;\r
  UINT8                         SerialBusType;\r
  UINT8                         GeneralFlags;\r
  UINT16                        TypeSpecificFlags;\r
  UINT8                         TypeSpecificRevisionId;\r
  UINT16                        TypeDataLength;\r
  UINT32                        ConnectionSpeed;\r
  UINT8                         DataBitLength;\r
  UINT8                         Phase;\r
  UINT8                         Polarity;\r
  UINT16                        DeviceSelection;\r
} EFI_ACPI_SERIAL_BUS_RESOURCE_SPI_DESCRIPTOR;\r
\r
///\r
/// Serial Bus Resource Descriptor (UART)\r
///\r
typedef PACKED struct {\r
  ACPI_LARGE_RESOURCE_HEADER    Header;\r
  UINT8                         RevisionId;\r
  UINT8                         ResourceSourceIndex;\r
  UINT8                         SerialBusType;\r
  UINT8                         GeneralFlags;\r
  UINT16                        TypeSpecificFlags;\r
  UINT8                         TypeSpecificRevisionId;\r
  UINT16                        TypeDataLength;\r
  UINT32                        DefaultBaudRate;\r
  UINT16                        RxFIFO;\r
  UINT16                        TxFIFO;\r
  UINT8                         Parity;\r
  UINT8                         SerialLinesEnabled;\r
} EFI_ACPI_SERIAL_BUS_RESOURCE_UART_DESCRIPTOR;\r
\r
#pragma pack()\r
\r
//\r
// Ensure proper structure formats\r
//\r
#pragma pack(1)\r
\r
///\r
/// ACPI 5.0 Generic Address Space definition\r
///\r
typedef struct {\r
  UINT8     AddressSpaceId;\r
  UINT8     RegisterBitWidth;\r
  UINT8     RegisterBitOffset;\r
  UINT8     AccessSize;\r
  UINT64    Address;\r
} EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
// Generic Address Space Address IDs\r
//\r
#define EFI_ACPI_5_0_SYSTEM_MEMORY                   0\r
#define EFI_ACPI_5_0_SYSTEM_IO                       1\r
#define EFI_ACPI_5_0_PCI_CONFIGURATION_SPACE         2\r
#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER             3\r
#define EFI_ACPI_5_0_SMBUS                           4\r
#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL  0x0A\r
#define EFI_ACPI_5_0_FUNCTIONAL_FIXED_HARDWARE       0x7F\r
\r
//\r
// Generic Address Space Access Sizes\r
//\r
#define EFI_ACPI_5_0_UNDEFINED  0\r
#define EFI_ACPI_5_0_BYTE       1\r
#define EFI_ACPI_5_0_WORD       2\r
#define EFI_ACPI_5_0_DWORD      3\r
#define EFI_ACPI_5_0_QWORD      4\r
\r
//\r
// ACPI 5.0 table structures\r
//\r
\r
///\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
  UINT64    Signature;\r
  UINT8     Checksum;\r
  UINT8     OemId[6];\r
  UINT8     Revision;\r
  UINT32    RsdtAddress;\r
  UINT32    Length;\r
  UINT64    XsdtAddress;\r
  UINT8     ExtendedChecksum;\r
  UINT8     Reserved[3];\r
} EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION  0x02 ///< ACPISpec (Revision 5.0) says current value is 2\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
  UINT32    Signature;\r
  UINT32    Length;\r
} EFI_ACPI_5_0_COMMON_HEADER;\r
\r
//\r
// Root System Description Table\r
// No definition needed as it is a common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\r
//\r
\r
///\r
/// RSDT Revision (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION  0x01\r
\r
//\r
// Extended System Description Table\r
// No definition needed as it is a common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\r
//\r
\r
///\r
/// XSDT Revision (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION  0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER               Header;\r
  UINT32                                    FirmwareCtrl;\r
  UINT32                                    Dsdt;\r
  UINT8                                     Reserved0;\r
  UINT8                                     PreferredPmProfile;\r
  UINT16                                    SciInt;\r
  UINT32                                    SmiCmd;\r
  UINT8                                     AcpiEnable;\r
  UINT8                                     AcpiDisable;\r
  UINT8                                     S4BiosReq;\r
  UINT8                                     PstateCnt;\r
  UINT32                                    Pm1aEvtBlk;\r
  UINT32                                    Pm1bEvtBlk;\r
  UINT32                                    Pm1aCntBlk;\r
  UINT32                                    Pm1bCntBlk;\r
  UINT32                                    Pm2CntBlk;\r
  UINT32                                    PmTmrBlk;\r
  UINT32                                    Gpe0Blk;\r
  UINT32                                    Gpe1Blk;\r
  UINT8                                     Pm1EvtLen;\r
  UINT8                                     Pm1CntLen;\r
  UINT8                                     Pm2CntLen;\r
  UINT8                                     PmTmrLen;\r
  UINT8                                     Gpe0BlkLen;\r
  UINT8                                     Gpe1BlkLen;\r
  UINT8                                     Gpe1Base;\r
  UINT8                                     CstCnt;\r
  UINT16                                    PLvl2Lat;\r
  UINT16                                    PLvl3Lat;\r
  UINT16                                    FlushSize;\r
  UINT16                                    FlushStride;\r
  UINT8                                     DutyOffset;\r
  UINT8                                     DutyWidth;\r
  UINT8                                     DayAlrm;\r
  UINT8                                     MonAlrm;\r
  UINT8                                     Century;\r
  UINT16                                    IaPcBootArch;\r
  UINT8                                     Reserved1;\r
  UINT32                                    Flags;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    ResetReg;\r
  UINT8                                     ResetValue;\r
  UINT8                                     Reserved2[3];\r
  UINT64                                    XFirmwareCtrl;\r
  UINT64                                    XDsdt;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    XPm1aEvtBlk;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    XPm1bEvtBlk;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    XPm1aCntBlk;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    XPm1bCntBlk;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    XPm2CntBlk;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    XPmTmrBlk;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    XGpe0Blk;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    XGpe1Blk;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    SleepControlReg;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    SleepStatusReg;\r
} EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
/// FADT Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x05\r
\r
//\r
// Fixed ACPI Description Table Preferred Power Management Profile\r
//\r
#define EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED         0\r
#define EFI_ACPI_5_0_PM_PROFILE_DESKTOP             1\r
#define EFI_ACPI_5_0_PM_PROFILE_MOBILE              2\r
#define EFI_ACPI_5_0_PM_PROFILE_WORKSTATION         3\r
#define EFI_ACPI_5_0_PM_PROFILE_ENTERPRISE_SERVER   4\r
#define EFI_ACPI_5_0_PM_PROFILE_SOHO_SERVER         5\r
#define EFI_ACPI_5_0_PM_PROFILE_APPLIANCE_PC        6\r
#define EFI_ACPI_5_0_PM_PROFILE_PERFORMANCE_SERVER  7\r
#define EFI_ACPI_5_0_PM_PROFILE_TABLET              8\r
\r
//\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
#define EFI_ACPI_5_0_LEGACY_DEVICES        BIT0\r
#define EFI_ACPI_5_0_8042                  BIT1\r
#define EFI_ACPI_5_0_VGA_NOT_PRESENT       BIT2\r
#define EFI_ACPI_5_0_MSI_NOT_SUPPORTED     BIT3\r
#define EFI_ACPI_5_0_PCIE_ASPM_CONTROLS    BIT4\r
#define EFI_ACPI_5_0_CMOS_RTC_NOT_PRESENT  BIT5\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
#define EFI_ACPI_5_0_WBINVD                                BIT0\r
#define EFI_ACPI_5_0_WBINVD_FLUSH                          BIT1\r
#define EFI_ACPI_5_0_PROC_C1                               BIT2\r
#define EFI_ACPI_5_0_P_LVL2_UP                             BIT3\r
#define EFI_ACPI_5_0_PWR_BUTTON                            BIT4\r
#define EFI_ACPI_5_0_SLP_BUTTON                            BIT5\r
#define EFI_ACPI_5_0_FIX_RTC                               BIT6\r
#define EFI_ACPI_5_0_RTC_S4                                BIT7\r
#define EFI_ACPI_5_0_TMR_VAL_EXT                           BIT8\r
#define EFI_ACPI_5_0_DCK_CAP                               BIT9\r
#define EFI_ACPI_5_0_RESET_REG_SUP                         BIT10\r
#define EFI_ACPI_5_0_SEALED_CASE                           BIT11\r
#define EFI_ACPI_5_0_HEADLESS                              BIT12\r
#define EFI_ACPI_5_0_CPU_SW_SLP                            BIT13\r
#define EFI_ACPI_5_0_PCI_EXP_WAK                           BIT14\r
#define EFI_ACPI_5_0_USE_PLATFORM_CLOCK                    BIT15\r
#define EFI_ACPI_5_0_S4_RTC_STS_VALID                      BIT16\r
#define EFI_ACPI_5_0_REMOTE_POWER_ON_CAPABLE               BIT17\r
#define EFI_ACPI_5_0_FORCE_APIC_CLUSTER_MODEL              BIT18\r
#define EFI_ACPI_5_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE  BIT19\r
#define EFI_ACPI_5_0_HW_REDUCED_ACPI                       BIT20\r
#define EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE             BIT21\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
  UINT32    Signature;\r
  UINT32    Length;\r
  UINT32    HardwareSignature;\r
  UINT32    FirmwareWakingVector;\r
  UINT32    GlobalLock;\r
  UINT32    Flags;\r
  UINT64    XFirmwareWakingVector;\r
  UINT8     Version;\r
  UINT8     Reserved0[3];\r
  UINT32    OspmFlags;\r
  UINT8     Reserved1[24];\r
} EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// FACS Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x02\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
#define EFI_ACPI_5_0_S4BIOS_F                BIT0\r
#define EFI_ACPI_5_0_64BIT_WAKE_SUPPORTED_F  BIT1\r
\r
///\r
/// OSPM Enabled Firmware Control Structure Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
#define EFI_ACPI_5_0_OSPM_64BIT_WAKE_F  BIT0\r
\r
//\r
// Differentiated System Description Table,\r
// Secondary System Description Table\r
// and Persistent System Description Table,\r
// no definition needed as they are common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\r
//\r
#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION  0x02\r
#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION       0x02\r
\r
///\r
/// Multiple APIC Description Table header definition.  The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT32                         LocalApicAddress;\r
  UINT32                         Flags;\r
} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION  0x03\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
#define EFI_ACPI_5_0_PCAT_COMPAT  BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
// All other values between 0x0D and 0x7F are reserved and\r
// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.\r
//\r
#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC           0x00\r
#define EFI_ACPI_5_0_IO_APIC                        0x01\r
#define EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE      0x02\r
#define EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE  0x03\r
#define EFI_ACPI_5_0_LOCAL_APIC_NMI                 0x04\r
#define EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE    0x05\r
#define EFI_ACPI_5_0_IO_SAPIC                       0x06\r
#define EFI_ACPI_5_0_LOCAL_SAPIC                    0x07\r
#define EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES     0x08\r
#define EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC         0x09\r
#define EFI_ACPI_5_0_LOCAL_X2APIC_NMI               0x0A\r
#define EFI_ACPI_5_0_GIC                            0x0B\r
#define EFI_ACPI_5_0_GICD                           0x0C\r
\r
//\r
// APIC Structure Definitions\r
//\r
\r
///\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT8     AcpiProcessorId;\r
  UINT8     ApicId;\r
  UINT32    Flags;\r
} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// Local APIC Flags.  All other bits are reserved and must be 0.\r
///\r
#define EFI_ACPI_5_0_LOCAL_APIC_ENABLED  BIT0\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT8     IoApicId;\r
  UINT8     Reserved;\r
  UINT32    IoApicAddress;\r
  UINT32    GlobalSystemInterruptBase;\r
} EFI_ACPI_5_0_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT8     Bus;\r
  UINT8     Source;\r
  UINT32    GlobalSystemInterrupt;\r
  UINT16    Flags;\r
} EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure Definition\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT16    Flags;\r
  UINT8     InterruptType;\r
  UINT8     ProcessorId;\r
  UINT8     ProcessorEid;\r
  UINT8     IoSapicVector;\r
  UINT32    GlobalSystemInterrupt;\r
  UINT32    PlatformInterruptSourceFlags;\r
  UINT8     CpeiProcessorOverride;\r
  UINT8     Reserved[31];\r
} EFI_ACPI_5_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;\r
\r
//\r
// MPS INTI flags.\r
// All other bits are reserved and must be set to 0.\r
//\r
#define EFI_ACPI_5_0_POLARITY      (3 << 0)\r
#define EFI_ACPI_5_0_TRIGGER_MODE  (3 << 2)\r
\r
///\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT16    Flags;\r
  UINT32    GlobalSystemInterrupt;\r
} EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT8     AcpiProcessorId;\r
  UINT16    Flags;\r
  UINT8     LocalApicLint;\r
} EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT16    Reserved;\r
  UINT64    LocalApicAddress;\r
} EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT8     IoApicId;\r
  UINT8     Reserved;\r
  UINT32    GlobalSystemInterruptBase;\r
  UINT64    IoSapicAddress;\r
} EFI_ACPI_5_0_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// Local SAPIC Structure\r
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT8     AcpiProcessorId;\r
  UINT8     LocalSapicId;\r
  UINT8     LocalSapicEid;\r
  UINT8     Reserved[3];\r
  UINT32    Flags;\r
  UINT32    ACPIProcessorUIDValue;\r
} EFI_ACPI_5_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT16    Flags;\r
  UINT8     InterruptType;\r
  UINT8     ProcessorId;\r
  UINT8     ProcessorEid;\r
  UINT8     IoSapicVector;\r
  UINT32    GlobalSystemInterrupt;\r
  UINT32    PlatformInterruptSourceFlags;\r
} EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
#define EFI_ACPI_5_0_CPEI_PROCESSOR_OVERRIDE  BIT0\r
\r
///\r
/// Processor Local x2APIC Structure Definition\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT8     Reserved[2];\r
  UINT32    X2ApicId;\r
  UINT32    Flags;\r
  UINT32    AcpiProcessorUid;\r
} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\r
\r
///\r
/// Local x2APIC NMI Structure\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT16    Flags;\r
  UINT32    AcpiProcessorUid;\r
  UINT8     LocalX2ApicLint;\r
  UINT8     Reserved[3];\r
} EFI_ACPI_5_0_LOCAL_X2APIC_NMI_STRUCTURE;\r
\r
///\r
/// GIC Structure\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT16    Reserved;\r
  UINT32    GicId;\r
  UINT32    AcpiProcessorUid;\r
  UINT32    Flags;\r
  UINT32    ParkingProtocolVersion;\r
  UINT32    PerformanceInterruptGsiv;\r
  UINT64    ParkedAddress;\r
  UINT64    PhysicalBaseAddress;\r
} EFI_ACPI_5_0_GIC_STRUCTURE;\r
\r
///\r
/// GIC Flags.  All other bits are reserved and must be 0.\r
///\r
#define EFI_ACPI_5_0_GIC_ENABLED                  BIT0\r
#define EFI_ACPI_5_0_PERFORMANCE_INTERRUPT_MODEL  BIT1\r
\r
///\r
/// GIC Distributor Structure\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT16    Reserved1;\r
  UINT32    GicId;\r
  UINT64    PhysicalBaseAddress;\r
  UINT32    SystemVectorBase;\r
  UINT32    Reserved2;\r
} EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE;\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT32                         WarningEnergyLevel;\r
  UINT32                         LowEnergyLevel;\r
  UINT32                         CriticalEnergyLevel;\r
} EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION  0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// The table is followed by a null terminated ASCII string that contains\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER               Header;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    EcControl;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    EcData;\r
  UINT32                                    Uid;\r
  UINT8                                     GpeBit;\r
} EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
/// ECDT Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01\r
\r
///\r
/// System Resource Affinity Table (SRAT).  The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT32                         Reserved1; ///< Must be set to 1\r
  UINT64                         Reserved2;\r
} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
/// SRAT Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x03\r
\r
//\r
// SRAT structure types.\r
// All other values between 0x03 an 0xFF are reserved and\r
// will be ignored by OSPM.\r
//\r
#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00\r
#define EFI_ACPI_5_0_MEMORY_AFFINITY                      0x01\r
#define EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY      0x02\r
\r
///\r
/// Processor Local APIC/SAPIC Affinity Structure Definition\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT8     ProximityDomain7To0;\r
  UINT8     ApicId;\r
  UINT32    Flags;\r
  UINT8     LocalSapicEid;\r
  UINT8     ProximityDomain31To8[3];\r
  UINT32    ClockDomain;\r
} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// Local APIC/SAPIC Flags.  All other bits are reserved and must be 0.\r
///\r
#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED  (1 << 0)\r
\r
///\r
/// Memory Affinity Structure Definition\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT32    ProximityDomain;\r
  UINT16    Reserved1;\r
  UINT32    AddressBaseLow;\r
  UINT32    AddressBaseHigh;\r
  UINT32    LengthLow;\r
  UINT32    LengthHigh;\r
  UINT32    Reserved2;\r
  UINT32    Flags;\r
  UINT64    Reserved3;\r
} EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE;\r
\r
//\r
// Memory Flags.  All other bits are reserved and must be 0.\r
//\r
#define EFI_ACPI_5_0_MEMORY_ENABLED        (1 << 0)\r
#define EFI_ACPI_5_0_MEMORY_HOT_PLUGGABLE  (1 << 1)\r
#define EFI_ACPI_5_0_MEMORY_NONVOLATILE    (1 << 2)\r
\r
///\r
/// Processor Local x2APIC Affinity Structure Definition\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT8     Reserved1[2];\r
  UINT32    ProximityDomain;\r
  UINT32    X2ApicId;\r
  UINT32    Flags;\r
  UINT32    ClockDomain;\r
  UINT8     Reserved2[4];\r
} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// System Locality Distance Information Table (SLIT).\r
/// The rest of the table is a matrix.\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT64                         NumberOfSystemLocalities;\r
} EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\r
\r
///\r
/// SLIT Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION  0x01\r
\r
///\r
/// Corrected Platform Error Polling Table (CPEP)\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT8                          Reserved[8];\r
} EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\r
\r
///\r
/// CPEP Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION  0x01\r
\r
//\r
// CPEP processor structure types.\r
//\r
#define EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC  0x00\r
\r
///\r
/// Corrected Platform Error Polling Processor Structure Definition\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT8     ProcessorId;\r
  UINT8     ProcessorEid;\r
  UINT32    PollingInterval;\r
} EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\r
\r
///\r
/// Maximum System Characteristics Table (MSCT)\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT32                         OffsetProxDomInfo;\r
  UINT32                         MaximumNumberOfProximityDomains;\r
  UINT32                         MaximumNumberOfClockDomains;\r
  UINT64                         MaximumPhysicalAddress;\r
} EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\r
\r
///\r
/// MSCT Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION  0x01\r
\r
///\r
/// Maximum Proximity Domain Information Structure Definition\r
///\r
typedef struct {\r
  UINT8     Revision;\r
  UINT8     Length;\r
  UINT32    ProximityDomainRangeLow;\r
  UINT32    ProximityDomainRangeHigh;\r
  UINT32    MaximumProcessorCapacity;\r
  UINT64    MaximumMemoryCapacity;\r
} EFI_ACPI_5_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\r
\r
///\r
/// ACPI RAS Feature Table definition.\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT8                          PlatformCommunicationChannelIdentifier[12];\r
} EFI_ACPI_5_0_RAS_FEATURE_TABLE;\r
\r
///\r
/// RASF Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_RAS_FEATURE_TABLE_REVISION  0x01\r
\r
///\r
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
  UINT32    Signature;\r
  UINT16    Command;\r
  UINT16    Status;\r
  UINT16    Version;\r
  UINT8     RASCapabilities[16];\r
  UINT8     SetRASCapabilities[16];\r
  UINT16    NumberOfRASFParameterBlocks;\r
  UINT32    SetRASCapabilitiesStatus;\r
} EFI_ACPI_5_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
/// ACPI RASF PCC command code\r
///\r
#define EFI_ACPI_5_0_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND  0x01\r
\r
///\r
/// ACPI RASF Platform RAS Capabilities\r
///\r
#define EFI_ACPI_5_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED                          0x01\r
#define EFI_ACPI_5_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE  0x02\r
\r
///\r
/// ACPI RASF Parameter Block structure for PATROL_SCRUB\r
///\r
typedef struct {\r
  UINT16    Type;\r
  UINT16    Version;\r
  UINT16    Length;\r
  UINT16    PatrolScrubCommand;\r
  UINT64    RequestedAddressRange[2];\r
  UINT64    ActualAddressRange[2];\r
  UINT16    Flags;\r
  UINT8     RequestedSpeed;\r
} EFI_ACPI_5_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\r
\r
///\r
/// ACPI RASF Patrol Scrub command\r
///\r
#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS  0x01\r
#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER  0x02\r
#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER   0x03\r
\r
///\r
/// Memory Power State Table definition.\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT8                          PlatformCommunicationChannelIdentifier;\r
  UINT8                          Reserved[3];\r
  // Memory Power Node Structure\r
  // Memory Power State Characteristics\r
} EFI_ACPI_5_0_MEMORY_POWER_STATUS_TABLE;\r
\r
///\r
/// MPST Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_REVISION  0x01\r
\r
///\r
/// MPST Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
  UINT32    Signature;\r
  UINT16    Command;\r
  UINT16    Status;\r
  UINT32    MemoryPowerCommandRegister;\r
  UINT32    MemoryPowerStatusRegister;\r
  UINT32    PowerStateId;\r
  UINT32    MemoryPowerNodeId;\r
  UINT64    MemoryEnergyConsumed;\r
  UINT64    ExpectedAveragePowerComsuned;\r
} EFI_ACPI_5_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
/// ACPI MPST PCC command code\r
///\r
#define EFI_ACPI_5_0_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND  0x03\r
\r
///\r
/// ACPI MPST Memory Power command\r
///\r
#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE      0x01\r
#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE      0x02\r
#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED  0x03\r
#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED  0x04\r
\r
///\r
/// MPST Memory Power Node Table\r
///\r
typedef struct {\r
  UINT8    PowerStateValue;\r
  UINT8    PowerStateInformationIndex;\r
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE;\r
\r
typedef struct {\r
  UINT8     Flag;\r
  UINT8     Reserved;\r
  UINT16    MemoryPowerNodeId;\r
  UINT32    Length;\r
  UINT64    AddressBase;\r
  UINT64    AddressLength;\r
  UINT32    NumberOfPowerStates;\r
  UINT32    NumberOfPhysicalComponents;\r
  // EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE              MemoryPowerState[NumberOfPowerStates];\r
  // UINT16                                            PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE;\r
\r
#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE         0x01\r
#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED  0x02\r
#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE  0x04\r
\r
typedef struct {\r
  UINT16    MemoryPowerNodeCount;\r
  UINT8     Reserved[2];\r
} EFI_ACPI_5_0_MPST_MEMORY_POWER_NODE_TABLE;\r
\r
///\r
/// MPST Memory Power State Characteristics Table\r
///\r
typedef struct {\r
  UINT8     PowerStateStructureID;\r
  UINT8     Flag;\r
  UINT16    Reserved;\r
  UINT32    AveragePowerConsumedInMPS0;\r
  UINT32    RelativePowerSavingToMPS0;\r
  UINT64    ExitLatencyToMPS0;\r
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\r
\r
#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED             0x01\r
#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY  0x02\r
#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT   0x04\r
\r
typedef struct {\r
  UINT16    MemoryPowerStateCharacteristicsCount;\r
  UINT8     Reserved[2];\r
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\r
\r
///\r
/// Memory Topology Table definition.\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT32                         Reserved;\r
} EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE;\r
\r
///\r
/// PMTT Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE_REVISION  0x01\r
\r
///\r
/// Common Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Reserved;\r
  UINT16    Length;\r
  UINT16    Flags;\r
  UINT16    Reserved1;\r
} EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Memory Aggregator Device Type\r
///\r
#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET             0x0\r
#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER  0x1\r
#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM               0x2\r
\r
///\r
/// Socket Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
  EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE    Header;\r
  UINT16                                                         SocketIdentifier;\r
  UINT16                                                         Reserved;\r
  // EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  MemoryController[];\r
} EFI_ACPI_5_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// MemoryController Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
  EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE    Header;\r
  UINT32                                                         ReadLatency;\r
  UINT32                                                         WriteLatency;\r
  UINT32                                                         ReadBandwidth;\r
  UINT32                                                         WriteBandwidth;\r
  UINT16                                                         OptimalAccessUnit;\r
  UINT16                                                         OptimalAccessAlignment;\r
  UINT16                                                         Reserved;\r
  UINT16                                                         NumberOfProximityDomains;\r
  // UINT32                                                       ProximityDomain[NumberOfProximityDomains];\r
  // EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE    PhysicalComponent[];\r
} EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// DIMM Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
  EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE    Header;\r
  UINT16                                                         PhysicalComponentIdentifier;\r
  UINT16                                                         Reserved;\r
  UINT32                                                         SizeOfDimm;\r
  UINT32                                                         SmbiosHandle;\r
} EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Boot Graphics Resource Table definition.\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  ///\r
  /// 2-bytes (16 bit) version ID. This value must be 1.\r
  ///\r
  UINT16                         Version;\r
  ///\r
  /// 1-byte status field indicating current status about the table.\r
  ///     Bits[7:1] = Reserved (must be zero)\r
  ///     Bit [0] = Valid. A one indicates the boot image graphic is valid.\r
  ///\r
  UINT8                          Status;\r
  ///\r
  /// 1-byte enumerated type field indicating format of the image.\r
  ///     0 = Bitmap\r
  ///     1 - 255  Reserved (for future use)\r
  ///\r
  UINT8                          ImageType;\r
  ///\r
  /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\r
  /// of the image bitmap.\r
  ///\r
  UINT64                         ImageAddress;\r
  ///\r
  /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\r
  /// (X, Y) display offset of the top left corner of the boot image.\r
  /// The top left corner of the display is at offset (0, 0).\r
  ///\r
  UINT32                         ImageOffsetX;\r
  ///\r
  /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\r
  /// (X, Y) display offset of the top left corner of the boot image.\r
  /// The top left corner of the display is at offset (0, 0).\r
  ///\r
  UINT32                         ImageOffsetY;\r
} EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE;\r
\r
///\r
/// BGRT Revision\r
///\r
#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION  1\r
\r
///\r
/// BGRT Version\r
///\r
#define EFI_ACPI_5_0_BGRT_VERSION  0x01\r
\r
///\r
/// BGRT Status\r
///\r
#define EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED  0x00\r
#define EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED      0x01\r
#define EFI_ACPI_5_0_BGRT_STATUS_INVALID        EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED\r
#define EFI_ACPI_5_0_BGRT_STATUS_VALID          EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED\r
\r
///\r
/// BGRT Image Type\r
///\r
#define EFI_ACPI_5_0_BGRT_IMAGE_TYPE_BMP  0x00\r
\r
///\r
/// FPDT Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION  0x01\r
\r
///\r
/// FPDT Performance Record Types\r
///\r
#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER   0x0000\r
#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER  0x0001\r
\r
///\r
/// FPDT Performance Record Revision\r
///\r
#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER   0x01\r
#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER  0x01\r
\r
///\r
/// FPDT Runtime Performance Record Types\r
///\r
#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME            0x0000\r
#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND           0x0001\r
#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT  0x0002\r
\r
///\r
/// FPDT Runtime Performance Record Revision\r
///\r
#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME            0x01\r
#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND           0x01\r
#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT  0x02\r
\r
///\r
/// FPDT Performance Record header\r
///\r
typedef struct {\r
  UINT16    Type;\r
  UINT8     Length;\r
  UINT8     Revision;\r
} EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER;\r
\r
///\r
/// FPDT Performance Table header\r
///\r
typedef struct {\r
  UINT32    Signature;\r
  UINT32    Length;\r
} EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Pointer Record Structure\r
///\r
typedef struct {\r
  EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER    Header;\r
  UINT32                                         Reserved;\r
  ///\r
  /// 64-bit processor-relative physical address of the Basic Boot Performance Table.\r
  ///\r
  UINT64                                         BootPerformanceTablePointer;\r
} EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT S3 Performance Table Pointer Record Structure\r
///\r
typedef struct {\r
  EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER    Header;\r
  UINT32                                         Reserved;\r
  ///\r
  /// 64-bit processor-relative physical address of the S3 Performance Table.\r
  ///\r
  UINT64                                         S3PerformanceTablePointer;\r
} EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Record Structure\r
///\r
typedef struct {\r
  EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER    Header;\r
  UINT32                                         Reserved;\r
  ///\r
  /// Timer value logged at the beginning of firmware image execution.\r
  /// This may not always be zero or near zero.\r
  ///\r
  UINT64                                         ResetEnd;\r
  ///\r
  /// Timer value logged just prior to loading the OS boot loader into memory.\r
  /// For non-UEFI compatible boots, this field must be zero.\r
  ///\r
  UINT64                                         OsLoaderLoadImageStart;\r
  ///\r
  /// Timer value logged just prior to launching the previously loaded OS boot loader image.\r
  /// For non-UEFI compatible boots, the timer value logged will be just prior\r
  /// to the INT 19h handler invocation.\r
  ///\r
  UINT64                                         OsLoaderStartImageStart;\r
  ///\r
  /// Timer value logged at the point when the OS loader calls the\r
  /// ExitBootServices function for UEFI compatible firmware.\r
  /// For non-UEFI compatible boots, this field must be zero.\r
  ///\r
  UINT64                                         ExitBootServicesEntry;\r
  ///\r
  /// Timer value logged at the point just prior to when the OS loader gaining\r
  /// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
  /// For non-UEFI compatible boots, this field must be zero.\r
  ///\r
  UINT64                                         ExitBootServicesExit;\r
} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Table signature\r
///\r
#define EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('F', 'B', 'P', 'T')\r
\r
//\r
// FPDT Firmware Basic Boot Performance Table\r
//\r
typedef struct {\r
  EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER    Header;\r
  //\r
  // one or more Performance Records.\r
  //\r
} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_TABLE;\r
\r
///\r
/// FPDT "S3PT" S3 Performance Table\r
///\r
#define EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('S', '3', 'P', 'T')\r
\r
//\r
// FPDT Firmware S3 Boot Performance Table\r
//\r
typedef struct {\r
  EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER    Header;\r
  //\r
  // one or more Performance Records.\r
  //\r
} EFI_ACPI_5_0_FPDT_FIRMWARE_S3_BOOT_TABLE;\r
\r
///\r
/// FPDT Basic S3 Resume Performance Record\r
///\r
typedef struct {\r
  EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER    Header;\r
  ///\r
  /// A count of the number of S3 resume cycles since the last full boot sequence.\r
  ///\r
  UINT32                                         ResumeCount;\r
  ///\r
  /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\r
  /// OS waking vector. Only the most recent resume cycle's time is retained.\r
  ///\r
  UINT64                                         FullResume;\r
  ///\r
  /// Average timer value of all resume cycles logged since the last full boot\r
  /// sequence, including the most recent resume.  Note that the entire log of\r
  /// timer values does not need to be retained in order to calculate this average.\r
  ///\r
  UINT64                                         AverageResume;\r
} EFI_ACPI_5_0_FPDT_S3_RESUME_RECORD;\r
\r
///\r
/// FPDT Basic S3 Suspend Performance Record\r
///\r
typedef struct {\r
  EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER    Header;\r
  ///\r
  /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\r
  /// Only the most recent suspend cycle's timer value is retained.\r
  ///\r
  UINT64                                         SuspendStart;\r
  ///\r
  /// Timer value recorded at the final firmware write to SLP_TYP (or other\r
  /// mechanism) used to trigger hardware entry to S3.\r
  /// Only the most recent suspend cycle's timer value is retained.\r
  ///\r
  UINT64                                         SuspendEnd;\r
} EFI_ACPI_5_0_FPDT_S3_SUSPEND_RECORD;\r
\r
///\r
/// Firmware Performance Record Table definition.\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
} EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_RECORD_TABLE;\r
\r
///\r
/// Generic Timer Description Table definition.\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT64                         PhysicalAddress;\r
  UINT32                         GlobalFlags;\r
  UINT32                         SecurePL1TimerGSIV;\r
  UINT32                         SecurePL1TimerFlags;\r
  UINT32                         NonSecurePL1TimerGSIV;\r
  UINT32                         NonSecurePL1TimerFlags;\r
  UINT32                         VirtualTimerGSIV;\r
  UINT32                         VirtualTimerFlags;\r
  UINT32                         NonSecurePL2TimerGSIV;\r
  UINT32                         NonSecurePL2TimerFlags;\r
} EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE;\r
\r
///\r
/// GTDT Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION  0x01\r
\r
///\r
/// Global Flags.  All other bits are reserved and must be 0.\r
///\r
#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT  BIT0\r
#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE               BIT1\r
\r
///\r
/// Timer Flags.  All other bits are reserved and must be 0.\r
///\r
#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE      BIT0\r
#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY  BIT1\r
\r
///\r
/// Boot Error Record Table (BERT)\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT32                         BootErrorRegionLength;\r
  UINT64                         BootErrorRegion;\r
} EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_HEADER;\r
\r
///\r
/// BERT Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_REVISION  0x01\r
\r
///\r
/// Boot Error Region Block Status Definition\r
///\r
typedef struct {\r
  UINT32    UncorrectableErrorValid     : 1;\r
  UINT32    CorrectableErrorValid       : 1;\r
  UINT32    MultipleUncorrectableErrors : 1;\r
  UINT32    MultipleCorrectableErrors   : 1;\r
  UINT32    ErrorDataEntryCount         : 10;\r
  UINT32    Reserved                    : 18;\r
} EFI_ACPI_5_0_ERROR_BLOCK_STATUS;\r
\r
///\r
/// Boot Error Region Definition\r
///\r
typedef struct {\r
  EFI_ACPI_5_0_ERROR_BLOCK_STATUS    BlockStatus;\r
  UINT32                             RawDataOffset;\r
  UINT32                             RawDataLength;\r
  UINT32                             DataLength;\r
  UINT32                             ErrorSeverity;\r
} EFI_ACPI_5_0_BOOT_ERROR_REGION_STRUCTURE;\r
\r
//\r
// Boot Error Severity types\r
//\r
#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTABLE  0x00\r
#define EFI_ACPI_5_0_ERROR_SEVERITY_FATAL        0x01\r
#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTED    0x02\r
#define EFI_ACPI_5_0_ERROR_SEVERITY_NONE         0x03\r
\r
///\r
/// Generic Error Data Entry Definition\r
///\r
typedef struct {\r
  UINT8     SectionType[16];\r
  UINT32    ErrorSeverity;\r
  UINT16    Revision;\r
  UINT8     ValidationBits;\r
  UINT8     Flags;\r
  UINT32    ErrorDataLength;\r
  UINT8     FruId[16];\r
  UINT8     FruText[20];\r
} EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\r
\r
///\r
/// Generic Error Data Entry Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_REVISION  0x0201\r
\r
///\r
/// HEST - Hardware Error Source Table\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT32                         ErrorSourceCount;\r
} EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\r
\r
///\r
/// HEST Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION  0x01\r
\r
//\r
// Error Source structure types.\r
//\r
#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION  0x00\r
#define EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK  0x01\r
#define EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR                0x02\r
#define EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER                  0x06\r
#define EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER                     0x07\r
#define EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER                     0x08\r
#define EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR                     0x09\r
\r
//\r
// Error Source structure flags.\r
//\r
#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST  (1 << 0)\r
#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_GLOBAL          (1 << 1)\r
\r
///\r
/// IA-32 Architecture Machine Check Exception Structure Definition\r
///\r
typedef struct {\r
  UINT16    Type;\r
  UINT16    SourceId;\r
  UINT8     Reserved0[2];\r
  UINT8     Flags;\r
  UINT8     Enabled;\r
  UINT32    NumberOfRecordsToPreAllocate;\r
  UINT32    MaxSectionsPerRecord;\r
  UINT64    GlobalCapabilityInitData;\r
  UINT64    GlobalControlInitData;\r
  UINT8     NumberOfHardwareBanks;\r
  UINT8     Reserved1[7];\r
} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure Definition\r
///\r
typedef struct {\r
  UINT8     BankNumber;\r
  UINT8     ClearStatusOnInitialization;\r
  UINT8     StatusDataFormat;\r
  UINT8     Reserved0;\r
  UINT32    ControlRegisterMsrAddress;\r
  UINT64    ControlInitData;\r
  UINT32    StatusRegisterMsrAddress;\r
  UINT32    AddressRegisterMsrAddress;\r
  UINT32    MiscRegisterMsrAddress;\r
} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure MCA data format\r
///\r
#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32     0x00\r
#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64  0x01\r
#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64    0x02\r
\r
//\r
// Hardware Error Notification types. All other values are reserved\r
//\r
#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_POLLED              0x00\r
#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT  0x01\r
#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT     0x02\r
#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_SCI                 0x03\r
#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_NMI                 0x04\r
\r
///\r
/// Hardware Error Notification Configuration Write Enable Structure Definition\r
///\r
typedef struct {\r
  UINT16    Type                           : 1;\r
  UINT16    PollInterval                   : 1;\r
  UINT16    SwitchToPollingThresholdValue  : 1;\r
  UINT16    SwitchToPollingThresholdWindow : 1;\r
  UINT16    ErrorThresholdValue            : 1;\r
  UINT16    ErrorThresholdWindow           : 1;\r
  UINT16    Reserved                       : 10;\r
} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\r
\r
///\r
/// Hardware Error Notification Structure Definition\r
///\r
typedef struct {\r
  UINT8                                                                            Type;\r
  UINT8                                                                            Length;\r
  EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE    ConfigurationWriteEnable;\r
  UINT32                                                                           PollInterval;\r
  UINT32                                                                           Vector;\r
  UINT32                                                                           SwitchToPollingThresholdValue;\r
  UINT32                                                                           SwitchToPollingThresholdWindow;\r
  UINT32                                                                           ErrorThresholdValue;\r
  UINT32                                                                           ErrorThresholdWindow;\r
} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Corrected Machine Check Structure Definition\r
///\r
typedef struct {\r
  UINT16                                                Type;\r
  UINT16                                                SourceId;\r
  UINT8                                                 Reserved0[2];\r
  UINT8                                                 Flags;\r
  UINT8                                                 Enabled;\r
  UINT32                                                NumberOfRecordsToPreAllocate;\r
  UINT32                                                MaxSectionsPerRecord;\r
  EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE    NotificationStructure;\r
  UINT8                                                 NumberOfHardwareBanks;\r
  UINT8                                                 Reserved1[3];\r
} EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture NMI Error Structure Definition\r
///\r
typedef struct {\r
  UINT16    Type;\r
  UINT16    SourceId;\r
  UINT8     Reserved0[2];\r
  UINT32    NumberOfRecordsToPreAllocate;\r
  UINT32    MaxSectionsPerRecord;\r
  UINT32    MaxRawDataLength;\r
} EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\r
\r
///\r
/// PCI Express Root Port AER Structure Definition\r
///\r
typedef struct {\r
  UINT16    Type;\r
  UINT16    SourceId;\r
  UINT8     Reserved0[2];\r
  UINT8     Flags;\r
  UINT8     Enabled;\r
  UINT32    NumberOfRecordsToPreAllocate;\r
  UINT32    MaxSectionsPerRecord;\r
  UINT32    Bus;\r
  UINT16    Device;\r
  UINT16    Function;\r
  UINT16    DeviceControl;\r
  UINT8     Reserved1[2];\r
  UINT32    UncorrectableErrorMask;\r
  UINT32    UncorrectableErrorSeverity;\r
  UINT32    CorrectableErrorMask;\r
  UINT32    AdvancedErrorCapabilitiesAndControl;\r
  UINT32    RootErrorCommand;\r
} EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Device AER Structure Definition\r
///\r
typedef struct {\r
  UINT16    Type;\r
  UINT16    SourceId;\r
  UINT8     Reserved0[2];\r
  UINT8     Flags;\r
  UINT8     Enabled;\r
  UINT32    NumberOfRecordsToPreAllocate;\r
  UINT32    MaxSectionsPerRecord;\r
  UINT32    Bus;\r
  UINT16    Device;\r
  UINT16    Function;\r
  UINT16    DeviceControl;\r
  UINT8     Reserved1[2];\r
  UINT32    UncorrectableErrorMask;\r
  UINT32    UncorrectableErrorSeverity;\r
  UINT32    CorrectableErrorMask;\r
  UINT32    AdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Bridge AER Structure Definition\r
///\r
typedef struct {\r
  UINT16    Type;\r
  UINT16    SourceId;\r
  UINT8     Reserved0[2];\r
  UINT8     Flags;\r
  UINT8     Enabled;\r
  UINT32    NumberOfRecordsToPreAllocate;\r
  UINT32    MaxSectionsPerRecord;\r
  UINT32    Bus;\r
  UINT16    Device;\r
  UINT16    Function;\r
  UINT16    DeviceControl;\r
  UINT8     Reserved1[2];\r
  UINT32    UncorrectableErrorMask;\r
  UINT32    UncorrectableErrorSeverity;\r
  UINT32    CorrectableErrorMask;\r
  UINT32    AdvancedErrorCapabilitiesAndControl;\r
  UINT32    SecondaryUncorrectableErrorMask;\r
  UINT32    SecondaryUncorrectableErrorSeverity;\r
  UINT32    SecondaryAdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Structure Definition\r
///\r
typedef struct {\r
  UINT16                                                Type;\r
  UINT16                                                SourceId;\r
  UINT16                                                RelatedSourceId;\r
  UINT8                                                 Flags;\r
  UINT8                                                 Enabled;\r
  UINT32                                                NumberOfRecordsToPreAllocate;\r
  UINT32                                                MaxSectionsPerRecord;\r
  UINT32                                                MaxRawDataLength;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE                ErrorStatusAddress;\r
  EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE    NotificationStructure;\r
  UINT32                                                ErrorStatusBlockLength;\r
} EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\r
\r
///\r
/// Generic Error Status Definition\r
///\r
typedef struct {\r
  EFI_ACPI_5_0_ERROR_BLOCK_STATUS    BlockStatus;\r
  UINT32                             RawDataOffset;\r
  UINT32                             RawDataLength;\r
  UINT32                             DataLength;\r
  UINT32                             ErrorSeverity;\r
} EFI_ACPI_5_0_GENERIC_ERROR_STATUS_STRUCTURE;\r
\r
///\r
/// ERST - Error Record Serialization Table\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT32                         SerializationHeaderSize;\r
  UINT8                          Reserved0[4];\r
  UINT32                         InstructionEntryCount;\r
} EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\r
\r
///\r
/// ERST Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION  0x01\r
\r
///\r
/// ERST Serialization Actions\r
///\r
#define EFI_ACPI_5_0_ERST_BEGIN_WRITE_OPERATION                   0x00\r
#define EFI_ACPI_5_0_ERST_BEGIN_READ_OPERATION                    0x01\r
#define EFI_ACPI_5_0_ERST_BEGIN_CLEAR_OPERATION                   0x02\r
#define EFI_ACPI_5_0_ERST_END_OPERATION                           0x03\r
#define EFI_ACPI_5_0_ERST_SET_RECORD_OFFSET                       0x04\r
#define EFI_ACPI_5_0_ERST_EXECUTE_OPERATION                       0x05\r
#define EFI_ACPI_5_0_ERST_CHECK_BUSY_STATUS                       0x06\r
#define EFI_ACPI_5_0_ERST_GET_COMMAND_STATUS                      0x07\r
#define EFI_ACPI_5_0_ERST_GET_RECORD_IDENTIFIER                   0x08\r
#define EFI_ACPI_5_0_ERST_SET_RECORD_IDENTIFIER                   0x09\r
#define EFI_ACPI_5_0_ERST_GET_RECORD_COUNT                        0x0A\r
#define EFI_ACPI_5_0_ERST_BEGIN_DUMMY_WRITE_OPERATION             0x0B\r
#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE             0x0D\r
#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH      0x0E\r
#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES  0x0F\r
\r
///\r
/// ERST Action Command Status\r
///\r
#define EFI_ACPI_5_0_ERST_STATUS_SUCCESS                 0x00\r
#define EFI_ACPI_5_0_ERST_STATUS_NOT_ENOUGH_SPACE        0x01\r
#define EFI_ACPI_5_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE  0x02\r
#define EFI_ACPI_5_0_ERST_STATUS_FAILED                  0x03\r
#define EFI_ACPI_5_0_ERST_STATUS_RECORD_STORE_EMPTY      0x04\r
#define EFI_ACPI_5_0_ERST_STATUS_RECORD_NOT_FOUND        0x05\r
\r
///\r
/// ERST Serialization Instructions\r
///\r
#define EFI_ACPI_5_0_ERST_READ_REGISTER                  0x00\r
#define EFI_ACPI_5_0_ERST_READ_REGISTER_VALUE            0x01\r
#define EFI_ACPI_5_0_ERST_WRITE_REGISTER                 0x02\r
#define EFI_ACPI_5_0_ERST_WRITE_REGISTER_VALUE           0x03\r
#define EFI_ACPI_5_0_ERST_NOOP                           0x04\r
#define EFI_ACPI_5_0_ERST_LOAD_VAR1                      0x05\r
#define EFI_ACPI_5_0_ERST_LOAD_VAR2                      0x06\r
#define EFI_ACPI_5_0_ERST_STORE_VAR1                     0x07\r
#define EFI_ACPI_5_0_ERST_ADD                            0x08\r
#define EFI_ACPI_5_0_ERST_SUBTRACT                       0x09\r
#define EFI_ACPI_5_0_ERST_ADD_VALUE                      0x0A\r
#define EFI_ACPI_5_0_ERST_SUBTRACT_VALUE                 0x0B\r
#define EFI_ACPI_5_0_ERST_STALL                          0x0C\r
#define EFI_ACPI_5_0_ERST_STALL_WHILE_TRUE               0x0D\r
#define EFI_ACPI_5_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE  0x0E\r
#define EFI_ACPI_5_0_ERST_GOTO                           0x0F\r
#define EFI_ACPI_5_0_ERST_SET_SRC_ADDRESS_BASE           0x10\r
#define EFI_ACPI_5_0_ERST_SET_DST_ADDRESS_BASE           0x11\r
#define EFI_ACPI_5_0_ERST_MOVE_DATA                      0x12\r
\r
///\r
/// ERST Instruction Flags\r
///\r
#define EFI_ACPI_5_0_ERST_PRESERVE_REGISTER  0x01\r
\r
///\r
/// ERST Serialization Instruction Entry\r
///\r
typedef struct {\r
  UINT8                                     SerializationAction;\r
  UINT8                                     Instruction;\r
  UINT8                                     Flags;\r
  UINT8                                     Reserved0;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    RegisterRegion;\r
  UINT64                                    Value;\r
  UINT64                                    Mask;\r
} EFI_ACPI_5_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ - Error Injection Table\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT32                         InjectionHeaderSize;\r
  UINT8                          InjectionFlags;\r
  UINT8                          Reserved0[3];\r
  UINT32                         InjectionEntryCount;\r
} EFI_ACPI_5_0_ERROR_INJECTION_TABLE_HEADER;\r
\r
///\r
/// EINJ Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_REVISION  0x01\r
\r
///\r
/// EINJ Error Injection Actions\r
///\r
#define EFI_ACPI_5_0_EINJ_BEGIN_INJECTION_OPERATION       0x00\r
#define EFI_ACPI_5_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE  0x01\r
#define EFI_ACPI_5_0_EINJ_SET_ERROR_TYPE                  0x02\r
#define EFI_ACPI_5_0_EINJ_GET_ERROR_TYPE                  0x03\r
#define EFI_ACPI_5_0_EINJ_END_OPERATION                   0x04\r
#define EFI_ACPI_5_0_EINJ_EXECUTE_OPERATION               0x05\r
#define EFI_ACPI_5_0_EINJ_CHECK_BUSY_STATUS               0x06\r
#define EFI_ACPI_5_0_EINJ_GET_COMMAND_STATUS              0x07\r
#define EFI_ACPI_5_0_EINJ_TRIGGER_ERROR                   0xFF\r
\r
///\r
/// EINJ Action Command Status\r
///\r
#define EFI_ACPI_5_0_EINJ_STATUS_SUCCESS          0x00\r
#define EFI_ACPI_5_0_EINJ_STATUS_UNKNOWN_FAILURE  0x01\r
#define EFI_ACPI_5_0_EINJ_STATUS_INVALID_ACCESS   0x02\r
\r
///\r
/// EINJ Error Type Definition\r
///\r
#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_CORRECTABLE               (1 << 0)\r
#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL    (1 << 1)\r
#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL       (1 << 2)\r
#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_CORRECTABLE                  (1 << 3)\r
#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL       (1 << 4)\r
#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL          (1 << 5)\r
#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE             (1 << 6)\r
#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL  (1 << 7)\r
#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL     (1 << 8)\r
#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_CORRECTABLE                (1 << 9)\r
#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL     (1 << 10)\r
#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL        (1 << 11)\r
\r
///\r
/// EINJ Injection Instructions\r
///\r
#define EFI_ACPI_5_0_EINJ_READ_REGISTER         0x00\r
#define EFI_ACPI_5_0_EINJ_READ_REGISTER_VALUE   0x01\r
#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER        0x02\r
#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER_VALUE  0x03\r
#define EFI_ACPI_5_0_EINJ_NOOP                  0x04\r
\r
///\r
/// EINJ Instruction Flags\r
///\r
#define EFI_ACPI_5_0_EINJ_PRESERVE_REGISTER  0x01\r
\r
///\r
/// EINJ Injection Instruction Entry\r
///\r
typedef struct {\r
  UINT8                                     InjectionAction;\r
  UINT8                                     Instruction;\r
  UINT8                                     Flags;\r
  UINT8                                     Reserved0;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    RegisterRegion;\r
  UINT64                                    Value;\r
  UINT64                                    Mask;\r
} EFI_ACPI_5_0_EINJ_INJECTION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ Trigger Action Table\r
///\r
typedef struct {\r
  UINT32    HeaderSize;\r
  UINT32    Revision;\r
  UINT32    TableSize;\r
  UINT32    EntryCount;\r
} EFI_ACPI_5_0_EINJ_TRIGGER_ACTION_TABLE;\r
\r
///\r
/// Platform Communications Channel Table (PCCT)\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
  UINT32                         Flags;\r
  UINT64                         Reserved;\r
} EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\r
\r
///\r
/// PCCT Version (as defined in ACPI 5.0 spec.)\r
///\r
#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION  0x01\r
\r
///\r
/// PCCT Global Flags\r
///\r
#define EFI_ACPI_5_0_PCCT_FLAGS_SCI_DOORBELL  BIT0\r
\r
//\r
// PCCT Subspace type\r
//\r
#define EFI_ACPI_5_0_PCCT_SUBSPACE_TYPE_GENERIC  0x00\r
\r
///\r
/// PCC Subspace Structure Header\r
///\r
typedef struct {\r
  UINT8    Type;\r
  UINT8    Length;\r
} EFI_ACPI_5_0_PCCT_SUBSPACE_HEADER;\r
\r
///\r
/// Generic Communications Subspace Structure\r
///\r
typedef struct {\r
  UINT8                                     Type;\r
  UINT8                                     Length;\r
  UINT8                                     Reserved[6];\r
  UINT64                                    BaseAddress;\r
  UINT64                                    AddressLength;\r
  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE    DoorbellRegister;\r
  UINT64                                    DoorbellPreserve;\r
  UINT64                                    DoorbellWrite;\r
  UINT32                                    NominalLatency;\r
  UINT32                                    MaximumPeriodicAccessRate;\r
  UINT16                                    MinimumRequestTurnaroundTime;\r
} EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC;\r
\r
///\r
/// Generic Communications Channel Shared Memory Region\r
///\r
\r
typedef struct {\r
  UINT8    Command;\r
  UINT8    Reserved    : 7;\r
  UINT8    GenerateSci : 1;\r
} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\r
\r
typedef struct {\r
  UINT8    CommandComplete      : 1;\r
  UINT8    SciDoorbell          : 1;\r
  UINT8    Error                : 1;\r
  UINT8    PlatformNotification : 1;\r
  UINT8    Reserved             : 4;\r
  UINT8    Reserved1;\r
} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\r
\r
typedef struct {\r
  UINT32                                                    Signature;\r
  EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND    Command;\r
  EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS     Status;\r
} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\r
\r
//\r
// Known table signatures\r
//\r
\r
///\r
/// "RSD PTR " Root System Description Pointer\r
///\r
#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\r
\r
///\r
/// "APIC" Multiple APIC Description Table\r
///\r
#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')\r
\r
///\r
/// "BERT" Boot Error Record Table\r
///\r
#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE  SIGNATURE_32('B', 'E', 'R', 'T')\r
\r
///\r
/// "BGRT" Boot Graphics Resource Table\r
///\r
#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('B', 'G', 'R', 'T')\r
\r
///\r
/// "CPEP" Corrected Platform Error Polling Table\r
///\r
#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE  SIGNATURE_32('C', 'P', 'E', 'P')\r
\r
///\r
/// "DSDT" Differentiated System Description Table\r
///\r
#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')\r
\r
///\r
/// "ECDT" Embedded Controller Boot Resources Table\r
///\r
#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE  SIGNATURE_32('E', 'C', 'D', 'T')\r
\r
///\r
/// "EINJ" Error Injection Table\r
///\r
#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'I', 'N', 'J')\r
\r
///\r
/// "ERST" Error Record Serialization Table\r
///\r
#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE  SIGNATURE_32('E', 'R', 'S', 'T')\r
\r
///\r
/// "FACP" Fixed ACPI Description Table\r
///\r
#define EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')\r
\r
///\r
/// "FACS" Firmware ACPI Control Structure\r
///\r
#define EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')\r
\r
///\r
/// "FPDT" Firmware Performance Data Table\r
///\r
#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE  SIGNATURE_32('F', 'P', 'D', 'T')\r
\r
///\r
/// "GTDT" Generic Timer Description Table\r
///\r
#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('G', 'T', 'D', 'T')\r
\r
///\r
/// "HEST" Hardware Error Source Table\r
///\r
#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE  SIGNATURE_32('H', 'E', 'S', 'T')\r
\r
///\r
/// "MPST" Memory Power State Table\r
///\r
#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_SIGNATURE  SIGNATURE_32('M', 'P', 'S', 'T')\r
\r
///\r
/// "MSCT" Maximum System Characteristics Table\r
///\r
#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'C', 'T')\r
\r
///\r
/// "PMTT" Platform Memory Topology Table\r
///\r
#define EFI_ACPI_5_0_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE  SIGNATURE_32('P', 'M', 'T', 'T')\r
\r
///\r
/// "PSDT" Persistent System Description Table\r
///\r
#define EFI_ACPI_5_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')\r
\r
///\r
/// "RASF" ACPI RAS Feature Table\r
///\r
#define EFI_ACPI_5_0_ACPI_RAS_FEATURE_TABLE_SIGNATURE  SIGNATURE_32('R', 'A', 'S', 'F')\r
\r
///\r
/// "RSDT" Root System Description Table\r
///\r
#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')\r
\r
///\r
/// "SBST" Smart Battery Specification Table\r
///\r
#define EFI_ACPI_5_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')\r
\r
///\r
/// "SLIT" System Locality Information Table\r
///\r
#define EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')\r
\r
///\r
/// "SRAT" System Resource Affinity Table\r
///\r
#define EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE  SIGNATURE_32('S', 'R', 'A', 'T')\r
\r
///\r
/// "SSDT" Secondary System Description Table\r
///\r
#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')\r
\r
///\r
/// "XSDT" Extended System Description Table\r
///\r
#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('X', 'S', 'D', 'T')\r
\r
///\r
/// "BOOT" MS Simple Boot Spec\r
///\r
#define EFI_ACPI_5_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE  SIGNATURE_32('B', 'O', 'O', 'T')\r
\r
///\r
/// "CSRT" MS Core System Resource Table\r
///\r
#define EFI_ACPI_5_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('C', 'S', 'R', 'T')\r
\r
///\r
/// "DBG2" MS Debug Port 2 Spec\r
///\r
#define EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', '2')\r
\r
///\r
/// "DBGP" MS Debug Port Spec\r
///\r
#define EFI_ACPI_5_0_DEBUG_PORT_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', 'P')\r
\r
///\r
/// "DMAR" DMA Remapping Table\r
///\r
#define EFI_ACPI_5_0_DMA_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('D', 'M', 'A', 'R')\r
\r
///\r
/// "DRTM" Dynamic Root of Trust for Measurement Table\r
///\r
#define EFI_ACPI_5_0_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE  SIGNATURE_32('D', 'R', 'T', 'M')\r
\r
///\r
/// "ETDT" Event Timer Description Table\r
///\r
#define EFI_ACPI_5_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'T', 'D', 'T')\r
\r
///\r
/// "HPET" IA-PC High Precision Event Timer Table\r
///\r
#define EFI_ACPI_5_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE  SIGNATURE_32('H', 'P', 'E', 'T')\r
\r
///\r
/// "iBFT" iSCSI Boot Firmware Table\r
///\r
#define EFI_ACPI_5_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE  SIGNATURE_32('i', 'B', 'F', 'T')\r
\r
///\r
/// "IVRS" I/O Virtualization Reporting Structure\r
///\r
#define EFI_ACPI_5_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE  SIGNATURE_32('I', 'V', 'R', 'S')\r
\r
///\r
/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table\r
///\r
#define EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')\r
\r
///\r
/// "MCHI" Management Controller Host Interface Table\r
///\r
#define EFI_ACPI_5_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'H', 'I')\r
\r
///\r
/// "MSDM" MS Data Management Table\r
///\r
#define EFI_ACPI_5_0_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')\r
\r
///\r
/// "PCCT" Platform Communications Channel Table\r
///\r
#define EFI_ACPI_5_0_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE  SIGNATURE_32('P', 'C', 'C', 'T')\r
\r
///\r
/// "SLIC" MS Software Licensing Table Specification\r
///\r
#define EFI_ACPI_5_0_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')\r
\r
///\r
/// "SPCR" Serial Port Console Redirection Table\r
///\r
#define EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')\r
\r
///\r
/// "SPMI" Server Platform Management Interface Table\r
///\r
#define EFI_ACPI_5_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'M', 'I')\r
\r
///\r
/// "TCPA" Trusted Computing Platform Alliance Capabilities Table\r
///\r
#define EFI_ACPI_5_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE  SIGNATURE_32('T', 'C', 'P', 'A')\r
\r
///\r
/// "TPM2" Trusted Computing Platform 1 Table\r
///\r
#define EFI_ACPI_5_0_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE  SIGNATURE_32('T', 'P', 'M', '2')\r
\r
///\r
/// "UEFI" UEFI ACPI Data Table\r
///\r
#define EFI_ACPI_5_0_UEFI_ACPI_DATA_TABLE_SIGNATURE  SIGNATURE_32('U', 'E', 'F', 'I')\r
\r
///\r
/// "WAET" Windows ACPI Emulated Devices Table\r
///\r
#define EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE  SIGNATURE_32('W', 'A', 'E', 'T')\r
#define EFI_ACPI_5_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE     EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE\r
\r
///\r
/// "WDAT" Watchdog Action Table\r
///\r
#define EFI_ACPI_5_0_WATCHDOG_ACTION_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'A', 'T')\r
\r
///\r
/// "WDRT" Watchdog Resource Table\r
///\r
#define EFI_ACPI_5_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'R', 'T')\r
\r
///\r
/// "WPBT" MS Platform Binary Table\r
///\r
#define EFI_ACPI_5_0_PLATFORM_BINARY_TABLE_SIGNATURE  SIGNATURE_32('W', 'P', 'B', 'T')\r
\r
#pragma pack()\r
\r
#endif\r