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[mirror_edk2.git] / MdePkg / Include / IndustryStandard / ArmErrorSourceTable.h

/** @file\r
  Arm Error Source Table as described in the\r
  'ACPI for the Armv8 RAS Extensions 1.1' Specification.\r
\r
  Copyright (c) 2020 Arm Limited.\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Reference(s):\r
    - ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document,\r
      dated 28 September 2020.\r
      (https://developer.arm.com/documentation/den0085/0101/)\r
\r
  @par Glossary\r
    - Ref : Reference\r
    - Id  : Identifier\r
**/\r
\r
#ifndef ARM_ERROR_SOURCE_TABLE_H_\r
#define ARM_ERROR_SOURCE_TABLE_H_\r
\r
///\r
/// "AEST" Arm Error Source Table\r
///\r
#define EFI_ACPI_6_3_ARM_ERROR_SOURCE_TABLE_SIGNATURE  SIGNATURE_32('A', 'E', 'S', 'T')\r
\r
#define EFI_ACPI_ARM_ERROR_SOURCE_TABLE_REVISION  1\r
\r
#pragma pack(1)\r
\r
///\r
/// Arm Error Source Table definition.\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
} EFI_ACPI_ARM_ERROR_SOURCE_TABLE;\r
\r
///\r
/// AEST Node structure.\r
///\r
typedef struct {\r
  /// Node type:\r
  ///   0x00 - Processor error node\r
  ///   0x01 - Memory error node\r
  ///   0x02 - SMMU error node\r
  ///   0x03 - Vendor-defined error node\r
  ///   0x04 - GIC error node\r
  UINT8     Type;\r
\r
  /// Length of structure in bytes.\r
  UINT16    Length;\r
\r
  /// Reserved - Must be zero.\r
  UINT8     Reserved;\r
\r
  /// Offset from the start of the node to node-specific data.\r
  UINT32    DataOffset;\r
\r
  /// Offset from the start of the node to the node interface structure.\r
  UINT32    InterfaceOffset;\r
\r
  /// Offset from the start of the node to node interrupt array.\r
  UINT32    InterruptArrayOffset;\r
\r
  /// Number of entries in the interrupt array.\r
  UINT32    InterruptArrayCount;\r
\r
  // Generic node data\r
\r
  /// The timestamp frequency of the counter in Hz.\r
  UINT64    TimestampRate;\r
\r
  /// Reserved - Must be zero.\r
  UINT64    Reserved1;\r
\r
  /// The rate in Hz at which the Error Generation Counter decrements.\r
  UINT64    ErrorInjectionCountdownRate;\r
} EFI_ACPI_AEST_NODE_STRUCT;\r
\r
// AEST Node type definitions\r
#define EFI_ACPI_AEST_NODE_TYPE_PROCESSOR       0x0\r
#define EFI_ACPI_AEST_NODE_TYPE_MEMORY          0x1\r
#define EFI_ACPI_AEST_NODE_TYPE_SMMU            0x2\r
#define EFI_ACPI_AEST_NODE_TYPE_VENDOR_DEFINED  0x3\r
#define EFI_ACPI_AEST_NODE_TYPE_GIC             0x4\r
\r
///\r
/// AEST Node Interface structure.\r
///\r
typedef struct {\r
  /// Interface type:\r
  ///   0x0 - System register (SR)\r
  ///   0x1 - Memory mapped (MMIO)\r
  UINT8     Type;\r
\r
  /// Reserved - Must be zero.\r
  UINT8     Reserved[3];\r
\r
  /// AEST node interface flags.\r
  UINT32    Flags;\r
\r
  /// Base address of error group that contains the error node.\r
  UINT64    BaseAddress;\r
\r
  /// Zero-based index of the first standard error record that\r
  /// belongs to this node.\r
  UINT32    StartErrorRecordIndex;\r
\r
  /// Number of error records in this node including both\r
  /// implemented and unimplemented records.\r
  UINT32    NumberErrorRecords;\r
\r
  /// A bitmap indicating the error records within this\r
  /// node that are implemented in the current system.\r
  UINT64    ErrorRecordImplemented;\r
\r
  /// A bitmap indicating the error records within this node that\r
  /// support error status reporting through the ERRGSR register.\r
  UINT64    ErrorRecordStatusReportingSupported;\r
\r
  /// A bitmap indicating the addressing mode used by each error\r
  /// record within this node to populate the ERR<n>_ADDR register.\r
  UINT64    AddressingMode;\r
} EFI_ACPI_AEST_INTERFACE_STRUCT;\r
\r
// AEST Interface node type definitions.\r
#define EFI_ACPI_AEST_INTERFACE_TYPE_SR    0x0\r
#define EFI_ACPI_AEST_INTERFACE_TYPE_MMIO  0x1\r
\r
// AEST node interface flag definitions.\r
#define EFI_ACPI_AEST_INTERFACE_FLAG_PRIVATE      0\r
#define EFI_ACPI_AEST_INTERFACE_FLAG_SHARED       BIT0\r
#define EFI_ACPI_AEST_INTERFACE_FLAG_CLEAR_MISCX  BIT1\r
\r
///\r
/// AEST Node Interrupt structure.\r
///\r
typedef struct {\r
  /// Interrupt type:\r
  ///   0x0 - Fault Handling Interrupt\r
  ///   0x1 - Error Recovery Interrupt\r
  UINT8     InterruptType;\r
\r
  /// Reserved - Must be zero.\r
  UINT8     Reserved[2];\r
\r
  /// Interrupt flags\r
  /// Bits [31:1]: Must be zero.\r
  /// Bit 0:\r
  ///   0b - Interrupt is edge-triggered\r
  ///   1b - Interrupt is level-triggered\r
  UINT8     InterruptFlags;\r
\r
  /// GSIV of interrupt, if interrupt is an SPI or a PPI.\r
  UINT32    InterruptGsiv;\r
\r
  /// If MSI is supported, then this field must be set to the\r
  /// Identifier field of the IORT ITS Group node.\r
  UINT8     ItsGroupRefId;\r
\r
  /// Reserved - must be zero.\r
  UINT8     Reserved1[3];\r
} EFI_ACPI_AEST_INTERRUPT_STRUCT;\r
\r
// AEST Interrupt node - interrupt type defintions.\r
#define EFI_ACPI_AEST_INTERRUPT_TYPE_FAULT_HANDLING  0x0\r
#define EFI_ACPI_AEST_INTERRUPT_TYPE_ERROR_RECOVERY  0x1\r
\r
// AEST Interrupt node - interrupt flag defintions.\r
#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_EDGE   0\r
#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_LEVEL  BIT0\r
\r
///\r
/// Cache Processor Resource structure.\r
///\r
typedef struct {\r
  /// Reference to the cache structure in the PPTT table.\r
  UINT32    CacheRefId;\r
\r
  /// Reserved\r
  UINT32    Reserved;\r
} EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT;\r
\r
///\r
/// TLB Processor Resource structure.\r
///\r
typedef struct {\r
  /// TLB level from perspective of current processor.\r
  UINT32    TlbRefId;\r
\r
  /// Reserved\r
  UINT32    Reserved;\r
} EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT;\r
\r
///\r
/// Processor Generic Resource structure.\r
///\r
typedef struct {\r
  /// Vendor-defined supplementary data.\r
  UINT32    Data;\r
} EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT;\r
\r
///\r
/// AEST Processor Resource union.\r
///\r
typedef union {\r
  /// Processor Cache resource.\r
  EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT      Cache;\r
\r
  /// Processor TLB resource.\r
  EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT        Tlb;\r
\r
  /// Processor Generic resource.\r
  EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT    Generic;\r
} EFI_ACPI_AEST_PROCESSOR_RESOURCE;\r
\r
///\r
/// AEST Processor structure.\r
///\r
typedef struct {\r
  /// AEST Node header\r
  EFI_ACPI_AEST_NODE_STRUCT           NodeHeader;\r
\r
  /// Processor ID of node.\r
  UINT32                              AcpiProcessorId;\r
\r
  /// Resource type of the processor node.\r
  ///   0x0 - Cache\r
  ///   0x1 - TLB\r
  ///   0x2 - Generic\r
  UINT8                               ResourceType;\r
\r
  /// Reserved - must be zero.\r
  UINT8                               Reserved;\r
\r
  /// Processor structure flags.\r
  UINT8                               Flags;\r
\r
  /// Processor structure revision.\r
  UINT8                               Revision;\r
\r
  /// Processor affinity descriptor for the resource that this\r
  /// error node pertains to.\r
  UINT64                              ProcessorAffinityLevelIndicator;\r
\r
  /// Processor resource\r
  EFI_ACPI_AEST_PROCESSOR_RESOURCE    Resource;\r
\r
  // Node Interface\r
  // EFI_ACPI_AEST_INTERFACE_STRUCT   NodeInterface;\r
\r
  // Node Interrupt Array\r
  // EFI_ACPI_AEST_INTERRUPT_STRUCT   NodeInterruptArray[n];\r
} EFI_ACPI_AEST_PROCESSOR_STRUCT;\r
\r
// AEST Processor resource type definitions.\r
#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_CACHE    0x0\r
#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_TLB      0x1\r
#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_GENERIC  0x2\r
\r
// AEST Processor flag definitions.\r
#define EFI_ACPI_AEST_PROCESSOR_FLAG_GLOBAL  BIT0\r
#define EFI_ACPI_AEST_PROCESSOR_FLAG_SHARED  BIT1\r
\r
///\r
/// Memory Controller structure.\r
///\r
typedef struct {\r
  /// AEST Node header\r
  EFI_ACPI_AEST_NODE_STRUCT    NodeHeader;\r
\r
  /// SRAT proximity domain.\r
  UINT32                       ProximityDomain;\r
\r
  // Node Interface\r
  // EFI_ACPI_AEST_INTERFACE_STRUCT   NodeInterface;\r
\r
  // Node Interrupt Array\r
  // EFI_ACPI_AEST_INTERRUPT_STRUCT   NodeInterruptArray[n];\r
} EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT;\r
\r
///\r
/// SMMU structure.\r
///\r
typedef struct {\r
  /// AEST Node header\r
  EFI_ACPI_AEST_NODE_STRUCT    NodeHeader;\r
\r
  /// Reference to the IORT table node that describes this SMMU.\r
  UINT32                       SmmuRefId;\r
\r
  /// Reference to the IORT table node that is associated with the\r
  /// sub-component within this SMMU.\r
  UINT32                       SubComponentRefId;\r
\r
  // Node Interface\r
  // EFI_ACPI_AEST_INTERFACE_STRUCT   NodeInterface;\r
\r
  // Node Interrupt Array\r
  // EFI_ACPI_AEST_INTERRUPT_STRUCT   NodeInterruptArray[n];\r
} EFI_ACPI_AEST_SMMU_STRUCT;\r
\r
///\r
/// Vendor-Defined structure.\r
///\r
typedef struct {\r
  /// AEST Node header\r
  EFI_ACPI_AEST_NODE_STRUCT    NodeHeader;\r
\r
  /// ACPI HID of the component.\r
  UINT32                       HardwareId;\r
\r
  /// The ACPI Unique identifier of the component.\r
  UINT32                       UniqueId;\r
\r
  /// Vendor-specific data, for example to identify this error source.\r
  UINT8                        VendorData[16];\r
\r
  // Node Interface\r
  // EFI_ACPI_AEST_INTERFACE_STRUCT   NodeInterface;\r
\r
  // Node Interrupt Array\r
  // EFI_ACPI_AEST_INTERRUPT_STRUCT   NodeInterruptArray[n];\r
} EFI_ACPI_AEST_VENDOR_DEFINED_STRUCT;\r
\r
///\r
/// GIC structure.\r
///\r
typedef struct {\r
  /// AEST Node header\r
  EFI_ACPI_AEST_NODE_STRUCT    NodeHeader;\r
\r
  /// Type of GIC interface that is associated with this error node.\r
  ///   0x0 - GIC CPU (GICC)\r
  ///   0x1 - GIC Distributor (GICD)\r
  ///   0x2 - GIC Resistributor (GICR)\r
  ///   0x3 - GIC ITS (GITS)\r
  UINT32                       InterfaceType;\r
\r
  /// Identifier for the interface instance.\r
  UINT32                       GicInterfaceRefId;\r
\r
  // Node Interface\r
  // EFI_ACPI_AEST_INTERFACE_STRUCT   NodeInterface;\r
\r
  // Node Interrupt Array\r
  // EFI_ACPI_AEST_INTERRUPT_STRUCT   NodeInterruptArray[n];\r
} EFI_ACPI_AEST_GIC_STRUCT;\r
\r
// AEST GIC interface type definitions.\r
#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICC  0x0\r
#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICD  0x1\r
#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICR  0x2\r
#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GITS  0x3\r
\r
#pragma pack()\r
\r
#endif // ARM_ERROR_SOURCE_TABLE_H_\r