[mirror_edk2.git] / MdePkg / Include / IndustryStandard / DmaRemappingReportingTable.h

/** @file\r
  DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)\r
  Virtualization Technology for Directed I/O (VT-D) Architecture Specification.\r
\r
  Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Revision Reference:\r
    - Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture\r
      Specification v3.2, Dated October 2020.\r
      https://software.intel.com/content/dam/develop/external/us/en/documents/vt-directed-io-spec.pdf\r
\r
  @par Glossary:\r
    - HPET - High Precision Event Timer\r
    - NUMA - Non-uniform Memory Access\r
**/\r
\r
#ifndef _DMA_REMAPPING_REPORTING_TABLE_H_\r
#define _DMA_REMAPPING_REPORTING_TABLE_H_\r
\r
#include <IndustryStandard/Acpi.h>\r
\r
#pragma pack(1)\r
\r
///\r
/// DMA-Remapping Reporting Structure definitions from section 8.1\r
///@{\r
#define EFI_ACPI_DMAR_REVISION  0x01\r
\r
#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP                     BIT0\r
#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT                 BIT1\r
#define EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG  BIT2\r
///@}\r
\r
///\r
/// Remapping Structure Types definitions from section 8.2\r
///@{\r
#define EFI_ACPI_DMAR_TYPE_DRHD  0x00\r
#define EFI_ACPI_DMAR_TYPE_RMRR  0x01\r
#define EFI_ACPI_DMAR_TYPE_ATSR  0x02\r
#define EFI_ACPI_DMAR_TYPE_RHSA  0x03\r
#define EFI_ACPI_DMAR_TYPE_ANDD  0x04\r
#define EFI_ACPI_DMAR_TYPE_SATC  0x05\r
///@}\r
\r
///\r
/// DMA-Remapping Hardware Unit definitions from section 8.3\r
///\r
#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL  BIT0\r
\r
///\r
/// DMA-Remapping Device Scope Entry Structure definitions from section 8.3.1\r
///@{\r
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT           0x01\r
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE             0x02\r
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC                 0x03\r
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET       0x04\r
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE  0x05\r
///@}\r
\r
///\r
/// Root Port ATS Capability Reporting Structure definitions from section 8.5\r
///\r
#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS  BIT0\r
\r
///\r
/// Definition for DMA Remapping Structure Header\r
///\r
typedef struct {\r
  UINT16    Type;\r
  UINT16    Length;\r
} EFI_ACPI_DMAR_STRUCTURE_HEADER;\r
\r
///\r
/// Definition for DMA-Remapping PCI Path\r
///\r
typedef struct {\r
  UINT8    Device;\r
  UINT8    Function;\r
} EFI_ACPI_DMAR_PCI_PATH;\r
\r
///\r
/// Device Scope Structure is defined in section 8.3.1\r
///\r
typedef struct {\r
  UINT8     Type;\r
  UINT8     Length;\r
  UINT16    Reserved2;\r
  UINT8     EnumerationId;\r
  UINT8     StartBusNumber;\r
} EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER;\r
\r
/**\r
  DMA-remapping hardware unit definition (DRHD) structure is defined in\r
  section 8.3. This uniquely represents a remapping hardware unit present\r
  in the platform. There must be at least one instance of this structure\r
  for each PCI segment in the platform.\r
**/\r
typedef struct {\r
  EFI_ACPI_DMAR_STRUCTURE_HEADER    Header;\r
\r
  /**\r
    - Bit[0]: INCLUDE_PCI_ALL\r
              - If Set, this remapping hardware unit has under its scope all\r
                PCI compatible devices in the specified Segment, except devices\r
                reported under the scope of other remapping hardware units for\r
                the same Segment.\r
              - If Clear, this remapping hardware unit has under its scope only\r
                devices in the specified Segment that are explicitly identified\r
                through the DeviceScope field.\r
    - Bits[7:1] Reserved.\r
  **/\r
  UINT8     Flags;\r
  UINT8     Reserved;\r
  ///\r
  /// The PCI Segment associated with this unit.\r
  ///\r
  UINT16    SegmentNumber;\r
  ///\r
  /// Base address of remapping hardware register-set for this unit.\r
  ///\r
  UINT64    RegisterBaseAddress;\r
} EFI_ACPI_DMAR_DRHD_HEADER;\r
\r
/**\r
  Reserved Memory Region Reporting Structure (RMRR) is described in section 8.4\r
  Reserved memory ranges that may be DMA targets may be reported through the\r
  RMRR structures, along with the devices that requires access to the specified\r
  reserved memory region.\r
**/\r
typedef struct {\r
  EFI_ACPI_DMAR_STRUCTURE_HEADER    Header;\r
  UINT8                             Reserved[2];\r
  ///\r
  /// PCI Segment Number associated with devices identified through\r
  /// the Device Scope field.\r
  ///\r
  UINT16                            SegmentNumber;\r
  ///\r
  /// Base address of 4KB-aligned reserved memory region\r
  ///\r
  UINT64                            ReservedMemoryRegionBaseAddress;\r
\r
  /**\r
    Last address of the reserved memory region. Value in this field must be\r
    greater than the value in Reserved Memory Region Base Address field.\r
    The reserved memory region size (Limit - Base + 1) must be an integer\r
    multiple of 4KB.\r
  **/\r
  UINT64                            ReservedMemoryRegionLimitAddress;\r
} EFI_ACPI_DMAR_RMRR_HEADER;\r
\r
/**\r
  Root Port ATS Capability Reporting (ATSR) structure is defined in section 8.5.\r
  This structure is applicable only for platforms supporting Device-TLBs as\r
  reported through the Extended Capability Register. For each PCI Segment in\r
  the platform that supports Device-TLBs, BIOS provides an ATSR structure. The\r
  ATSR structures identifies PCI-Express Root-Ports supporting Address\r
  Translation Services (ATS) transactions. Software must enable ATS on endpoint\r
  devices behind a Root Port only if the Root Port is reported as supporting\r
  ATS transactions.\r
**/\r
typedef struct {\r
  EFI_ACPI_DMAR_STRUCTURE_HEADER    Header;\r
\r
  /**\r
    - Bit[0]: ALL_PORTS:\r
              - If Set, indicates all PCI Express Root Ports in the specified\r
                PCI Segment supports ATS transactions.\r
              - If Clear, indicates ATS transactions are supported only on\r
                Root Ports identified through the Device Scope field.\r
    - Bits[7:1] Reserved.\r
  **/\r
  UINT8     Flags;\r
  UINT8     Reserved;\r
  ///\r
  /// The PCI Segment associated with this ATSR structure\r
  ///\r
  UINT16    SegmentNumber;\r
} EFI_ACPI_DMAR_ATSR_HEADER;\r
\r
/**\r
  Remapping Hardware Static Affinity (RHSA) is an optional structure defined\r
  in section 8.6. This is intended to be used only on NUMA platforms with\r
  Remapping hardware units and memory spanned across multiple nodes.\r
  When used, there must be a RHSA structure for each Remapping hardware unit\r
  reported through DRHD structure.\r
**/\r
typedef struct {\r
  EFI_ACPI_DMAR_STRUCTURE_HEADER    Header;\r
  UINT8                             Reserved[4];\r
  ///\r
  /// Register Base Address of this Remap hardware unit reported in the\r
  /// corresponding DRHD structure.\r
  ///\r
  UINT64                            RegisterBaseAddress;\r
  ///\r
  /// Proximity Domain to which the Remap hardware unit identified by the\r
  /// Register Base Address field belongs.\r
  ///\r
  UINT32                            ProximityDomain;\r
} EFI_ACPI_DMAR_RHSA_HEADER;\r
\r
/**\r
  An ACPI Name-space Device Declaration (ANDD) structure is defined in section\r
  8.7 and uniquely represents an ACPI name-space enumerated device capable of\r
  issuing DMA requests in the platform. ANDD structures are used in conjunction\r
  with Device-Scope entries of type ACPI_NAMESPACE_DEVICE.\r
**/\r
typedef struct {\r
  EFI_ACPI_DMAR_STRUCTURE_HEADER    Header;\r
  UINT8                             Reserved[3];\r
\r
  /**\r
    Each ACPI device enumerated through an ANDD structure must have a unique\r
    value for this field. To report an ACPI device with ACPI Device Number\r
    value of X, under the scope of a DRHD unit, a Device-Scope entry of type\r
    ACPI_NAMESPACE_DEVICE is used with value of X in the Enumeration ID field.\r
    The Start Bus Number and Path fields in the Device-Scope together\r
    provides the 16-bit source-id allocated by platform for the ACPI device.\r
  **/\r
  UINT8    AcpiDeviceNumber;\r
} EFI_ACPI_DMAR_ANDD_HEADER;\r
\r
/**\r
  An SoC Integrated Address Translation Cache (SATC) reporting structure is\r
  defined in section 8.8.\r
**/\r
typedef struct {\r
  EFI_ACPI_DMAR_STRUCTURE_HEADER    Header;\r
\r
  /**\r
    - Bit[0]: ATC_REQUIRED:\r
              - If Set, indicates that every SoC integrated device enumerated\r
                in this table has a functional requirement to enable its ATC\r
                (via the ATS capability) for device operation.\r
              - If Clear, any device enumerated in this table can operate when\r
                its respective ATC is not enabled (albeit with reduced\r
                performance or functionality).\r
    - Bits[7:1] Reserved.\r
  **/\r
  UINT8     Flags;\r
  UINT8     Reserved;\r
  ///\r
  /// The PCI Segment associated with this SATC structure. All SoC integrated\r
  /// devices within a PCI segment with same value for Flags field must be\r
  /// enumerated in the same SATC structure.\r
  ///\r
  UINT16    SegmentNumber;\r
} EFI_ACPI_DMAR_SATC_HEADER;\r
\r
/**\r
  DMA Remapping Reporting Structure Header as defined in section 8.1\r
  This header will be followed by list of Remapping Structures listed below\r
    - DMA Remapping Hardware Unit Definition (DRHD)\r
    - Reserved Memory Region Reporting (RMRR)\r
    - Root Port ATS Capability Reporting (ATSR)\r
    - Remapping Hardware Static Affinity (RHSA)\r
    - ACPI Name-space Device Declaration (ANDD)\r
    - SoC Integrated Address Translation Cache reporting (SATC)\r
  These structure types must by reported in numerical order.\r
  i.e., All remapping structures of type 0 (DRHD) enumerated before remapping\r
  structures of type 1 (RMRR), and so forth.\r
**/\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER    Header;\r
\r
  /**\r
    This field indicates the maximum DMA physical addressability supported by\r
    this platform. The system address map reported by the BIOS indicates what\r
    portions of this addresses are populated. The Host Address Width (HAW) of\r
    the platform is computed as (N+1), where N is the value reported in this\r
    field.\r
    For example, for a platform supporting 40 bits of physical addressability,\r
    the value of 100111b is reported in this field.\r
  **/\r
  UINT8    HostAddressWidth;\r
\r
  /**\r
    - Bit[0]:   INTR_REMAP - If Clear, the platform does not support interrupt\r
                remapping. If Set, the platform supports interrupt remapping.\r
    - Bit[1]:   X2APIC_OPT_OUT - For firmware compatibility reasons, platform\r
                firmware may Set this field to request system software to opt\r
                out of enabling Extended xAPIC (X2APIC) mode. This field is\r
                valid only when the INTR_REMAP field (bit 0) is Set.\r
    - Bit[2]:   DMA_CTRL_PLATFORM_OPT_IN_FLAG - Platform firmware is\r
                recommended to Set this field to report any platform initiated\r
                DMA is restricted to only reserved memory regions (reported in\r
                RMRR structures) when transferring control to system software\r
                such as on ExitBootServices().\r
    - Bits[7:3] Reserved.\r
  **/\r
  UINT8    Flags;\r
  UINT8    Reserved[10];\r
} EFI_ACPI_DMAR_HEADER;\r
\r
#pragma pack()\r
\r
#endif\r
Commit	Line	Data
846ea5f5 GM	1	/** @file\r
	2	DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)\r
	3	Virtualization Technology for Directed I/O (VT-D) Architecture Specification.\r
	4	\r
5c3cdebf	5	Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
9344f092	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
846ea5f5 GM	7	\r
	8	@par Revision Reference:\r
	9	- Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture\r
5c3cdebf SW	10	Specification v3.2, Dated October 2020.\r
5c3cdebf SW	11	https://software.intel.com/content/dam/develop/external/us/en/documents/vt-directed-io-spec.pdf\r
846ea5f5 GM	12	\r
	13	@par Glossary:\r
	14	- HPET - High Precision Event Timer\r
	15	- NUMA - Non-uniform Memory Access\r
	16	**/\r
2f88bd3a	17	\r
846ea5f5 GM	18	#ifndef _DMA_REMAPPING_REPORTING_TABLE_H_\r
	19	#define _DMA_REMAPPING_REPORTING_TABLE_H_\r
	20	\r
83a45784 JY	21	#include <IndustryStandard/Acpi.h>\r
83a45784 JY	22	\r
846ea5f5 GM	23	#pragma pack(1)\r
	24	\r
	25	///\r
	26	/// DMA-Remapping Reporting Structure definitions from section 8.1\r
	27	///@{\r
2f88bd3a	28	#define EFI_ACPI_DMAR_REVISION 0x01\r
846ea5f5	29	\r
8ab0bd23 HW	30	#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0\r
	31	#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1\r
	32	#define EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG BIT2\r
846ea5f5 GM	33	///@}\r
	34	\r
	35	///\r
	36	/// Remapping Structure Types definitions from section 8.2\r
	37	///@{\r
2f88bd3a MK	38	#define EFI_ACPI_DMAR_TYPE_DRHD 0x00\r
	39	#define EFI_ACPI_DMAR_TYPE_RMRR 0x01\r
	40	#define EFI_ACPI_DMAR_TYPE_ATSR 0x02\r
	41	#define EFI_ACPI_DMAR_TYPE_RHSA 0x03\r
	42	#define EFI_ACPI_DMAR_TYPE_ANDD 0x04\r
	43	#define EFI_ACPI_DMAR_TYPE_SATC 0x05\r
846ea5f5 GM	44	///@}\r
	45	\r
	46	///\r
	47	/// DMA-Remapping Hardware Unit definitions from section 8.3\r
	48	///\r
	49	#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL BIT0\r
	50	\r
	51	///\r
	52	/// DMA-Remapping Device Scope Entry Structure definitions from section 8.3.1\r
	53	///@{\r
	54	#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT 0x01\r
	55	#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE 0x02\r
	56	#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03\r
	57	#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04\r
	58	#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE 0x05\r
	59	///@}\r
	60	\r
	61	///\r
	62	/// Root Port ATS Capability Reporting Structure definitions from section 8.5\r
	63	///\r
2f88bd3a	64	#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0\r
846ea5f5 GM	65	\r
	66	///\r
	67	/// Definition for DMA Remapping Structure Header\r
	68	///\r
	69	typedef struct {\r
2f88bd3a MK	70	UINT16 Type;\r
2f88bd3a MK	71	UINT16 Length;\r
846ea5f5 GM	72	} EFI_ACPI_DMAR_STRUCTURE_HEADER;\r
	73	\r
	74	///\r
	75	/// Definition for DMA-Remapping PCI Path\r
	76	///\r
	77	typedef struct {\r
2f88bd3a MK	78	UINT8 Device;\r
2f88bd3a MK	79	UINT8 Function;\r
846ea5f5 GM	80	} EFI_ACPI_DMAR_PCI_PATH;\r
	81	\r
	82	///\r
	83	/// Device Scope Structure is defined in section 8.3.1\r
	84	///\r
	85	typedef struct {\r
2f88bd3a MK	86	UINT8 Type;\r
	87	UINT8 Length;\r
	88	UINT16 Reserved2;\r
	89	UINT8 EnumerationId;\r
	90	UINT8 StartBusNumber;\r
846ea5f5 GM	91	} EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER;\r
	92	\r
	93	/**\r
	94	DMA-remapping hardware unit definition (DRHD) structure is defined in\r
	95	section 8.3. This uniquely represents a remapping hardware unit present\r
	96	in the platform. There must be at least one instance of this structure\r
	97	for each PCI segment in the platform.\r
	98	**/\r
	99	typedef struct {\r
2f88bd3a MK	100	EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
2f88bd3a MK	101	\r
846ea5f5 GM	102	/**\r
	103	- Bit[0]: INCLUDE_PCI_ALL\r
	104	- If Set, this remapping hardware unit has under its scope all\r
	105	PCI compatible devices in the specified Segment, except devices\r
	106	reported under the scope of other remapping hardware units for\r
	107	the same Segment.\r
	108	- If Clear, this remapping hardware unit has under its scope only\r
	109	devices in the specified Segment that are explicitly identified\r
	110	through the DeviceScope field.\r
	111	- Bits[7:1] Reserved.\r
	112	**/\r
2f88bd3a MK	113	UINT8 Flags;\r
2f88bd3a MK	114	UINT8 Reserved;\r
846ea5f5 GM	115	///\r
	116	/// The PCI Segment associated with this unit.\r
	117	///\r
2f88bd3a	118	UINT16 SegmentNumber;\r
846ea5f5 GM	119	///\r
	120	/// Base address of remapping hardware register-set for this unit.\r
	121	///\r
2f88bd3a	122	UINT64 RegisterBaseAddress;\r
846ea5f5 GM	123	} EFI_ACPI_DMAR_DRHD_HEADER;\r
	124	\r
	125	/**\r
	126	Reserved Memory Region Reporting Structure (RMRR) is described in section 8.4\r
	127	Reserved memory ranges that may be DMA targets may be reported through the\r
	128	RMRR structures, along with the devices that requires access to the specified\r
	129	reserved memory region.\r
	130	**/\r
	131	typedef struct {\r
2f88bd3a MK	132	EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
2f88bd3a MK	133	UINT8 Reserved[2];\r
846ea5f5 GM	134	///\r
	135	/// PCI Segment Number associated with devices identified through\r
	136	/// the Device Scope field.\r
	137	///\r
2f88bd3a	138	UINT16 SegmentNumber;\r
846ea5f5 GM	139	///\r
	140	/// Base address of 4KB-aligned reserved memory region\r
	141	///\r
2f88bd3a MK	142	UINT64 ReservedMemoryRegionBaseAddress;\r
2f88bd3a MK	143	\r
846ea5f5 GM	144	/**\r
	145	Last address of the reserved memory region. Value in this field must be\r
	146	greater than the value in Reserved Memory Region Base Address field.\r
	147	The reserved memory region size (Limit - Base + 1) must be an integer\r
	148	multiple of 4KB.\r
	149	**/\r
2f88bd3a	150	UINT64 ReservedMemoryRegionLimitAddress;\r
846ea5f5 GM	151	} EFI_ACPI_DMAR_RMRR_HEADER;\r
	152	\r
	153	/**\r
	154	Root Port ATS Capability Reporting (ATSR) structure is defined in section 8.5.\r
	155	This structure is applicable only for platforms supporting Device-TLBs as\r
	156	reported through the Extended Capability Register. For each PCI Segment in\r
	157	the platform that supports Device-TLBs, BIOS provides an ATSR structure. The\r
	158	ATSR structures identifies PCI-Express Root-Ports supporting Address\r
	159	Translation Services (ATS) transactions. Software must enable ATS on endpoint\r
	160	devices behind a Root Port only if the Root Port is reported as supporting\r
	161	ATS transactions.\r
	162	**/\r
	163	typedef struct {\r
2f88bd3a MK	164	EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
2f88bd3a MK	165	\r
846ea5f5 GM	166	/**\r
	167	- Bit[0]: ALL_PORTS:\r
	168	- If Set, indicates all PCI Express Root Ports in the specified\r
	169	PCI Segment supports ATS transactions.\r
	170	- If Clear, indicates ATS transactions are supported only on\r
	171	Root Ports identified through the Device Scope field.\r
	172	- Bits[7:1] Reserved.\r
	173	**/\r
2f88bd3a MK	174	UINT8 Flags;\r
2f88bd3a MK	175	UINT8 Reserved;\r
846ea5f5 GM	176	///\r
	177	/// The PCI Segment associated with this ATSR structure\r
	178	///\r
2f88bd3a	179	UINT16 SegmentNumber;\r
846ea5f5 GM	180	} EFI_ACPI_DMAR_ATSR_HEADER;\r
	181	\r
	182	/**\r
	183	Remapping Hardware Static Affinity (RHSA) is an optional structure defined\r
	184	in section 8.6. This is intended to be used only on NUMA platforms with\r
	185	Remapping hardware units and memory spanned across multiple nodes.\r
	186	When used, there must be a RHSA structure for each Remapping hardware unit\r
	187	reported through DRHD structure.\r
	188	**/\r
	189	typedef struct {\r
2f88bd3a MK	190	EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
2f88bd3a MK	191	UINT8 Reserved[4];\r
846ea5f5 GM	192	///\r
	193	/// Register Base Address of this Remap hardware unit reported in the\r
	194	/// corresponding DRHD structure.\r
	195	///\r
2f88bd3a	196	UINT64 RegisterBaseAddress;\r
846ea5f5 GM	197	///\r
	198	/// Proximity Domain to which the Remap hardware unit identified by the\r
	199	/// Register Base Address field belongs.\r
	200	///\r
2f88bd3a	201	UINT32 ProximityDomain;\r
846ea5f5 GM	202	} EFI_ACPI_DMAR_RHSA_HEADER;\r
	203	\r
	204	/**\r
	205	An ACPI Name-space Device Declaration (ANDD) structure is defined in section\r
	206	8.7 and uniquely represents an ACPI name-space enumerated device capable of\r
	207	issuing DMA requests in the platform. ANDD structures are used in conjunction\r
	208	with Device-Scope entries of type ACPI_NAMESPACE_DEVICE.\r
	209	**/\r
	210	typedef struct {\r
2f88bd3a MK	211	EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
	212	UINT8 Reserved[3];\r
	213	\r
846ea5f5 GM	214	/**\r
	215	Each ACPI device enumerated through an ANDD structure must have a unique\r
	216	value for this field. To report an ACPI device with ACPI Device Number\r
	217	value of X, under the scope of a DRHD unit, a Device-Scope entry of type\r
	218	ACPI_NAMESPACE_DEVICE is used with value of X in the Enumeration ID field.\r
	219	The Start Bus Number and Path fields in the Device-Scope together\r
	220	provides the 16-bit source-id allocated by platform for the ACPI device.\r
	221	**/\r
2f88bd3a	222	UINT8 AcpiDeviceNumber;\r
846ea5f5 GM	223	} EFI_ACPI_DMAR_ANDD_HEADER;\r
846ea5f5 GM	224	\r
5c3cdebf SW	225	/**\r
	226	An SoC Integrated Address Translation Cache (SATC) reporting structure is\r
	227	defined in section 8.8.\r
	228	**/\r
	229	typedef struct {\r
2f88bd3a MK	230	EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
2f88bd3a MK	231	\r
5c3cdebf SW	232	/**\r
	233	- Bit[0]: ATC_REQUIRED:\r
	234	- If Set, indicates that every SoC integrated device enumerated\r
	235	in this table has a functional requirement to enable its ATC\r
	236	(via the ATS capability) for device operation.\r
	237	- If Clear, any device enumerated in this table can operate when\r
	238	its respective ATC is not enabled (albeit with reduced\r
	239	performance or functionality).\r
	240	- Bits[7:1] Reserved.\r
	241	**/\r
2f88bd3a MK	242	UINT8 Flags;\r
2f88bd3a MK	243	UINT8 Reserved;\r
5c3cdebf SW	244	///\r
	245	/// The PCI Segment associated with this SATC structure. All SoC integrated\r
	246	/// devices within a PCI segment with same value for Flags field must be\r
	247	/// enumerated in the same SATC structure.\r
	248	///\r
2f88bd3a	249	UINT16 SegmentNumber;\r
5c3cdebf SW	250	} EFI_ACPI_DMAR_SATC_HEADER;\r
5c3cdebf SW	251	\r
846ea5f5 GM	252	/**\r
	253	DMA Remapping Reporting Structure Header as defined in section 8.1\r
	254	This header will be followed by list of Remapping Structures listed below\r
	255	- DMA Remapping Hardware Unit Definition (DRHD)\r
	256	- Reserved Memory Region Reporting (RMRR)\r
	257	- Root Port ATS Capability Reporting (ATSR)\r
	258	- Remapping Hardware Static Affinity (RHSA)\r
	259	- ACPI Name-space Device Declaration (ANDD)\r
5c3cdebf	260	- SoC Integrated Address Translation Cache reporting (SATC)\r
846ea5f5 GM	261	These structure types must by reported in numerical order.\r
	262	i.e., All remapping structures of type 0 (DRHD) enumerated before remapping\r
	263	structures of type 1 (RMRR), and so forth.\r
	264	**/\r
	265	typedef struct {\r
2f88bd3a MK	266	EFI_ACPI_DESCRIPTION_HEADER Header;\r
2f88bd3a MK	267	\r
846ea5f5 GM	268	/**\r
	269	This field indicates the maximum DMA physical addressability supported by\r
	270	this platform. The system address map reported by the BIOS indicates what\r
	271	portions of this addresses are populated. The Host Address Width (HAW) of\r
	272	the platform is computed as (N+1), where N is the value reported in this\r
	273	field.\r
	274	For example, for a platform supporting 40 bits of physical addressability,\r
	275	the value of 100111b is reported in this field.\r
	276	**/\r
2f88bd3a MK	277	UINT8 HostAddressWidth;\r
2f88bd3a MK	278	\r
846ea5f5 GM	279	/**\r
	280	- Bit[0]: INTR_REMAP - If Clear, the platform does not support interrupt\r
	281	remapping. If Set, the platform supports interrupt remapping.\r
	282	- Bit[1]: X2APIC_OPT_OUT - For firmware compatibility reasons, platform\r
	283	firmware may Set this field to request system software to opt\r
	284	out of enabling Extended xAPIC (X2APIC) mode. This field is\r
	285	valid only when the INTR_REMAP field (bit 0) is Set.\r
8ab0bd23 HW	286	- Bit[2]: DMA_CTRL_PLATFORM_OPT_IN_FLAG - Platform firmware is\r
	287	recommended to Set this field to report any platform initiated\r
	288	DMA is restricted to only reserved memory regions (reported in\r
	289	RMRR structures) when transferring control to system software\r
	290	such as on ExitBootServices().\r
	291	- Bits[7:3] Reserved.\r
846ea5f5	292	**/\r
2f88bd3a MK	293	UINT8 Flags;\r
2f88bd3a MK	294	UINT8 Reserved[10];\r
846ea5f5 GM	295	} EFI_ACPI_DMAR_HEADER;\r
	296	\r
	297	#pragma pack()\r
	298	\r
	299	#endif\r