[mirror_edk2.git] / MdePkg / Include / IndustryStandard / IoRemappingTable.h

/** @file\r
  ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049C\r
\r
  http://infocenter.arm.com/help/topic/com.arm.doc.den0049c/DEN0049C_IO_Remapping_Table.pdf\r
\r
  Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
**/\r
\r
#ifndef __IO_REMAPPING_TABLE_H__\r
#define __IO_REMAPPING_TABLE_H__\r
\r
#include <IndustryStandard/Acpi.h>\r
\r
#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION        0x0\r
\r
#define EFI_ACPI_IORT_TYPE_ITS_GROUP                0x0\r
#define EFI_ACPI_IORT_TYPE_NAMED_COMP               0x1\r
#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX             0x2\r
#define EFI_ACPI_IORT_TYPE_SMMUv1v2                 0x3\r
#define EFI_ACPI_IORT_TYPE_SMMUv3                   0x4\r
#define EFI_ACPI_IORT_TYPE_PMCG                     0x5\r
\r
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA           BIT0\r
\r
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR         BIT0\r
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA         BIT1\r
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA         BIT2\r
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO        BIT3\r
\r
#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM          BIT0\r
#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS         BIT1\r
\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1             0x0\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2             0x1\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400         0x2\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500         0x3\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401         0x4\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2  0x5\r
\r
#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM             BIT0\r
#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK        BIT1\r
\r
#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL       0x0\r
#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE        0x1\r
\r
#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE    BIT0\r
#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE     BIT1\r
\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED  0x0\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED    0x1\r
\r
#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE       BIT0\r
\r
#pragma pack(1)\r
\r
///\r
/// Table header\r
///\r
typedef struct {\r
  EFI_ACPI_DESCRIPTION_HEADER             Header;\r
  UINT32                                  NumNodes;\r
  UINT32                                  NodeOffset;\r
  UINT32                                  Reserved;\r
} EFI_ACPI_6_0_IO_REMAPPING_TABLE;\r
\r
///\r
/// Definition for ID mapping table shared by all node types\r
///\r
typedef struct {\r
  UINT32                                  InputBase;\r
  UINT32                                  NumIds;\r
  UINT32                                  OutputBase;\r
  UINT32                                  OutputReference;\r
  UINT32                                  Flags;\r
} EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;\r
\r
///\r
/// Node header definition shared by all node types\r
///\r
typedef struct {\r
  UINT8                                   Type;\r
  UINT16                                  Length;\r
  UINT8                                   Revision;\r
  UINT32                                  Reserved;\r
  UINT32                                  NumIdMappings;\r
  UINT32                                  IdReference;\r
} EFI_ACPI_6_0_IO_REMAPPING_NODE;\r
\r
///\r
/// Node type 0: ITS node\r
///\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;\r
\r
  UINT32                                  NumItsIdentifiers;\r
//UINT32                                  ItsIdentifiers[NumItsIdentifiers];\r
} EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;\r
\r
///\r
/// Node type 1: root complex node\r
///\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;\r
\r
  UINT32                                  CacheCoherent;\r
  UINT8                                   AllocationHints;\r
  UINT16                                  Reserved;\r
  UINT8                                   MemoryAccessFlags;\r
\r
  UINT32                                  AtsAttribute;\r
  UINT32                                  PciSegmentNumber;\r
} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;\r
\r
///\r
/// Node type 2: named component node\r
///\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;\r
\r
  UINT32                                  Flags;\r
  UINT32                                  CacheCoherent;\r
  UINT8                                   AllocationHints;\r
  UINT16                                  Reserved;\r
  UINT8                                   MemoryAccessFlags;\r
  UINT8                                   AddressSizeLimit;\r
//UINT8                                   ObjectName[];\r
} EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;\r
\r
///\r
/// Node type 3: SMMUv1 or SMMUv2 node\r
///\r
typedef struct {\r
  UINT32                                  Interrupt;\r
  UINT32                                  InterruptFlags;\r
} EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;\r
\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;\r
\r
  UINT64                                  Base;\r
  UINT64                                  Span;\r
  UINT32                                  Model;\r
  UINT32                                  Flags;\r
  UINT32                                  GlobalInterruptArrayRef;\r
  UINT32                                  NumContextInterrupts;\r
  UINT32                                  ContextInterruptArrayRef;\r
  UINT32                                  NumPmuInterrupts;\r
  UINT32                                  PmuInterruptArrayRef;\r
\r
  UINT32                                  SMMU_NSgIrpt;\r
  UINT32                                  SMMU_NSgIrptFlags;\r
  UINT32                                  SMMU_NSgCfgIrpt;\r
  UINT32                                  SMMU_NSgCfgIrptFlags;\r
\r
//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT  ContextInterrupt[NumContextInterrupts];\r
//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT  PmuInterrupt[NumPmuInterrupts];\r
} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;\r
\r
///\r
/// Node type 4: SMMUv4 node\r
///\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;\r
\r
  UINT64                                  Base;\r
  UINT32                                  Flags;\r
  UINT32                                  Reserved;\r
  UINT64                                  VatosAddress;\r
  UINT32                                  Model;\r
  UINT32                                  Event;\r
  UINT32                                  Pri;\r
  UINT32                                  Gerr;\r
  UINT32                                  Sync;\r
} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;\r
\r
///\r
/// Node type 5: PMCG node\r
///\r
typedef struct {\r
  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;\r
\r
  UINT64                                  Base;\r
  UINT32                                  OverflowInterruptGsiv;\r
  UINT32                                  NodeReference;\r
//EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE      OverflowInterruptMsiMapping[1];\r
} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;\r
\r
#pragma pack()\r
\r
#endif\r
Commit	Line	Data
75ce7ef7	1	/** @file\r
157fb7bf	2	ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049C\r
75ce7ef7	3	\r
157fb7bf	4	http://infocenter.arm.com/help/topic/com.arm.doc.den0049c/DEN0049C_IO_Remapping_Table.pdf\r
75ce7ef7 AB	5	\r
	6	Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>\r
	7	\r
	8	This program and the accompanying materials\r
	9	are licensed and made available under the terms and conditions of the BSD License\r
	10	which accompanies this distribution. The full text of the license may be found at\r
	11	http://opensource.org/licenses/bsd-license.php\r
	12	\r
	13	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	14	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	15	**/\r
	16	\r
	17	#ifndef __IO_REMAPPING_TABLE_H__\r
	18	#define __IO_REMAPPING_TABLE_H__\r
	19	\r
	20	#include <IndustryStandard/Acpi.h>\r
	21	\r
	22	#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION 0x0\r
	23	\r
	24	#define EFI_ACPI_IORT_TYPE_ITS_GROUP 0x0\r
	25	#define EFI_ACPI_IORT_TYPE_NAMED_COMP 0x1\r
	26	#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2\r
	27	#define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3\r
	28	#define EFI_ACPI_IORT_TYPE_SMMUv3 0x4\r
157fb7bf	29	#define EFI_ACPI_IORT_TYPE_PMCG 0x5\r
75ce7ef7 AB	30	\r
	31	#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0\r
	32	\r
	33	#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR BIT0\r
	34	#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA BIT1\r
	35	#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2\r
	36	#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3\r
	37	\r
	38	#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0\r
	39	#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1\r
	40	\r
	41	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0\r
	42	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1\r
	43	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400 0x2\r
	44	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500 0x3\r
157fb7bf AB	45	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4\r
157fb7bf AB	46	#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2 0x5\r
75ce7ef7 AB	47	\r
	48	#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0\r
	49	#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1\r
	50	\r
	51	#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL 0x0\r
	52	#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1\r
	53	\r
	54	#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0\r
	55	#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1\r
	56	\r
	57	#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED 0x0\r
	58	#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED 0x1\r
	59	\r
	60	#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE BIT0\r
	61	\r
	62	#pragma pack(1)\r
	63	\r
	64	///\r
	65	/// Table header\r
	66	///\r
	67	typedef struct {\r
	68	EFI_ACPI_DESCRIPTION_HEADER Header;\r
	69	UINT32 NumNodes;\r
	70	UINT32 NodeOffset;\r
	71	UINT32 Reserved;\r
	72	} EFI_ACPI_6_0_IO_REMAPPING_TABLE;\r
	73	\r
	74	///\r
	75	/// Definition for ID mapping table shared by all node types\r
	76	///\r
	77	typedef struct {\r
	78	UINT32 InputBase;\r
	79	UINT32 NumIds;\r
	80	UINT32 OutputBase;\r
	81	UINT32 OutputReference;\r
	82	UINT32 Flags;\r
	83	} EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;\r
	84	\r
	85	///\r
	86	/// Node header definition shared by all node types\r
	87	///\r
	88	typedef struct {\r
	89	UINT8 Type;\r
	90	UINT16 Length;\r
	91	UINT8 Revision;\r
	92	UINT32 Reserved;\r
	93	UINT32 NumIdMappings;\r
	94	UINT32 IdReference;\r
	95	} EFI_ACPI_6_0_IO_REMAPPING_NODE;\r
	96	\r
	97	///\r
	98	/// Node type 0: ITS node\r
	99	///\r
	100	typedef struct {\r
	101	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
	102	\r
	103	UINT32 NumItsIdentifiers;\r
	104	//UINT32 ItsIdentifiers[NumItsIdentifiers];\r
	105	} EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;\r
	106	\r
	107	///\r
	108	/// Node type 1: root complex node\r
	109	///\r
	110	typedef struct {\r
111	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
112	\r
113	UINT32 CacheCoherent;\r
114	UINT8 AllocationHints;\r
115	UINT16 Reserved;\r
116	UINT8 MemoryAccessFlags;\r
117	\r
118	UINT32 AtsAttribute;\r
119	UINT32 PciSegmentNumber;\r
120	} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;\r
121	\r
122	///\r
123	/// Node type 2: named component node\r
124	///\r
125	typedef struct {\r
126	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
127	\r
128	UINT32 Flags;\r
129	UINT32 CacheCoherent;\r
130	UINT8 AllocationHints;\r
131	UINT16 Reserved;\r
132	UINT8 MemoryAccessFlags;\r
133	UINT8 AddressSizeLimit;\r
134	//UINT8 ObjectName[];\r
135	} EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;\r
136	\r
137	///\r
138	/// Node type 3: SMMUv1 or SMMUv2 node\r
139	///\r
140	typedef struct {\r
141	UINT32 Interrupt;\r
142	UINT32 InterruptFlags;\r
143	} EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;\r
144	\r
145	typedef struct {\r
146	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
147	\r
148	UINT64 Base;\r
149	UINT64 Span;\r
150	UINT32 Model;\r
151	UINT32 Flags;\r
152	UINT32 GlobalInterruptArrayRef;\r
153	UINT32 NumContextInterrupts;\r
154	UINT32 ContextInterruptArrayRef;\r
155	UINT32 NumPmuInterrupts;\r
156	UINT32 PmuInterruptArrayRef;\r
157	\r
158	UINT32 SMMU_NSgIrpt;\r
159	UINT32 SMMU_NSgIrptFlags;\r
160	UINT32 SMMU_NSgCfgIrpt;\r
161	UINT32 SMMU_NSgCfgIrptFlags;\r
162	\r
163	//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT ContextInterrupt[NumContextInterrupts];\r
164	//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT PmuInterrupt[NumPmuInterrupts];\r
165	} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;\r
166	\r
167	///\r
168	/// Node type 4: SMMUv4 node\r
169	///\r
170	typedef struct {\r
171	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
172	\r
173	UINT64 Base;\r
174	UINT32 Flags;\r
175	UINT32 Reserved;\r
176	UINT64 VatosAddress;\r
177	UINT32 Model;\r
178	UINT32 Event;\r
179	UINT32 Pri;\r
180	UINT32 Gerr;\r
181	UINT32 Sync;\r
182	} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;\r
183	\r
157fb7bf AB	184	///\r
	185	/// Node type 5: PMCG node\r
	186	///\r
	187	typedef struct {\r
	188	EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
	189	\r
	190	UINT64 Base;\r
	191	UINT32 OverflowInterruptGsiv;\r
	192	UINT32 NodeReference;\r
	193	//EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1];\r
	194	} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;\r
	195	\r
75ce7ef7 AB	196	#pragma pack()\r
	197	\r
	198	#endif\r