projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| a7b64584 | 1 | /** @file\r |
| 5d51e463 | 2 | Main PAL API's defined in Intel Itanium Architecture Software Developer's Manual.\r |
| a7b64584 | 3 | \r |
| e2a5ae07 | 4 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r |
| 9df063a0 | 5 | This program and the accompanying materials \r |
| a7b64584 | 6 | are licensed and made available under the terms and conditions of the BSD License \r |
| 7 | which accompanies this distribution. The full text of the license may be found at \r | |
| 8 | http://opensource.org/licenses/bsd-license.php \r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #ifndef __PAL_API_H__\r | |
| 16 | #define __PAL_API_H__\r | |
| 17 | \r | |
| 18 | #define PAL_SUCCESS 0x0\r | |
| 19 | \r | |
| 7e6a7a63 | 20 | ///\r |
| 21 | /// CacheType of PAL_CACHE_FLUSH.\r | |
| 22 | ///\r | |
| a7b64584 | 23 | #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r |
| 24 | #define PAL_CACHE_FLUSH_DATA_ALL 2\r | |
| 25 | #define PAL_CACHE_FLUSH_ALL 3\r | |
| 26 | #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r | |
| 27 | \r | |
| 28 | \r | |
| 7e6a7a63 | 29 | ///\r |
| 30 | /// Bitmask of Opearation of PAL_CACHE_FLUSH.\r | |
| 31 | ///\r | |
| a7b64584 | 32 | #define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0\r |
| 33 | #define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0\r | |
| 34 | #define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1\r | |
| 35 | #define PAL_CACHE_FLUSH_NO_INTERRUPT 0\r | |
| 36 | \r | |
| 37 | /**\r | |
| 38 | PAL Procedure - PAL_CACHE_FLUSH.\r | |
| 39 | \r | |
| 1a2f870c | 40 | Flush the instruction or data caches. It is required by Itanium processors.\r |
| a7b64584 | 41 | The PAL procedure supports the Static Registers calling\r |
| 42 | convention. It could be called at virtual mode and physical\r | |
| 43 | mode.\r | |
| 44 | \r | |
| 45 | @param Index Index of PAL_CACHE_FLUSH within the\r | |
| 46 | list of PAL procedures.\r | |
| 47 | @param CacheType Unsigned 64-bit integer indicating\r | |
| 48 | which cache to flush.\r | |
| 49 | @param Operation Formatted bit vector indicating the\r | |
| 50 | operation of this call.\r | |
| 51 | @param ProgressIndicator Unsigned 64-bit integer specifying\r | |
| 52 | the starting position of the flush\r | |
| 53 | operation.\r | |
| 54 | \r | |
| 55 | @retval 2 Call completed without error, but a PMI\r | |
| 56 | was taken during the execution of this\r | |
| 57 | procedure.\r | |
| 58 | @retval 1 Call has not completed flushing due to\r | |
| 59 | a pending interrupt.\r | |
| 60 | @retval 0 Call completed without error\r | |
| 61 | @retval -2 Invalid argument\r | |
| 62 | @retval -3 Call completed with error\r | |
| 63 | \r | |
| 64 | @return R9 Unsigned 64-bit integer specifying the vector\r | |
| 65 | number of the pending interrupt.\r | |
| 66 | @return R10 Unsigned 64-bit integer specifying the\r | |
| 67 | starting position of the flush operation.\r | |
| 68 | @return R11 Unsigned 64-bit integer specifying the vector\r | |
| 69 | number of the pending interrupt.\r | |
| 70 | \r | |
| 71 | **/\r | |
| 72 | #define PAL_CACHE_FLUSH 1\r | |
| 73 | \r | |
| 74 | \r | |
| 7e6a7a63 | 75 | ///\r |
| 76 | /// Attributes of PAL_CACHE_CONFIG_INFO1\r | |
| 77 | ///\r | |
| a7b64584 | 78 | #define PAL_CACHE_ATTR_WT 0\r |
| 79 | #define PAL_CACHE_ATTR_WB 1\r | |
| 80 | \r | |
| 7e6a7a63 | 81 | ///\r |
| 82 | /// PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
| 83 | ///\r | |
| a7b64584 | 84 | #define PAL_CACHE_STORE_TEMPORAL 0\r |
| 85 | #define PAL_CACHE_STORE_NONE_TEMPORAL 3\r | |
| 86 | \r | |
| 7e6a7a63 | 87 | ///\r |
| 88 | /// PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
| 89 | ///\r | |
| a7b64584 | 90 | #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r |
| 91 | #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r | |
| 92 | \r | |
| 7e6a7a63 | 93 | ///\r |
| 94 | /// PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
| 95 | ///\r | |
| a7b64584 | 96 | #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r |
| 97 | #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r | |
| 98 | #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r | |
| 99 | \r | |
| 7e6a7a63 | 100 | ///\r |
| 101 | /// Detail the characteristics of a given processor controlled\r | |
| 102 | /// cache in the cache hierarchy.\r | |
| 103 | ///\r | |
| a7b64584 | 104 | typedef struct {\r |
| 105 | UINT64 IsUnified : 1;\r | |
| 106 | UINT64 Attributes : 2;\r | |
| 107 | UINT64 Associativity:8;\r | |
| 108 | UINT64 LineSize:8;\r | |
| 109 | UINT64 Stride:8;\r | |
| 110 | UINT64 StoreLatency:8;\r | |
| 111 | UINT64 StoreHint:8;\r | |
| 112 | UINT64 LoadHint:8;\r | |
| 113 | } PAL_CACHE_INFO_RETURN1;\r | |
| 114 | \r | |
| 7e6a7a63 | 115 | ///\r |
| 116 | /// Detail the characteristics of a given processor controlled\r | |
| 117 | /// cache in the cache hierarchy.\r | |
| 118 | ///\r | |
| a7b64584 | 119 | typedef struct {\r |
| 120 | UINT64 CacheSize:32;\r | |
| 121 | UINT64 AliasBoundary:8;\r | |
| 122 | UINT64 TagLsBits:8;\r | |
| 123 | UINT64 TagMsBits:8;\r | |
| 124 | } PAL_CACHE_INFO_RETURN2;\r | |
| 125 | \r | |
| 126 | /**\r | |
| 127 | PAL Procedure - PAL_CACHE_INFO.\r | |
| 128 | \r | |
| 129 | Return detailed instruction or data cache information. It is\r | |
| 1a2f870c | 130 | required by Itanium processors. The PAL procedure supports the Static\r |
| a7b64584 | 131 | Registers calling convention. It could be called at virtual\r |
| 132 | mode and physical mode.\r | |
| 133 | \r | |
| 134 | @param Index Index of PAL_CACHE_INFO within the list of\r | |
| 135 | PAL procedures.\r | |
| 136 | @param CacheLevel Unsigned 64-bit integer specifying the\r | |
| 137 | level in the cache hierarchy for which\r | |
| 138 | information is requested. This value must\r | |
| 139 | be between 0 and one less than the value\r | |
| 140 | returned in the cache_levels return value\r | |
| 141 | from PAL_CACHE_SUMMARY.\r | |
| 142 | @param CacheType Unsigned 64-bit integer with a value of 1\r | |
| 143 | for instruction cache and 2 for data or\r | |
| 144 | unified cache. All other values are\r | |
| 145 | reserved.\r | |
| 146 | @param Reserved Should be 0.\r | |
| 147 | \r | |
| 148 | @retval 0 Call completed without error\r | |
| 149 | @retval -2 Invalid argument\r | |
| 150 | @retval -3 Call completed with error\r | |
| 151 | \r | |
| 152 | @return R9 Detail the characteristics of a given\r | |
| 153 | processor controlled cache in the cache\r | |
| 154 | hierarchy. See PAL_CACHE_INFO_RETURN1.\r | |
| 155 | @return R10 Detail the characteristics of a given\r | |
| 156 | processor controlled cache in the cache\r | |
| 157 | hierarchy. See PAL_CACHE_INFO_RETURN2.\r | |
| 158 | @return R11 Reserved with 0.\r | |
| 159 | \r | |
| 160 | **/\r | |
| 161 | #define PAL_CACHE_INFO 2\r | |
| 162 | \r | |
| 163 | \r | |
| 164 | \r | |
| 7e6a7a63 | 165 | ///\r |
| 166 | /// Level of PAL_CACHE_INIT.\r | |
| 167 | ///\r | |
| a7b64584 | 168 | #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r |
| 169 | \r | |
| 7e6a7a63 | 170 | ///\r |
| 171 | /// CacheType\r | |
| 172 | ///\r | |
| a7b64584 | 173 | #define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1\r |
| 174 | #define PAL_CACHE_INIT_TYPE_DATA 0x2\r | |
| 175 | #define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3\r | |
| 176 | \r | |
| 7e6a7a63 | 177 | ///\r |
| 178 | /// Restrict of PAL_CACHE_INIT.\r | |
| 179 | ///\r | |
| a7b64584 | 180 | #define PAL_CACHE_INIT_NO_RESTRICT 0\r |
| 181 | #define PAL_CACHE_INIT_RESTRICTED 1\r | |
| 182 | \r | |
| 183 | /**\r | |
| 184 | PAL Procedure - PAL_CACHE_INIT.\r | |
| 185 | \r | |
| 186 | Initialize the instruction or data caches. It is required by\r | |
| 1a2f870c | 187 | Itanium processors. The PAL procedure supports the Static Registers calling\r |
| a7b64584 | 188 | convention. It could be called at physical mode.\r |
| 189 | \r | |
| 190 | @param Index Index of PAL_CACHE_INIT within the list of PAL\r | |
| 191 | procedures.\r | |
| 192 | @param Level Unsigned 64-bit integer containing the level of\r | |
| 193 | cache to initialize. If the cache level can be\r | |
| 194 | initialized independently, only that level will\r | |
| 195 | be initialized. Otherwise\r | |
| 196 | implementation-dependent side-effects will\r | |
| 197 | occur.\r | |
| 198 | @param CacheType Unsigned 64-bit integer with a value of 1 to\r | |
| 199 | initialize the instruction cache, 2 to\r | |
| 200 | initialize the data cache, or 3 to\r | |
| 201 | initialize both. All other values are\r | |
| 202 | reserved.\r | |
| 203 | @param Restrict Unsigned 64-bit integer with a value of 0 or\r | |
| 204 | 1. All other values are reserved. If\r | |
| 205 | restrict is 1 and initializing the specified\r | |
| 206 | level and cache_type of the cache would\r | |
| 207 | cause side-effects, PAL_CACHE_INIT will\r | |
| 208 | return -4 instead of initializing the cache.\r | |
| 209 | \r | |
| 210 | @retval 0 Call completed without error\r | |
| 211 | @retval -2 Invalid argument\r | |
| 212 | @retval -3 Call completed with error.\r | |
| 213 | @retval -4 Call could not initialize the specified\r | |
| 214 | level and cache_type of the cache without\r | |
| 215 | side-effects and restrict was 1.\r | |
| 216 | \r | |
| 217 | **/\r | |
| 218 | #define PAL_CACHE_INIT 3\r | |
| 219 | \r | |
| 220 | \r | |
| 7e6a7a63 | 221 | ///\r |
| 222 | /// PAL_CACHE_PROTECTION.Method.\r | |
| 223 | ///\r | |
| a7b64584 | 224 | #define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r |
| 225 | #define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r | |
| 226 | #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r | |
| 227 | #define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r | |
| 228 | \r | |
| 229 | \r | |
| 230 | \r | |
| 7e6a7a63 | 231 | ///\r |
| 232 | /// PAL_CACHE_PROTECTION.TagOrData.\r | |
| 233 | ///\r | |
| a7b64584 | 234 | #define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r |
| 235 | #define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r | |
| 236 | #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r | |
| 237 | #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r | |
| 238 | \r | |
| 7e6a7a63 | 239 | ///\r |
| 240 | /// 32-bit protection information structures.\r | |
| 241 | ///\r | |
| a7b64584 | 242 | typedef struct {\r |
| 243 | UINT32 DataBits:8;\r | |
| 244 | UINT32 TagProtLsb:6;\r | |
| 245 | UINT32 TagProtMsb:6;\r | |
| 246 | UINT32 ProtBits:6;\r | |
| 247 | UINT32 Method:4;\r | |
| 248 | UINT32 TagOrData:2;\r | |
| 249 | } PAL_CACHE_PROTECTION;\r | |
| 250 | \r | |
| 251 | /**\r | |
| 252 | PAL Procedure - PAL_CACHE_PROT_INFO.\r | |
| 253 | \r | |
| 254 | Return instruction or data cache protection information. It is\r | |
| 1a2f870c | 255 | required by Itanium processors. The PAL procedure supports the Static\r |
| a7b64584 | 256 | Registers calling convention. It could be called at physical\r |
| 257 | mode and Virtual mode.\r | |
| 258 | \r | |
| 259 | @param Index Index of PAL_CACHE_PROT_INFO within the list of\r | |
| 260 | PAL procedures.\r | |
| 261 | @param CacheLevel Unsigned 64-bit integer specifying the level\r | |
| 262 | in the cache hierarchy for which information\r | |
| 263 | is requested. This value must be between 0\r | |
| 264 | and one less than the value returned in the\r | |
| 265 | cache_levels return value from\r | |
| 266 | PAL_CACHE_SUMMARY.\r | |
| 267 | @param CacheType Unsigned 64-bit integer with a value of 1\r | |
| 268 | for instruction cache and 2 for data or\r | |
| 269 | unified cache. All other values are\r | |
| 270 | reserved.\r | |
| 271 | \r | |
| 272 | @retval 0 Call completed without error\r | |
| 273 | @retval -2 Invalid argument\r | |
| 274 | @retval -3 Call completed with error.\r | |
| 275 | \r | |
| 276 | @return R9 Detail the characteristics of a given\r | |
| 277 | processor controlled cache in the cache\r | |
| 278 | hierarchy. See PAL_CACHE_PROTECTION[0..1].\r | |
| 279 | @return R10 Detail the characteristics of a given\r | |
| 280 | processor controlled cache in the cache\r | |
| 281 | hierarchy. See PAL_CACHE_PROTECTION[2..3].\r | |
| 282 | @return R11 Detail the characteristics of a given\r | |
| 283 | processor controlled cache in the cache\r | |
| 284 | hierarchy. See PAL_CACHE_PROTECTION[4..5].\r | |
| 285 | \r | |
| 286 | **/\r | |
| 287 | #define PAL_CACHE_PROT_INFO 38\r | |
| 288 | \r | |
| a7b64584 | 289 | typedef struct {\r |
| 992f22b9 LG |
290 | UINT64 ThreadId : 16; ///< The thread identifier of the logical\r |
| 291 | ///< processor for which information is being\r | |
| 292 | ///< returned. This value will be unique on a per core basis.\r | |
| a7b64584 | 293 | UINT64 Reserved1: 16;\r |
| 992f22b9 LG |
294 | UINT64 CoreId: 16; ///< The core identifier of the logical processor\r |
| 295 | ///< for which information is being returned.\r | |
| 296 | ///< This value will be unique on a per physical\r | |
| 297 | ///< processor package basis.\r | |
| a7b64584 | 298 | UINT64 Reserved2: 16;\r |
| 299 | } PAL_PCOC_N_CACHE_INFO1;\r | |
| 300 | \r | |
| a7b64584 | 301 | \r |
| a7b64584 | 302 | typedef struct {\r |
| 992f22b9 LG |
303 | UINT64 LogicalAddress : 16; ///< Logical address: geographical address\r |
| 304 | ///< of the logical processor for which\r | |
| 305 | ///< information is being returned. This is\r | |
| 306 | ///< the same value that is returned by the\r | |
| 307 | ///< PAL_FIXED_ADDR procedure when it is\r | |
| 308 | ///< called on the logical processor.\r | |
| a7b64584 | 309 | UINT64 Reserved1: 16;\r |
| 310 | UINT64 Reserved2: 32;\r | |
| 311 | } PAL_PCOC_N_CACHE_INFO2;\r | |
| 312 | \r | |
| 313 | /**\r | |
| 314 | PAL Procedure - PAL_CACHE_SHARED_INFO.\r | |
| 315 | \r | |
| 316 | Returns information on which logical processors share caches.\r | |
| 317 | It is optional. The PAL procedure supports the Static\r | |
| 318 | Registers calling convention. It could be called at physical\r | |
| 319 | mode and Virtual mode.\r | |
| 320 | \r | |
| 321 | @param Index Index of PAL_CACHE_SHARED_INFO within the list\r | |
| 322 | of PAL procedures.\r | |
| 323 | @param CacheLevel Unsigned 64-bit integer specifying the\r | |
| 324 | level in the cache hierarchy for which\r | |
| 325 | information is requested. This value must\r | |
| 326 | be between 0 and one less than the value\r | |
| 327 | returned in the cache_levels return value\r | |
| 328 | from PAL_CACHE_SUMMARY.\r | |
| 329 | @param CacheType Unsigned 64-bit integer with a value of 1\r | |
| 330 | for instruction cache and 2 for data or\r | |
| 331 | unified cache. All other values are\r | |
| 332 | reserved.\r | |
| 333 | @param ProcNumber Unsigned 64-bit integer that specifies for\r | |
| 334 | which logical processor information is\r | |
| 335 | being requested. This input argument must\r | |
| 336 | be zero for the first call to this\r | |
| 337 | procedure and can be a maximum value of\r | |
| 338 | one less than the number of logical\r | |
| 339 | processors sharing this cache, which is\r | |
| 340 | returned by the num_shared return value.\r | |
| 341 | \r | |
| 342 | @retval 0 Call completed without error\r | |
| 343 | @retval -1 Unimplemented procedure\r | |
| 344 | @retval -2 Invalid argument\r | |
| 345 | @retval -3 Call completed with error.\r | |
| 346 | \r | |
| 347 | @return R9 Unsigned integer that returns the number of\r | |
| 348 | logical processors that share the processor\r | |
| 349 | cache level and type, for which information was\r | |
| 350 | requested.\r | |
| 351 | @return R10 The format of PAL_PCOC_N_CACHE_INFO1.\r | |
| 352 | @return R11 The format of PAL_PCOC_N_CACHE_INFO2.\r | |
| 353 | \r | |
| 354 | **/\r | |
| 355 | #define PAL_CACHE_SHARED_INFO 43\r | |
| 356 | \r | |
| 357 | \r | |
| 358 | /**\r | |
| 359 | PAL Procedure - PAL_CACHE_SUMMARY.\r | |
| 360 | \r | |
| 361 | Return a summary of the cache hierarchy. It is required by\r | |
| 1a2f870c | 362 | Itanium processors. The PAL procedure supports the Static Registers calling\r |
| a7b64584 | 363 | convention. It could be called at physical mode and Virtual\r |
| 364 | mode.\r | |
| 365 | \r | |
| 366 | @param Index Index of PAL_CACHE_SUMMARY within the list of\r | |
| 367 | PAL procedures.\r | |
| 368 | \r | |
| 369 | @retval 0 Call completed without error\r | |
| 370 | @retval -2 Invalid argument\r | |
| 371 | @retval -3 Call completed with error.\r | |
| 372 | \r | |
| 373 | @return R9 CacheLevels Unsigned 64-bit integer denoting the\r | |
| 374 | number of levels of cache\r | |
| 375 | implemented by the processor.\r | |
| 376 | Strictly, this is the number of\r | |
| 377 | levels for which the cache\r | |
| 378 | controller is integrated into the\r | |
| 379 | processor (the cache SRAMs may be\r | |
| 380 | external to the processor).\r | |
| 381 | @return R10 UniqueCaches Unsigned 64-bit integer denoting the\r | |
| 382 | number of unique caches implemented\r | |
| 383 | by the processor. This has a maximum\r | |
| 384 | of 2*cache_levels, but may be less\r | |
| 385 | if any of the levels in the cache\r | |
| 386 | hierarchy are unified caches or do\r | |
| 387 | not have both instruction and data\r | |
| 388 | caches.\r | |
| 389 | \r | |
| 390 | **/\r | |
| 391 | #define PAL_CACHE_SUMMARY 4\r | |
| 392 | \r | |
| 393 | \r | |
| 394 | //\r | |
| 395 | // Virtual Memory Attributes implemented by processor.\r | |
| 396 | //\r | |
| 397 | #define PAL_MEMORY_ATTR_WB 0\r | |
| 398 | #define PAL_MEMORY_ATTR_WC 6\r | |
| 399 | #define PAL_MEMORY_ATTR_UC 4\r | |
| 400 | #define PAL_MEMORY_ATTR_UCE 5\r | |
| 401 | #define PAL_MEMORY_ATTR_NATPAGE 7\r | |
| 402 | \r | |
| 403 | /**\r | |
| 404 | PAL Procedure - PAL_MEM_ATTRIB.\r | |
| 405 | \r | |
| 406 | Return a list of supported memory attributes.. It is required\r | |
| 1a2f870c | 407 | by Itanium processors. The PAL procedure supports the Static Registers calling\r |
| a7b64584 | 408 | convention. It could be called at physical mode and Virtual\r |
| 409 | mode.\r | |
| 410 | \r | |
| 411 | @param Index Index of PAL_MEM_ATTRIB within the list of PAL\r | |
| 412 | procedures.\r | |
| 413 | \r | |
| 414 | @retval 0 Call completed without error\r | |
| 415 | @retval -2 Invalid argument\r | |
| 416 | @retval -3 Call completed with error.\r | |
| 417 | \r | |
| 418 | @return R9 Attributes 8-bit vector of memory attributes\r | |
| 419 | implemented by processor. See Virtual\r | |
| 420 | Memory Attributes above.\r | |
| 421 | \r | |
| 422 | **/\r | |
| 423 | \r | |
| 424 | #define PAL_MEM_ATTRIB 5\r | |
| 425 | \r | |
| 426 | /**\r | |
| 427 | PAL Procedure - PAL_PREFETCH_VISIBILITY.\r | |
| 428 | \r | |
| 429 | Used in architected sequence to transition pages from a\r | |
| 430 | cacheable, speculative attribute to an uncacheable attribute.\r | |
| 1a2f870c | 431 | It is required by Itanium processors. The PAL procedure supports the Static\r |
| a7b64584 | 432 | Registers calling convention. It could be called at physical\r |
| 433 | mode and Virtual mode.\r | |
| 434 | \r | |
| 435 | @param Index Index of PAL_PREFETCH_VISIBILITY within the list\r | |
| 436 | of PAL procedures.\r | |
| 437 | @param TransitionType Unsigned integer specifying the type\r | |
| 438 | of memory attribute transition that is\r | |
| 439 | being performed.\r | |
| 440 | \r | |
| 441 | @retval 1 Call completed without error; this\r | |
| 442 | call is not necessary on remote\r | |
| 443 | processors.\r | |
| 444 | @retval 0 Call completed without error\r | |
| 445 | @retval -2 Invalid argument\r | |
| 446 | @retval -3 Call completed with error.\r | |
| 447 | \r | |
| 448 | **/\r | |
| 449 | #define PAL_PREFETCH_VISIBILITY 41\r | |
| 450 | \r | |
| 451 | /**\r | |
| 452 | PAL Procedure - PAL_PTCE_INFO.\r | |
| 453 | \r | |
| 454 | Return information needed for ptc.e instruction to purge\r | |
| 1a2f870c | 455 | entire TC. It is required by Itanium processors. The PAL procedure supports\r |
| a7b64584 | 456 | the Static Registers calling convention. It could be called at\r |
| 457 | physical mode and Virtual mode.\r | |
| 458 | \r | |
| 459 | @param Index Index of PAL_PTCE_INFO within the list\r | |
| 460 | of PAL procedures.\r | |
| 461 | \r | |
| 462 | @retval 0 Call completed without error\r | |
| 463 | @retval -2 Invalid argument\r | |
| 464 | @retval -3 Call completed with error.\r | |
| 465 | \r | |
| 466 | @return R9 Unsigned 64-bit integer denoting the beginning\r | |
| 467 | address to be used by the first PTCE instruction\r | |
| 468 | in the purge loop.\r | |
| 469 | @return R10 Two unsigned 32-bit integers denoting the loop\r | |
| 470 | counts of the outer (loop 1) and inner (loop 2)\r | |
| 471 | purge loops. count1 (loop 1) is contained in bits\r | |
| 472 | 63:32 of the parameter, and count2 (loop 2) is\r | |
| 473 | contained in bits 31:0 of the parameter.\r | |
| 474 | @return R11 Two unsigned 32-bit integers denoting the loop\r | |
| 475 | strides of the outer (loop 1) and inner (loop 2)\r | |
| 476 | purge loops. stride1 (loop 1) is contained in bits\r | |
| 477 | 63:32 of the parameter, and stride2 (loop 2) is\r | |
| 478 | contained in bits 31:0 of the parameter.\r | |
| 479 | \r | |
| 480 | **/\r | |
| 481 | #define PAL_PTCE_INFO 6\r | |
| 482 | \r | |
| a7b64584 | 483 | typedef struct {\r |
| 992f22b9 LG |
484 | UINT64 NumberSets:8; ///< Unsigned 8-bit integer denoting the number\r |
| 485 | ///< of hash sets for the specified level\r | |
| 486 | ///< (1=fully associative)\r | |
| 487 | UINT64 NumberWays:8; ///< Unsigned 8-bit integer denoting the\r | |
| 488 | ///< associativity of the specified level\r | |
| 489 | ///< (1=direct).\r | |
| 490 | UINT64 NumberEntries:16; ///< Unsigned 16-bit integer denoting the\r | |
| 491 | ///< number of entries in the specified TC.\r | |
| 492 | UINT64 PageSizeIsOptimized:1; ///< Flag denoting whether the\r | |
| 493 | ///< specified level is optimized for\r | |
| 494 | ///< the region's preferred page size\r | |
| 495 | ///< (1=optimized) tc_pages indicates\r | |
| 496 | ///< which page sizes are usable by\r | |
| 497 | ///< this translation cache.\r | |
| 498 | UINT64 TcIsUnified:1; ///< Flag denoting whether the specified TC is\r | |
| 499 | ///< unified (1=unified).\r | |
| 500 | UINT64 EntriesReduction:1; ///< Flag denoting whether installed\r | |
| 501 | ///< translation registers will reduce\r | |
| 502 | ///< the number of entries within the\r | |
| 503 | ///< specified TC.\r | |
| a7b64584 | 504 | } PAL_TC_INFO;\r |
| 505 | \r | |
| 506 | /**\r | |
| 507 | PAL Procedure - PAL_VM_INFO.\r | |
| 508 | \r | |
| 509 | Return detailed information about virtual memory features\r | |
| 1a2f870c | 510 | supported in the processor. It is required by Itanium processors. The PAL\r |
| a7b64584 | 511 | procedure supports the Static Registers calling convention. It\r |
| 512 | could be called at physical mode and Virtual mode.\r | |
| 513 | \r | |
| 514 | @param Index Index of PAL_VM_INFO within the list\r | |
| 515 | of PAL procedures.\r | |
| 516 | @param TcLevel Unsigned 64-bit integer specifying the level\r | |
| 517 | in the TLB hierarchy for which information is\r | |
| 518 | required. This value must be between 0 and one\r | |
| 519 | less than the value returned in the\r | |
| 520 | vm_info_1.num_tc_levels return value from\r | |
| 521 | PAL_VM_SUMMARY.\r | |
| 522 | @param TcType Unsigned 64-bit integer with a value of 1 for\r | |
| 523 | instruction translation cache and 2 for data\r | |
| 524 | or unified translation cache. All other values\r | |
| 525 | are reserved.\r | |
| 526 | \r | |
| 527 | @retval 0 Call completed without error\r | |
| 528 | @retval -2 Invalid argument\r | |
| 529 | @retval -3 Call completed with error.\r | |
| 530 | \r | |
| 531 | @return R9 8-byte formatted value returning information\r | |
| 532 | about the specified TC. See PAL_TC_INFO above.\r | |
| 533 | @return R10 64-bit vector containing a bit for each page\r | |
| 534 | size supported in the specified TC, where bit\r | |
| 535 | position n indicates a page size of 2**n.\r | |
| 536 | \r | |
| 537 | **/\r | |
| 538 | #define PAL_VM_INFO 7\r | |
| 539 | \r | |
| 540 | \r | |
| 541 | /**\r | |
| 542 | PAL Procedure - PAL_VM_PAGE_SIZE.\r | |
| 543 | \r | |
| 544 | Return virtual memory TC and hardware walker page sizes\r | |
| 1a2f870c | 545 | supported in the processor. It is required by Itanium processors. The PAL\r |
| a7b64584 | 546 | procedure supports the Static Registers calling convention. It\r |
| 547 | could be called at physical mode and Virtual mode.\r | |
| 548 | \r | |
| 549 | @param Index Index of PAL_VM_PAGE_SIZE within the list\r | |
| 550 | of PAL procedures.\r | |
| 551 | \r | |
| 552 | @retval 0 Call completed without error\r | |
| 553 | @retval -2 Invalid argument\r | |
| 554 | @retval -3 Call completed with error.\r | |
| 555 | \r | |
| 556 | @return R9 64-bit vector containing a bit for each\r | |
| 557 | architected page size that is supported for\r | |
| 558 | TLB insertions and region registers.\r | |
| 559 | @return R10 64-bit vector containing a bit for each\r | |
| 560 | architected page size supported for TLB purge\r | |
| 561 | operations.\r | |
| 562 | \r | |
| 563 | **/\r | |
| 564 | #define PAL_VM_PAGE_SIZE 34\r | |
| 565 | \r | |
| a7b64584 | 566 | typedef struct {\r |
| 992f22b9 LG |
567 | UINT64 WalkerPresent:1; ///< 1-bit flag indicating whether a hardware\r |
| 568 | ///< TLB walker is implemented (1 = walker\r | |
| 569 | ///< present).\r | |
| 570 | UINT64 WidthOfPhysicalAddress: 7; ///< Unsigned 7-bit integer\r | |
| 571 | ///< denoting the number of bits of\r | |
| 572 | ///< physical address implemented.\r | |
| 573 | UINT64 WidthOfKey:8; ///< Unsigned 8-bit integer denoting the number\r | |
| 574 | ///< of bits mplemented in the PKR.key field.\r | |
| 575 | UINT64 MaxPkrIndex:8; ///< Unsigned 8-bit integer denoting the\r | |
| 576 | ///< maximum PKR index (number of PKRs-1).\r | |
| 577 | UINT64 HashTagId:8; ///< Unsigned 8-bit integer which uniquely\r | |
| 578 | ///< identifies the processor hash and tag\r | |
| 579 | ///< algorithm.\r | |
| 580 | UINT64 MaxDtrIndex:8; ///< Unsigned 8 bit integer denoting the\r | |
| 581 | ///< maximum data translation register index\r | |
| 582 | ///< (number of dtr entries - 1).\r | |
| 583 | UINT64 MaxItrIndex:8; ///< Unsigned 8 bit integer denoting the\r | |
| 584 | ///< maximum instruction translation register\r | |
| 585 | ///< index (number of itr entries - 1).\r | |
| 586 | UINT64 NumberOfUniqueTc:8; ///< Unsigned 8-bit integer denoting the\r | |
| 587 | ///< number of unique TCs implemented.\r | |
| 588 | ///< This is a maximum of\r | |
| 589 | ///< 2*num_tc_levels.\r | |
| 590 | UINT64 NumberOfTcLevels:8; ///< Unsigned 8-bit integer denoting the\r | |
| 591 | ///< number of TC levels.\r | |
| a7b64584 | 592 | } PAL_VM_INFO1;\r |
| 593 | \r | |
| a7b64584 | 594 | typedef struct {\r |
| 992f22b9 LG |
595 | UINT64 WidthOfVirtualAddress:8; ///< Unsigned 8-bit integer denoting\r |
| 596 | ///< is the total number of virtual\r | |
| 597 | ///< address bits - 1.\r | |
| 598 | UINT64 WidthOfRid:8; ///< Unsigned 8-bit integer denoting the number\r | |
| 599 | ///< of bits implemented in the RR.rid field.\r | |
| 600 | UINT64 MaxPurgedTlbs:16; ///< Unsigned 16 bit integer denoting the\r | |
| 601 | ///< maximum number of concurrent outstanding\r | |
| 602 | ///< TLB purges allowed by the processor. A\r | |
| 603 | ///< value of 0 indicates one outstanding\r | |
| 604 | ///< purge allowed. A value of 216-1\r | |
| 605 | ///< indicates no limit on outstanding\r | |
| 606 | ///< purges. All other values indicate the\r | |
| 607 | ///< actual number of concurrent outstanding\r | |
| 608 | ///< purges allowed.\r | |
| a7b64584 | 609 | UINT64 Reserved:32;\r |
| 610 | } PAL_VM_INFO2;\r | |
| 611 | \r | |
| 612 | /**\r | |
| 613 | PAL Procedure - PAL_VM_SUMMARY.\r | |
| 614 | \r | |
| 615 | Return summary information about virtual memory features\r | |
| 1a2f870c | 616 | supported in the processor. It is required by Itanium processors. The PAL\r |
| a7b64584 | 617 | procedure supports the Static Registers calling convention. It\r |
| 618 | could be called at physical mode and Virtual mode.\r | |
| 619 | \r | |
| 620 | @param Index Index of PAL_VM_SUMMARY within the list\r | |
| 621 | of PAL procedures.\r | |
| 622 | \r | |
| 623 | @retval 0 Call completed without error\r | |
| 624 | @retval -2 Invalid argument\r | |
| 625 | @retval -3 Call completed with error.\r | |
| 626 | \r | |
| 627 | @return R9 8-byte formatted value returning global virtual\r | |
| 628 | memory information. See PAL_VM_INFO1 above.\r | |
| 629 | @return R10 8-byte formatted value returning global virtual\r | |
| 630 | memory information. See PAL_VM_INFO2 above.\r | |
| 631 | \r | |
| 632 | **/\r | |
| 633 | #define PAL_VM_SUMMARY 8\r | |
| 634 | \r | |
| 635 | \r | |
| 636 | //\r | |
| 637 | // Bit mask of TR_valid flag.\r | |
| 638 | //\r | |
| 639 | #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0\r | |
| 640 | #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1\r | |
| 641 | #define PAL_TR_DIRTY_IS_VALID BIT2\r | |
| 642 | #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3\r | |
| 643 | \r | |
| 644 | \r | |
| 645 | /**\r | |
| 646 | PAL Procedure - PAL_VM_TR_READ.\r | |
| 647 | \r | |
| 648 | Read contents of a translation register. It is required by\r | |
| 1a2f870c | 649 | Itanium processors. The PAL procedure supports the Stacked Register calling\r |
| a7b64584 | 650 | convention. It could be called at physical mode.\r |
| 651 | \r | |
| 652 | @param Index Index of PAL_VM_TR_READ within the list\r | |
| 653 | of PAL procedures.\r | |
| 654 | @param RegNumber Unsigned 64-bit number denoting which TR to\r | |
| 655 | read.\r | |
| 656 | @param TrType Unsigned 64-bit number denoting whether to\r | |
| 657 | read an ITR (0) or DTR (1). All other values\r | |
| 658 | are reserved.\r | |
| 659 | @param TrBuffer 64-bit pointer to the 32-byte memory buffer in\r | |
| 660 | which translation data is returned.\r | |
| 661 | \r | |
| 662 | @retval 0 Call completed without error\r | |
| 663 | @retval -2 Invalid argument\r | |
| 664 | @retval -3 Call completed with error.\r | |
| 665 | \r | |
| 666 | @return R9 Formatted bit vector denoting which fields are\r | |
| 667 | valid. See TR_valid above.\r | |
| 668 | \r | |
| 669 | **/\r | |
| 670 | #define PAL_VM_TR_READ 261\r | |
| 671 | \r | |
| 672 | \r | |
| 673 | \r | |
| 674 | \r | |
| 675 | //\r | |
| 676 | // Bit Mask of Processor Bus Fesatures .\r | |
| 677 | //\r | |
| 678 | \r | |
| 679 | /**\r | |
| 680 | \r | |
| 681 | When 0, bus data errors are detected and single bit errors are\r | |
| 682 | corrected. When 1, no error detection or correction is done.\r | |
| 683 | \r | |
| 684 | **/\r | |
| 685 | #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63\r | |
| 686 | \r | |
| 687 | \r | |
| 688 | /**\r | |
| 689 | \r | |
| 690 | When 0, bus address errors are signalled on the bus. When 1,\r | |
| 691 | no bus errors are signalled on the bus. If Disable Bus Address\r | |
| 692 | Error Checking is 1, this bit is ignored.\r | |
| 693 | \r | |
| 694 | **/\r | |
| 695 | #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62\r | |
| 696 | \r | |
| 697 | \r | |
| 698 | \r | |
| 699 | \r | |
| 700 | /**\r | |
| 701 | \r | |
| 702 | When 0, bus errors are detected, single bit errors are\r | |
| 703 | corrected., and a CMCI or MCA is generated internally to the\r | |
| 704 | processor. When 1, no bus address errors are detected or\r | |
| 705 | corrected.\r | |
| 706 | \r | |
| 707 | **/\r | |
| 708 | #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61\r | |
| 709 | \r | |
| 710 | \r | |
| 711 | /**\r | |
| 712 | \r | |
| 713 | When 0, bus protocol errors (BINIT#) are signaled by the\r | |
| 714 | processor on the bus. When 1, bus protocol errors (BINIT#) are\r | |
| 715 | not signaled on the bus. If Disable Bus Initialization Event\r | |
| 716 | Checking is 1, this bit is ignored.\r | |
| 717 | \r | |
| 718 | **/\r | |
| 719 | #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60\r | |
| 720 | \r | |
| 721 | \r | |
| 722 | /**\r | |
| 723 | \r | |
| 724 | When 0, bus protocol errors (BINIT#) are detected and sampled\r | |
| 725 | and an MCA is generated internally to the processor. When 1,\r | |
| 726 | the processor will ignore bus protocol error conditions\r | |
| 727 | (BINIT#).\r | |
| 728 | \r | |
| 729 | **/\r | |
| 730 | #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59\r | |
| 731 | \r | |
| 732 | \r | |
| 733 | \r | |
| 734 | /**\r | |
| 735 | \r | |
| 736 | When 0, BERR# is signalled if a bus error is detected. When 1,\r | |
| 737 | bus errors are not signalled on the bus.\r | |
| 738 | \r | |
| 739 | **/\r | |
| 740 | #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58\r | |
| 741 | \r | |
| 742 | \r | |
| 743 | \r | |
| 744 | \r | |
| 745 | /**\r | |
| 746 | \r | |
| 747 | When 0, BERR# is signalled when internal processor requestor\r | |
| 748 | initiated bus errors are detected. When 1, internal requester\r | |
| 749 | bus errors are not signalled on the bus.\r | |
| 750 | \r | |
| 751 | **/\r | |
| 752 | #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57\r | |
| 753 | \r | |
| 754 | \r | |
| 755 | /**\r | |
| 756 | \r | |
| 757 | When 0, the processor takes an MCA if BERR# is asserted. When\r | |
| 758 | 1, the processor ignores the BERR# signal.\r | |
| 759 | \r | |
| 760 | **/\r | |
| 761 | #define PAL_BUS_DISABLE_ERROR_CHECK BIT56\r | |
| 762 | \r | |
| 763 | \r | |
| 764 | /**\r | |
| 765 | \r | |
| 766 | When 0, the processor asserts BINIT# if it detects a parity\r | |
| 767 | error on the signals which identify the transactions to which\r | |
| 768 | this is a response. When 1, the processor ignores parity on\r | |
| 769 | these signals.\r | |
| 770 | \r | |
| 771 | **/\r | |
| 772 | #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55\r | |
| 773 | \r | |
| 774 | \r | |
| 775 | /**\r | |
| 776 | \r | |
| 777 | When 0, the in-order transaction queue is limited only by the\r | |
| 778 | number of hardware entries. When 1, the processor's in-order\r | |
| 779 | transactions queue is limited to one entry.\r | |
| 780 | \r | |
| 781 | **/\r | |
| 782 | #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54\r | |
| 783 | \r | |
| 784 | /**\r | |
| 785 | \r | |
| 786 | Enable a bus cache line replacement transaction when a cache\r | |
| 787 | line in the exclusive state is replaced from the highest level\r | |
| 788 | processor cache and is not present in the lower level processor\r | |
| 789 | caches. When 0, no bus cache line replacement transaction will\r | |
| 790 | be seen on the bus. When 1, bus cache line replacement\r | |
| 791 | transactions will be seen on the bus when the above condition is\r | |
| 792 | detected.\r | |
| 793 | \r | |
| 794 | **/\r | |
| 795 | #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53\r | |
| 796 | \r | |
| 797 | \r | |
| 798 | /**\r | |
| 799 | \r | |
| 800 | Enable a bus cache line replacement transaction when a cache\r | |
| 801 | line in the shared or exclusive state is replaced from the\r | |
| 802 | highest level processor cache and is not present in the lower\r | |
| 803 | level processor caches.\r | |
| 804 | When 0, no bus cache line replacement transaction will be seen\r | |
| 805 | on the bus. When 1, bus cache line replacement transactions\r | |
| 806 | will be seen on the bus when the above condition is detected.\r | |
| 807 | \r | |
| 808 | **/\r | |
| 809 | #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52\r | |
| 810 | \r | |
| 811 | \r | |
| 812 | \r | |
| 813 | /**\r | |
| 814 | \r | |
| 815 | When 0, the data bus is configured at the 2x data transfer\r | |
| 816 | rate.When 1, the data bus is configured at the 1x data\r | |
| 817 | transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the\r | |
| 818 | processor executes locked transactions atomically. When 1, the\r | |
| 819 | processor masks the bus lock signal and executes locked\r | |
| 820 | transactions as a non-atomic series of transactions.\r | |
| 821 | \r | |
| 822 | **/\r | |
| 823 | #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30\r | |
| 824 | \r | |
| 825 | /**\r | |
| 826 | \r | |
| 827 | When 0, the processor will deassert bus request when finished\r | |
| 828 | with each transaction. When 1, the processor will continue to\r | |
| 829 | assert bus request after it has finished, if it was the last\r | |
| 830 | agent to own the bus and if there are no other pending\r | |
| 831 | requests.\r | |
| 832 | \r | |
| 833 | **/\r | |
| 834 | #define PAL_BUS_REQUEST_BUS_PARKING BIT29\r | |
| 835 | \r | |
| 836 | \r | |
| 837 | /**\r | |
| 838 | PAL Procedure - PAL_BUS_GET_FEATURES.\r | |
| 839 | \r | |
| 840 | Return configurable processor bus interface features and their\r | |
| 1a2f870c | 841 | current settings. It is required by Itanium processors. The PAL procedure\r |
| a7b64584 | 842 | supports the Stacked Register calling convention. It could be\r |
| 843 | called at physical mode.\r | |
| 844 | \r | |
| 845 | @param Index Index of PAL_BUS_GET_FEATURES within the list\r | |
| 846 | of PAL procedures.\r | |
| 847 | \r | |
| 848 | @retval 0 Call completed without error\r | |
| 849 | @retval -2 Invalid argument\r | |
| 850 | @retval -3 Call completed with error.\r | |
| 851 | \r | |
| 852 | @return R9 64-bit vector of features implemented.\r | |
| 853 | (1=implemented, 0=not implemented)\r | |
| 854 | @return R10 64-bit vector of current feature settings.\r | |
| 855 | @return R11 64-bit vector of features controllable by\r | |
| 856 | software. (1=controllable, 0= not controllable)\r | |
| 857 | \r | |
| 858 | **/\r | |
| 859 | #define PAL_BUS_GET_FEATURES 9\r | |
| 860 | \r | |
| 861 | /**\r | |
| 862 | PAL Procedure - PAL_BUS_SET_FEATURES.\r | |
| 863 | \r | |
| 864 | Enable or disable configurable features in processor bus\r | |
| 1a2f870c | 865 | interface. It is required by Itanium processors. The PAL procedure\r |
| a7b64584 | 866 | supports the Static Registers calling convention. It could be\r |
| 867 | called at physical mode.\r | |
| 868 | \r | |
| 869 | @param Index Index of PAL_BUS_SET_FEATURES within the list\r | |
| 870 | of PAL procedures.\r | |
| 871 | @param FeatureSelect 64-bit vector denoting desired state of\r | |
| 872 | each feature (1=select, 0=non-select).\r | |
| 873 | \r | |
| 874 | @retval 0 Call completed without error\r | |
| 875 | @retval -2 Invalid argument\r | |
| 876 | @retval -3 Call completed with error.\r | |
| 877 | \r | |
| 878 | **/\r | |
| 879 | #define PAL_BUS_SET_FEATURES 10\r | |
| 880 | \r | |
| 881 | \r | |
| 882 | /**\r | |
| 883 | PAL Procedure - PAL_DEBUG_INFO.\r | |
| 884 | \r | |
| 885 | Return the number of instruction and data breakpoint\r | |
| 1a2f870c | 886 | registers. It is required by Itanium processors. The\r |
| a7b64584 | 887 | PAL procedure supports the Static Registers calling\r |
| 888 | convention. It could be called at physical mode and virtual\r | |
| 889 | mode.\r | |
| 890 | \r | |
| 891 | @param Index Index of PAL_DEBUG_INFO within the list of PAL\r | |
| 892 | procedures.\r | |
| 893 | \r | |
| 894 | @retval 0 Call completed without error\r | |
| 895 | @retval -2 Invalid argument\r | |
| 896 | @retval -3 Call completed with error.\r | |
| 897 | \r | |
| 898 | @return R9 Unsigned 64-bit integer denoting the number of\r | |
| 899 | pairs of instruction debug registers implemented\r | |
| 900 | by the processor.\r | |
| 901 | @return R10 Unsigned 64-bit integer denoting the number of\r | |
| 902 | pairs of data debug registers implemented by the\r | |
| 903 | processor.\r | |
| 904 | \r | |
| 905 | **/\r | |
| 906 | #define PAL_DEBUG_INFO 11\r | |
| 907 | \r | |
| 908 | /**\r | |
| 909 | PAL Procedure - PAL_FIXED_ADDR.\r | |
| 910 | \r | |
| 911 | Return the fixed component of a processor's directed address.\r | |
| 1a2f870c | 912 | It is required by Itanium processors. The PAL\r |
| a7b64584 | 913 | procedure supports the Static Registers calling convention. It\r |
| 914 | could be called at physical mode and virtual mode.\r | |
| 915 | \r | |
| 916 | @param Index Index of PAL_FIXED_ADDR within the list of PAL\r | |
| 917 | procedures.\r | |
| 918 | \r | |
| 919 | @retval 0 Call completed without error\r | |
| 920 | @retval -2 Invalid argument\r | |
| 921 | @retval -3 Call completed with error.\r | |
| 922 | \r | |
| 923 | @return R9 Fixed geographical address of this processor.\r | |
| 924 | \r | |
| 925 | **/\r | |
| 926 | #define PAL_FIXED_ADDR 12\r | |
| 927 | \r | |
| 928 | /**\r | |
| 929 | PAL Procedure - PAL_FREQ_BASE.\r | |
| 930 | \r | |
| 931 | Return the frequency of the output clock for use by the\r | |
| 932 | platform, if generated by the processor. It is optinal. The\r | |
| 933 | PAL procedure supports the Static Registers calling\r | |
| 934 | convention. It could be called at physical mode and virtual\r | |
| 935 | mode.\r | |
| 936 | \r | |
| 937 | @param Index Index of PAL_FREQ_BASE within the list of PAL\r | |
| 938 | procedures.\r | |
| 939 | \r | |
| 940 | @retval 0 Call completed without error\r | |
| 941 | @retval -1 Unimplemented procedure\r | |
| 942 | @retval -2 Invalid argument\r | |
| 943 | @retval -3 Call completed with error.\r | |
| 944 | \r | |
| 945 | @return R9 Base frequency of the platform if generated by the\r | |
| 946 | processor chip.\r | |
| 947 | \r | |
| 948 | **/\r | |
| 949 | #define PAL_FREQ_BASE 13\r | |
| 950 | \r | |
| 951 | \r | |
| 952 | /**\r | |
| 953 | PAL Procedure - PAL_FREQ_RATIOS.\r | |
| 954 | \r | |
| 955 | Return ratio of processor, bus, and interval time counter to\r | |
| 956 | processor input clock or output clock for platform use, if\r | |
| 1a2f870c | 957 | generated by the processor. It is required by Itanium processors. The PAL\r |
| a7b64584 | 958 | procedure supports the Static Registers calling convention. It\r |
| 959 | could be called at physical mode and virtual mode.\r | |
| 960 | \r | |
| 961 | @param Index Index of PAL_FREQ_RATIOS within the list of PAL\r | |
| 962 | procedures.\r | |
| 963 | \r | |
| 964 | @retval 0 Call completed without error\r | |
| 965 | @retval -2 Invalid argument\r | |
| 966 | @retval -3 Call completed with error.\r | |
| 967 | \r | |
| 968 | @return R9 Ratio of the processor frequency to the input\r | |
| 969 | clock of the processor, if the platform clock is\r | |
| 970 | generated externally or to the output clock to the\r | |
| 971 | platform, if the platform clock is generated by\r | |
| 972 | the processor.\r | |
| 973 | @return R10 Ratio of the bus frequency to the input clock of\r | |
| 974 | the processor, if the platform clock is generated\r | |
| 975 | externally or to the output clock to the platform,\r | |
| 976 | if the platform clock is generated by the\r | |
| 977 | processor.\r | |
| 978 | @return R11 Ratio of the interval timer counter rate to input\r | |
| 979 | clock of the processor, if the platform clock is\r | |
| 980 | generated externally or to the output clock to the\r | |
| 981 | platform, if the platform clock is generated by\r | |
| 982 | the processor.\r | |
| 983 | \r | |
| 984 | **/\r | |
| 985 | #define PAL_FREQ_RATIOS 14\r | |
| 986 | \r | |
| a7b64584 | 987 | typedef struct {\r |
| 992f22b9 LG |
988 | UINT64 NumberOfLogicalProcessors:16; ///< Total number of logical\r |
| 989 | ///< processors on this physical\r | |
| 990 | ///< processor package that are\r | |
| 991 | ///< enabled.\r | |
| 992 | UINT64 ThreadsPerCore:8; ///< Number of threads per core.\r | |
| a7b64584 | 993 | UINT64 Reserved1:8;\r |
| e2a5ae07 | 994 | UINT64 CoresPerProcessor:8; ///< Total number of cores on this\r |
| 992f22b9 | 995 | ///< physical processor package.\r |
| a7b64584 | 996 | UINT64 Reserved2:8;\r |
| 992f22b9 LG |
997 | UINT64 PhysicalProcessorPackageId:8; ///< Physical processor package\r |
| 998 | ///< identifier which was\r | |
| 999 | ///< assigned at reset by the\r | |
| 1000 | ///< platform or bus\r | |
| 1001 | ///< controller. This value may\r | |
| 1002 | ///< or may not be unique\r | |
| 1003 | ///< across the entire platform\r | |
| 1004 | ///< since it depends on the\r | |
| 1005 | ///< platform vendor's policy.\r | |
| a7b64584 | 1006 | UINT64 Reserved3:8;\r |
| 1007 | } PAL_LOGICAL_PROCESSPR_OVERVIEW;\r | |
| 1008 | \r | |
| a7b64584 | 1009 | typedef struct {\r |
| 992f22b9 LG |
1010 | UINT64 ThreadId:16; ///< The thread identifier of the logical\r |
| 1011 | ///< processor for which information is being\r | |
| 1012 | ///< returned. This value will be unique on a per\r | |
| 1013 | ///< core basis.\r | |
| a7b64584 | 1014 | UINT64 Reserved1:16;\r |
| 992f22b9 LG |
1015 | UINT64 CoreId:16; ///< The core identifier of the logical processor\r |
| 1016 | ///< for which information is being returned.\r | |
| 1017 | ///< This value will be unique on a per physical\r | |
| 1018 | ///< processor package basis.\r | |
| a7b64584 | 1019 | UINT64 Reserved2:16;\r |
| 1020 | } PAL_LOGICAL_PROCESSORN_INFO1;\r | |
| 1021 | \r | |
| a7b64584 | 1022 | typedef struct {\r |
| 992f22b9 LG |
1023 | UINT64 LogicalAddress:16; ///< Geographical address of the logical\r |
| 1024 | ///< processor for which information is being\r | |
| 1025 | ///< returned. This is the same value that is\r | |
| 1026 | ///< returned by the PAL_FIXED_ADDR procedure\r | |
| 1027 | ///< when it is called on the logical processor.\r | |
| a7b64584 | 1028 | UINT64 Reserved:48;\r |
| 1029 | } PAL_LOGICAL_PROCESSORN_INFO2;\r | |
| 1030 | \r | |
| 1031 | /**\r | |
| 1032 | PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.\r | |
| 1033 | \r | |
| 1034 | Return information on which logical processors map to a\r | |
| 1035 | physical processor die. It is optinal. The PAL procedure\r | |
| 1036 | supports the Static Registers calling convention. It could be\r | |
| 1037 | called at physical mode and virtual mode.\r | |
| 1038 | \r | |
| 1039 | @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL\r | |
| 1040 | procedures.\r | |
| 1041 | @param ProcessorNumber Signed 64-bit integer that specifies\r | |
| 1042 | for which logical processor\r | |
| 1043 | information is being requested. When\r | |
| 1044 | this input argument is -1, information\r | |
| 1045 | is returned about the logical\r | |
| 1046 | processor on which the procedure call\r | |
| 1047 | is made. This input argument must be\r | |
| 1048 | in the range of 1 up to one less than\r | |
| 1049 | the number of logical processors\r | |
| 1050 | returned by num_log in the\r | |
| 1051 | log_overview return value.\r | |
| 1052 | \r | |
| 1053 | @retval 0 Call completed without error\r | |
| 1054 | @retval -1 Unimplemented procedure\r | |
| 1055 | @retval -2 Invalid argument\r | |
| 1056 | @retval -3 Call completed with error.\r | |
| 1057 | \r | |
| 1058 | @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.\r | |
| 1059 | @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.\r | |
| 1060 | @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.\r | |
| 1061 | \r | |
| 1062 | **/\r | |
| 1063 | #define PAL_LOGICAL_TO_PHYSICAL 42\r | |
| 1064 | \r | |
| a7b64584 | 1065 | typedef struct {\r |
| 992f22b9 LG |
1066 | UINT64 NumberOfPmcPairs:8; ///< Unsigned 8-bit number defining the\r |
| 1067 | ///< number of generic PMC/PMD pairs.\r | |
| 1068 | UINT64 WidthOfCounter:8; ///< Unsigned 8-bit number in the range\r | |
| 1069 | ///< 0:60 defining the number of\r | |
| 1070 | ///< implemented counter bits.\r | |
| 1071 | UINT64 TypeOfCycleCounting:8; ///< Unsigned 8-bit number defining the\r | |
| 1072 | ///< event type for counting processor cycles.\r | |
| 1073 | UINT64 TypeOfRetiredInstructionBundle:8; ///< Retired Unsigned 8-bit\r | |
| 1074 | ///< number defining the\r | |
| 1075 | ///< event type for retired\r | |
| 1076 | ///< instruction bundles.\r | |
| a7b64584 | 1077 | UINT64 Reserved:32;\r |
| 1078 | } PAL_PERFORMANCE_INFO;\r | |
| 1079 | \r | |
| 1080 | /**\r | |
| 1081 | PAL Procedure - PAL_PERF_MON_INFO.\r | |
| 1082 | \r | |
| 1083 | Return the number and type of performance monitors. It is\r | |
| 1a2f870c | 1084 | required by Itanium processors. The PAL procedure supports the Static\r |
| a7b64584 | 1085 | Registers calling convention. It could be called at physical\r |
| 1086 | mode and virtual mode.\r | |
| 1087 | \r | |
| 1088 | @param Index Index of PAL_PERF_MON_INFO within the list of\r | |
| 1089 | PAL procedures.\r | |
| 1090 | @param PerformanceBuffer An address to an 8-byte aligned\r | |
| 1091 | 128-byte memory buffer.\r | |
| 1092 | \r | |
| 1093 | @retval 0 Call completed without error\r | |
| 1094 | @retval -2 Invalid argument\r | |
| 1095 | @retval -3 Call completed with error.\r | |
| 1096 | \r | |
| 1097 | @return R9 Information about the performance monitors\r | |
| 1098 | implemented. See PAL_PERFORMANCE_INFO;\r | |
| 1099 | \r | |
| 1100 | **/\r | |
| 1101 | #define PAL_PERF_MON_INFO 15\r | |
| 1102 | \r | |
| 1103 | #define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0\r | |
| 1104 | #define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1\r | |
| 1105 | \r | |
| 1106 | /**\r | |
| 1107 | PAL Procedure - PAL_PLATFORM_ADDR.\r | |
| 1108 | \r | |
| 1109 | Specify processor interrupt block address and I/O port space\r | |
| 1a2f870c | 1110 | address. It is required by Itanium processors. The PAL procedure supports the\r |
| a7b64584 | 1111 | Static Registers calling convention. It could be called at\r |
| 1112 | physical mode and virtual mode.\r | |
| 1113 | \r | |
| 1114 | @param Index Index of PAL_PLATFORM_ADDR within the list of\r | |
| 1115 | PAL procedures.\r | |
| 1116 | @param Type Unsigned 64-bit integer specifying the type of\r | |
| 1117 | block. 0 indicates that the processor interrupt\r | |
| 1118 | block pointer should be initialized. 1 indicates\r | |
| 1119 | that the processor I/O block pointer should be\r | |
| 1120 | initialized.\r | |
| 1121 | @param Address Unsigned 64-bit integer specifying the address\r | |
| 1122 | to which the processor I/O block or interrupt\r | |
| 1123 | block shall be set. The address must specify\r | |
| 1124 | an implemented physical address on the\r | |
| 1125 | processor model, bit 63 is ignored.\r | |
| 1126 | \r | |
| 1127 | @retval 0 Call completed without error\r | |
| 1128 | @retval -1 Unimplemented procedure.\r | |
| 1129 | @retval -2 Invalid argument\r | |
| 1130 | @retval -3 Call completed with error.\r | |
| 1131 | \r | |
| 1132 | **/\r | |
| 1133 | #define PAL_PLATFORM_ADDR 16\r | |
| 1134 | \r | |
| a7b64584 | 1135 | typedef struct {\r |
| 1136 | UINT64 Reserved1:36;\r | |
| 992f22b9 LG |
1137 | UINT64 FaultInUndefinedIns:1; ///< Bit36, No Unimplemented\r |
| 1138 | ///< instruction address reported as\r | |
| 1139 | ///< fault. Denotes how the processor\r | |
| 1140 | ///< reports the detection of\r | |
| 1141 | ///< unimplemented instruction\r | |
| 1142 | ///< addresses. When 1, the processor\r | |
| 1143 | ///< reports an Unimplemented\r | |
| 1144 | ///< Instruction Address fault on the\r | |
| 1145 | ///< unimplemented address; when 0, it\r | |
| 1146 | ///< reports an Unimplemented\r | |
| 1147 | ///< Instruction Address trap on the\r | |
| 1148 | ///< previous instruction in program\r | |
| 1149 | ///< order. This feature may only be\r | |
| 1150 | ///< interrogated by\r | |
| 1151 | ///< PAL_PROC_GET_FEATURES. It may not\r | |
| 1152 | ///< be enabled or disabled by\r | |
| 1153 | ///< PAL_PROC_SET_FEATURES. The\r | |
| 1154 | ///< corresponding argument is ignored.\r | |
| 7e6a7a63 | 1155 | \r |
| 992f22b9 LG |
1156 | UINT64 NoPresentPmi:1; ///< Bit37, No INIT, PMI, and LINT pins\r |
| 1157 | ///< present. Denotes the absence of INIT,\r | |
| 1158 | ///< PMI, LINT0 and LINT1 pins on the\r | |
| 1159 | ///< processor. When 1, the pins are absent.\r | |
| 1160 | ///< When 0, the pins are present. This\r | |
| 1161 | ///< feature may only be interrogated by\r | |
| 1162 | ///< PAL_PROC_GET_FEATURES. It may not be\r | |
| 1163 | ///< enabled or disabled by\r | |
| 1164 | ///< PAL_PROC_SET_FEATURES. The corresponding\r | |
| 1165 | ///< argument is ignored.\r | |
| 7e6a7a63 | 1166 | \r |
| 992f22b9 LG |
1167 | UINT64 NoSimpleImpInUndefinedIns:1; ///< Bit38, No Simple\r |
| 1168 | ///< implementation of\r | |
| 1169 | ///< unimplemented instruction\r | |
| 1170 | ///< addresses. Denotes how an\r | |
| 1171 | ///< unimplemented instruction\r | |
| 1172 | ///< address is recorded in IIP\r | |
| 1173 | ///< on an Unimplemented\r | |
| 1174 | ///< Instruction Address trap or\r | |
| 1175 | ///< fault. When 1, the full\r | |
| 1176 | ///< unimplemented address is\r | |
| 1177 | ///< recorded in IIP; when 0, the\r | |
| 1178 | ///< address is sign extended\r | |
| 1179 | ///< (virtual addresses) or zero\r | |
| 1180 | ///< extended (physical\r | |
| 1181 | ///< addresses). This feature may\r | |
| 1182 | ///< only be interrogated by\r | |
| 1183 | ///< PAL_PROC_GET_FEATURES. It\r | |
| 1184 | ///< may not be enabled or\r | |
| 1185 | ///< disabled by\r | |
| 1186 | ///< PAL_PROC_SET_FEATURES. The\r | |
| 1187 | ///< corresponding argument is\r | |
| 1188 | ///< ignored.\r | |
| 1189 | \r | |
| 1190 | UINT64 NoVariablePState:1; ///< Bit39, No Variable P-state\r | |
| 1191 | ///< performance: A value of 1, indicates\r | |
| 1192 | ///< that a processor implements\r | |
| 1193 | ///< techniques to optimize performance\r | |
| 1194 | ///< for the given P-state power budget\r | |
| 1195 | ///< by dynamically varying the\r | |
| 1196 | ///< frequency, such that maximum\r | |
| 1197 | ///< performance is achieved for the\r | |
| 1198 | ///< power budget. A value of 0,\r | |
| 1199 | ///< indicates that P-states have no\r | |
| 1200 | ///< frequency variation or very small\r | |
| 1201 | ///< frequency variations for their given\r | |
| 1202 | ///< power budget. This feature may only\r | |
| 1203 | ///< be interrogated by\r | |
| 1204 | ///< PAL_PROC_GET_FEATURES. it may not be\r | |
| 1205 | ///< enabled or disabled by\r | |
| 1206 | ///< PAL_PROC_SET_FEATURES. The\r | |
| 1207 | ///< corresponding argument is ignored.\r | |
| 1208 | \r | |
| 1209 | UINT64 NoVM:1; ///< Bit40, No Virtual Machine features implemented.\r | |
| 1210 | ///< Denotes whether PSR.vm is implemented. This\r | |
| 1211 | ///< feature may only be interrogated by\r | |
| 1212 | ///< PAL_PROC_GET_FEATURES. It may not be enabled or\r | |
| 1213 | ///< disabled by PAL_PROC_SET_FEATURES. The\r | |
| 1214 | ///< corresponding argument is ignored.\r | |
| 1215 | \r | |
| 1216 | UINT64 NoXipXpsrXfs:1; ///< Bit41, No XIP, XPSR, and XFS\r | |
| 1217 | ///< implemented. Denotes whether XIP, XPSR,\r | |
| 1218 | ///< and XFS are implemented for machine\r | |
| 1219 | ///< check recovery. This feature may only be\r | |
| 1220 | ///< interrogated by PAL_PROC_GET_FEATURES.\r | |
| 1221 | ///< It may not be enabled or disabled by\r | |
| 1222 | ///< PAL_PROC_SET_FEATURES. The corresponding\r | |
| 1223 | ///< argument is ignored.\r | |
| 1224 | \r | |
| 1225 | UINT64 NoXr1ThroughXr3:1; ///< Bit42, No XR1 through XR3 implemented.\r | |
| 1226 | ///< Denotes whether XR1 XR3 are\r | |
| 1227 | ///< implemented for machine check\r | |
| 1228 | ///< recovery. This feature may only be\r | |
| 1229 | ///< interrogated by PAL_PROC_GET_FEATURES.\r | |
| 1230 | ///< It may not be enabled or disabled by\r | |
| 1231 | ///< PAL_PROC_SET_FEATURES. The\r | |
| 1232 | ///< corresponding argument is ignored.\r | |
| 1233 | \r | |
| 1234 | UINT64 DisableDynamicPrediction:1; ///< Bit43, Disable Dynamic\r | |
| 1235 | ///< Predicate Prediction. When\r | |
| 1236 | ///< 0, the processor may predict\r | |
| 1237 | ///< predicate results and\r | |
| 1238 | ///< execute speculatively, but\r | |
| 1239 | ///< may not commit results until\r | |
| 1240 | ///< the actual predicates are\r | |
| 1241 | ///< known. When 1, the processor\r | |
| 1242 | ///< shall not execute predicated\r | |
| 1243 | ///< instructions until the\r | |
| 1244 | ///< actual predicates are known.\r | |
| 1245 | \r | |
| 1246 | UINT64 DisableSpontaneousDeferral:1; ///< Bit44, Disable Spontaneous\r | |
| 1247 | ///< Deferral. When 1, the\r | |
| 1248 | ///< processor may optionally\r | |
| 1249 | ///< defer speculative loads\r | |
| 1250 | ///< that do not encounter any\r | |
| 1251 | ///< exception conditions, but\r | |
| 1252 | ///< that trigger other\r | |
| 1253 | ///< implementation-dependent\r | |
| 1254 | ///< conditions (e.g., cache\r | |
| 1255 | ///< miss). When 0, spontaneous\r | |
| 1256 | ///< deferral is disabled.\r | |
| 1257 | \r | |
| 1258 | UINT64 DisableDynamicDataCachePrefetch:1; ///< Bit45, Disable Dynamic\r | |
| 1259 | ///< Data Cache Prefetch.\r | |
| 1260 | ///< When 0, the processor\r | |
| 1261 | ///< may prefetch into the\r | |
| 1262 | ///< caches any data which\r | |
| 1263 | ///< has not been accessed\r | |
| 1264 | ///< by instruction\r | |
| 1265 | ///< execution, but which\r | |
| 1266 | ///< is likely to be\r | |
| 1267 | ///< accessed. When 1, no\r | |
| 1268 | ///< data may be fetched\r | |
| 1269 | ///< until it is needed for\r | |
| 1270 | ///< instruction execution\r | |
| 1271 | ///< or is fetched by an\r | |
| 1272 | ///< lfetch instruction.\r | |
| 1273 | \r | |
| 1274 | UINT64 DisableDynamicInsCachePrefetch:1; ///< Bit46, Disable\r | |
| 1275 | ///< DynamicInstruction Cache\r | |
| 1276 | ///< Prefetch. When 0, the\r | |
| 1277 | ///< processor may prefetch\r | |
| 1278 | ///< into the caches any\r | |
| 1279 | ///< instruction which has\r | |
| 1280 | ///< not been executed, but\r | |
| 1281 | ///< whose execution is\r | |
| 1282 | ///< likely. When 1,\r | |
| 1283 | ///< instructions may not be\r | |
| 1284 | ///< fetched until needed or\r | |
| 1285 | ///< hinted for execution.\r | |
| 1286 | ///< (Prefetch for a hinted\r | |
| 1287 | ///< branch is allowed even\r | |
| 1288 | ///< when dynamic instruction\r | |
| 1289 | ///< cache prefetch is\r | |
| 1290 | ///< disabled.)\r | |
| 1291 | \r | |
| 1292 | UINT64 DisableBranchPrediction:1; ///< Bit47, Disable Dynamic branch\r | |
| 1293 | ///< prediction. When 0, the\r | |
| 1294 | ///< processor may predict branch\r | |
| 1295 | ///< targets and speculatively\r | |
| 1296 | ///< execute, but may not commit\r | |
| 1297 | ///< results. When 1, the processor\r | |
| 1298 | ///< must wait until branch targets\r | |
| 1299 | ///< are known to execute.\r | |
| a7b64584 | 1300 | UINT64 Reserved2:4;\r |
| 992f22b9 LG |
1301 | UINT64 DisablePState:1; ///< Bit52, Disable P-states. When 1, the PAL\r |
| 1302 | ///< P-state procedures (PAL_PSTATE_INFO,\r | |
| 1303 | ///< PAL_SET_PSTATE, PAL_GET_PSTATE) will\r | |
| 1304 | ///< return with a status of -1\r | |
| 1305 | ///< (Unimplemented procedure).\r | |
| 1306 | \r | |
| 1307 | UINT64 EnableMcaOnDataPoisoning:1; ///< Bit53, Enable MCA signaling\r | |
| 1308 | ///< on data-poisoning event\r | |
| 1309 | ///< detection. When 0, a CMCI\r | |
| 1310 | ///< will be signaled on error\r | |
| 1311 | ///< detection. When 1, an MCA\r | |
| 1312 | ///< will be signaled on error\r | |
| 1313 | ///< detection. If this feature\r | |
| 1314 | ///< is not supported, then the\r | |
| 1315 | ///< corresponding argument is\r | |
| 1316 | ///< ignored when calling\r | |
| 1317 | ///< PAL_PROC_SET_FEATURES. Note\r | |
| 1318 | ///< that the functionality of\r | |
| 1319 | ///< this bit is independent of\r | |
| 1320 | ///< the setting in bit 60\r | |
| 1321 | ///< (Enable CMCI promotion), and\r | |
| 1322 | ///< that the bit 60 setting does\r | |
| 1323 | ///< not affect CMCI signaling\r | |
| 1324 | ///< for data-poisoning related\r | |
| 1325 | ///< events. Volume 2: Processor\r | |
| 1326 | ///< Abstraction Layer 2:431\r | |
| 1327 | ///< PAL_PROC_GET_FEATURES\r | |
| 1328 | \r | |
| 1329 | UINT64 EnableVmsw:1; ///< Bit54, Enable the use of the vmsw\r | |
| 1330 | ///< instruction. When 0, the vmsw instruction\r | |
| 1331 | ///< causes a Virtualization fault when\r | |
| 1332 | ///< executed at the most privileged level.\r | |
| 1333 | ///< When 1, this bit will enable normal\r | |
| 1334 | ///< operation of the vmsw instruction.\r | |
| 1335 | \r | |
| 1336 | UINT64 EnableEnvNotification:1; ///< Bit55, Enable external\r | |
| 1337 | ///< notification when the processor\r | |
| 1338 | ///< detects hardware errors caused\r | |
| 1339 | ///< by environmental factors that\r | |
| 1340 | ///< could cause loss of\r | |
| 1341 | ///< deterministic behavior of the\r | |
| 1342 | ///< processor. When 1, this bit will\r | |
| 1343 | ///< enable external notification,\r | |
| 1344 | ///< when 0 external notification is\r | |
| 1345 | ///< not provided. The type of\r | |
| 1346 | ///< external notification of these\r | |
| 1347 | ///< errors is processor-dependent. A\r | |
| 1348 | ///< loss of processor deterministic\r | |
| 1349 | ///< behavior is considered to have\r | |
| 1350 | ///< occurred if these\r | |
| 1351 | ///< environmentally induced errors\r | |
| 1352 | ///< cause the processor to deviate\r | |
| 1353 | ///< from its normal execution and\r | |
| 1354 | ///< eventually causes different\r | |
| 1355 | ///< behavior which can be observed\r | |
| 1356 | ///< at the processor bus pins.\r | |
| 1357 | ///< Processor errors that do not\r | |
| 1358 | ///< have this effects (i.e.,\r | |
| 1359 | ///< software induced machine checks)\r | |
| 1360 | ///< may or may not be promoted\r | |
| 1361 | ///< depending on the processor\r | |
| 1362 | ///< implementation.\r | |
| 1363 | \r | |
| 1364 | UINT64 DisableBinitWithTimeout:1; ///< Bit56, Disable a BINIT on\r | |
| 1365 | ///< internal processor time-out.\r | |
| 1366 | ///< When 0, the processor may\r | |
| 1367 | ///< generate a BINIT on an\r | |
| 1368 | ///< internal processor time-out.\r | |
| 1369 | ///< When 1, the processor will not\r | |
| 1370 | ///< generate a BINIT on an\r | |
| 1371 | ///< internal processor time-out.\r | |
| 1372 | ///< The event is silently ignored.\r | |
| 1373 | \r | |
| 1374 | UINT64 DisableDPM:1; ///< Bit57, Disable Dynamic Power Management\r | |
| 1375 | ///< (DPM). When 0, the hardware may reduce\r | |
| 1376 | ///< power consumption by removing the clock\r | |
| 1377 | ///< input from idle functional units. When 1,\r | |
| 1378 | ///< all functional units will receive clock\r | |
| 1379 | ///< input, even when idle.\r | |
| 1380 | \r | |
| 1381 | UINT64 DisableCoherency:1; ///< Bit58, Disable Coherency. When 0,\r | |
| 1382 | ///< the processor uses normal coherency\r | |
| 1383 | ///< requests and responses. When 1, the\r | |
| 1384 | ///< processor answers all requests as if\r | |
| 1385 | ///< the line were not present.\r | |
| 1386 | \r | |
| 1387 | UINT64 DisableCache:1; ///< Bit59, Disable Cache. When 0, the\r | |
| 1388 | ///< processor performs cast outs on\r | |
| 1389 | ///< cacheable pages and issues and responds\r | |
| 1390 | ///< to coherency requests normally. When 1,\r | |
| 1391 | ///< the processor performs a memory access\r | |
| 1392 | ///< for each reference regardless of cache\r | |
| 1393 | ///< contents and issues no coherence\r | |
| 1394 | ///< requests and responds as if the line\r | |
| 1395 | ///< were not present. Cache contents cannot\r | |
| 1396 | ///< be relied upon when the cache is\r | |
| 1397 | ///< disabled. WARNING: Semaphore\r | |
| 1398 | ///< instructions may not be atomic or may\r | |
| 1399 | ///< cause Unsupported Data Reference faults\r | |
| 1400 | ///< if caches are disabled.\r | |
| 1401 | \r | |
| 1402 | UINT64 EnableCmciPromotion:1; ///< Bit60, Enable CMCI promotion When\r | |
| 1403 | ///< 1, Corrected Machine Check\r | |
| 1404 | ///< Interrupts (CMCI) are promoted to\r | |
| 1405 | ///< MCAs. They are also further\r | |
| 1406 | ///< promoted to BERR if bit 39, Enable\r | |
| 1407 | ///< MCA promotion, is also set and\r | |
| 1408 | ///< they are promoted to BINIT if bit\r | |
| 1409 | ///< 38, Enable MCA to BINIT promotion,\r | |
| 1410 | ///< is also set. This bit has no\r | |
| 1411 | ///< effect if MCA signalling is\r | |
| 1412 | ///< disabled (see\r | |
| 1413 | ///< PAL_BUS_GET/SET_FEATURES)\r | |
| 1414 | \r | |
| 1415 | UINT64 EnableMcaToBinitPromotion:1; ///< Bit61, Enable MCA to BINIT\r | |
| 1416 | ///< promotion. When 1, machine\r | |
| 1417 | ///< check aborts (MCAs) are\r | |
| 1418 | ///< promoted to the Bus\r | |
| 1419 | ///< Initialization signal, and\r | |
| 1420 | ///< the BINIT pin is assert on\r | |
| 1421 | ///< each occurrence of an MCA.\r | |
| 1422 | ///< Setting this bit has no\r | |
| 1423 | ///< effect if BINIT signalling\r | |
| 1424 | ///< is disabled. (See\r | |
| 1425 | ///< PAL_BUS_GET/SET_FEATURES)\r | |
| 1426 | \r | |
| 1427 | UINT64 EnableMcaPromotion:1; ///< Bit62, Enable MCA promotion. When\r | |
| 1428 | ///< 1, machine check aborts (MCAs) are\r | |
| 1429 | ///< promoted to the Bus Error signal,\r | |
| 1430 | ///< and the BERR pin is assert on each\r | |
| 1431 | ///< occurrence of an MCA. Setting this\r | |
| 1432 | ///< bit has no effect if BERR\r | |
| 1433 | ///< signalling is disabled. (See\r | |
| 1434 | ///< PAL_BUS_GET/SET_FEATURES)\r | |
| 7e6a7a63 | 1435 | \r |
| 992f22b9 LG |
1436 | UINT64 EnableBerrPromotion:1; ///< Bit63. Enable BERR promotion. When\r |
| 1437 | ///< 1, the Bus Error (BERR) signal is\r | |
| 1438 | ///< promoted to the Bus Initialization\r | |
| 1439 | ///< (BINIT) signal, and the BINIT pin\r | |
| 1440 | ///< is asserted on the occurrence of\r | |
| 1441 | ///< each Bus Error. Setting this bit\r | |
| 1442 | ///< has no effect if BINIT signalling\r | |
| 1443 | ///< is disabled. (See\r | |
| 1444 | ///< PAL_BUS_GET/SET_FEATURES)\r | |
| a7b64584 | 1445 | } PAL_PROCESSOR_FEATURES;\r |
| 1446 | \r | |
| 1447 | /**\r | |
| 1448 | PAL Procedure - PAL_PROC_GET_FEATURES.\r | |
| 1449 | \r | |
| 1450 | Return configurable processor features and their current\r | |
| 1a2f870c | 1451 | setting. It is required by Itanium processors. The PAL procedure supports the\r |
| a7b64584 | 1452 | Static Registers calling convention. It could be called at\r |
| 1453 | physical mode and virtual mode.\r | |
| 1454 | \r | |
| 1455 | @param Index Index of PAL_PROC_GET_FEATURES within the list of\r | |
| 1456 | PAL procedures.\r | |
| 1457 | @param Reserved Reserved parameter.\r | |
| 1458 | @param FeatureSet Feature set information is being requested\r | |
| 1459 | for.\r | |
| 1460 | \r | |
| 1461 | @retval 1 Call completed without error; The\r | |
| 1462 | feature_set passed is not supported but a\r | |
| 1463 | feature_set of a larger value is supported.\r | |
| 1464 | @retval 0 Call completed without error\r | |
| 1465 | @retval -2 Invalid argument\r | |
| 1466 | @retval -3 Call completed with error.\r | |
| 1467 | @retval -8 feature_set passed is beyond the maximum\r | |
| 1468 | feature_set supported\r | |
| 1469 | \r | |
| 1470 | @return R9 64-bit vector of features implemented. See\r | |
| 1471 | PAL_PROCESSOR_FEATURES.\r | |
| 1472 | @return R10 64-bit vector of current feature settings. See\r | |
| 1473 | PAL_PROCESSOR_FEATURES.\r | |
| 1474 | @return R11 64-bit vector of features controllable by\r | |
| 1475 | software.\r | |
| 1476 | \r | |
| 1477 | **/\r | |
| 1478 | #define PAL_PROC_GET_FEATURES 17\r | |
| 1479 | \r | |
| 1480 | \r | |
| 1481 | /**\r | |
| 1482 | PAL Procedure - PAL_PROC_SET_FEATURES.\r | |
| 1483 | \r | |
| 1484 | Enable or disable configurable processor features. It is\r | |
| 1a2f870c | 1485 | required by Itanium processors. The PAL procedure supports the Static\r |
| a7b64584 | 1486 | Registers calling convention. It could be called at physical\r |
| 1487 | mode.\r | |
| 1488 | \r | |
| 1489 | @param Index Index of PAL_PROC_SET_FEATURES within the list of\r | |
| 1490 | PAL procedures.\r | |
| 1491 | @param FeatureSelect 64-bit vector denoting desired state of\r | |
| 1492 | each feature (1=select, 0=non-select).\r | |
| 1493 | @param FeatureSet Feature set to apply changes to. See\r | |
| 1494 | PAL_PROC_GET_FEATURES for more information\r | |
| 1495 | on feature sets.\r | |
| 1496 | \r | |
| 1497 | @retval 1 Call completed without error; The\r | |
| 1498 | feature_set passed is not supported but a\r | |
| 1499 | feature_set of a larger value is supported\r | |
| 1500 | @retval 0 Call completed without error\r | |
| 1501 | @retval -2 Invalid argument\r | |
| 1502 | @retval -3 Call completed with error.\r | |
| 1503 | @retval -8 feature_set passed is beyond the maximum\r | |
| 1504 | feature_set supported\r | |
| 1505 | \r | |
| 1506 | **/\r | |
| 1507 | #define PAL_PROC_SET_FEATURES 18\r | |
| 1508 | \r | |
| 1509 | \r | |
| 1510 | //\r | |
| 1511 | // Value of PAL_REGISTER_INFO.InfoRequest.\r | |
| 1512 | //\r | |
| 1513 | #define PAL_APPLICATION_REGISTER_IMPLEMENTED 0\r | |
| 1514 | #define PAL_APPLICATION_REGISTER_READABLE 1\r | |
| 1515 | #define PAL_CONTROL_REGISTER_IMPLEMENTED 2\r | |
| 1516 | #define PAL_CONTROL_REGISTER_READABLE 3\r | |
| 1517 | \r | |
| 1518 | \r | |
| 1519 | /**\r | |
| 1520 | PAL Procedure - PAL_REGISTER_INFO.\r | |
| 1521 | \r | |
| 1a2f870c | 1522 | Return AR and CR register information. It is required by Itanium processors.\r |
| a7b64584 | 1523 | The PAL procedure supports the Static Registers calling\r |
| 1524 | convention. It could be called at physical mode and virtual\r | |
| 1525 | mode.\r | |
| 1526 | \r | |
| 1527 | @param Index Index of PAL_REGISTER_INFO within the list of\r | |
| 1528 | PAL procedures.\r | |
| 1529 | @param InfoRequest Unsigned 64-bit integer denoting what\r | |
| 1530 | register information is requested. See\r | |
| 1531 | PAL_REGISTER_INFO.InfoRequest above.\r | |
| 1532 | \r | |
| 1533 | @retval 0 Call completed without error\r | |
| 1534 | @retval -2 Invalid argument\r | |
| 1535 | @retval -3 Call completed with error.\r | |
| 1536 | \r | |
| 1537 | @return R9 64-bit vector denoting information for registers\r | |
| 1538 | 0-63. Bit 0 is register 0, bit 63 is register 63.\r | |
| 1539 | @return R10 64-bit vector denoting information for registers\r | |
| 1540 | 64-127. Bit 0 is register 64, bit 63 is register\r | |
| 1541 | 127.\r | |
| 1542 | \r | |
| 1543 | **/\r | |
| 1544 | #define PAL_REGISTER_INFO 39\r | |
| 1545 | \r | |
| 1546 | /**\r | |
| 1547 | PAL Procedure - PAL_RSE_INFO.\r | |
| 1548 | \r | |
| 1a2f870c | 1549 | Return RSE information. It is required by Itanium processors. The PAL\r |
| a7b64584 | 1550 | procedure supports the Static Registers calling convention. It\r |
| 1551 | could be called at physical mode and virtual mode.\r | |
| 1552 | \r | |
| 1553 | @param Index Index of PAL_RSE_INFO within the list of\r | |
| 1554 | PAL procedures.\r | |
| 1555 | @param InfoRequest Unsigned 64-bit integer denoting what\r | |
| 1556 | register information is requested. See\r | |
| 1557 | PAL_REGISTER_INFO.InfoRequest above.\r | |
| 1558 | \r | |
| 1559 | @retval 0 Call completed without error\r | |
| 1560 | @retval -2 Invalid argument\r | |
| 1561 | @retval -3 Call completed with error.\r | |
| 1562 | \r | |
| 1563 | @return R9 Number of physical stacked general registers.\r | |
| 1564 | @return R10 RSE hints supported by processor.\r | |
| 1565 | \r | |
| 1566 | **/\r | |
| 1567 | #define PAL_RSE_INFO 19\r | |
| 1568 | \r | |
| a7b64584 | 1569 | typedef struct {\r |
| 992f22b9 LG |
1570 | UINT64 VersionOfPalB:16; ///< Is a 16-bit binary coded decimal (BCD)\r |
| 1571 | ///< number that provides identification\r | |
| 1572 | ///< information about the PAL_B firmware.\r | |
| a7b64584 | 1573 | UINT64 Reserved1:8;\r |
| 992f22b9 LG |
1574 | UINT64 PalVendor:8; ///< Is an unsigned 8-bit integer indicating the\r |
| 1575 | ///< vendor of the PAL code.\r | |
| 1576 | UINT64 VersionOfPalA:16; ///< Is a 16-bit binary coded decimal (BCD)\r | |
| 1577 | ///< number that provides identification\r | |
| 1578 | ///< information about the PAL_A firmware. In\r | |
| 1579 | ///< the split PAL_A model, this return value\r | |
| 1580 | ///< is the version number of the\r | |
| 1581 | ///< processor-specific PAL_A. The generic\r | |
| 1582 | ///< PAL_A version is not returned by this\r | |
| 1583 | ///< procedure in the split PAL_A model.\r | |
| a7b64584 | 1584 | UINT64 Reserved2:16;\r |
| 1585 | } PAL_VERSION_INFO;\r | |
| 1586 | \r | |
| 1587 | /**\r | |
| 1588 | PAL Procedure - PAL_VERSION.\r | |
| 1589 | \r | |
| 1a2f870c | 1590 | Return version of PAL code. It is required by Itanium processors. The PAL\r |
| a7b64584 | 1591 | procedure supports the Static Registers calling convention. It\r |
| 1592 | could be called at physical mode and virtual mode.\r | |
| 1593 | \r | |
| 1594 | @param Index Index of PAL_VERSION within the list of\r | |
| 1595 | PAL procedures.\r | |
| 1596 | @param InfoRequest Unsigned 64-bit integer denoting what\r | |
| 1597 | register information is requested. See\r | |
| 1598 | PAL_REGISTER_INFO.InfoRequest above.\r | |
| 1599 | \r | |
| 1600 | @retval 0 Call completed without error\r | |
| 1601 | @retval -2 Invalid argument\r | |
| 1602 | @retval -3 Call completed with error.\r | |
| 1603 | \r | |
| 1604 | @return R9 8-byte formatted value returning the minimum PAL\r | |
| 1605 | version needed for proper operation of the\r | |
| 1606 | processor. See PAL_VERSION_INFO above.\r | |
| 1607 | @return R10 8-byte formatted value returning the current PAL\r | |
| 1608 | version running on the processor. See\r | |
| 1609 | PAL_VERSION_INFO above.\r | |
| 1610 | \r | |
| 1611 | **/\r | |
| 1612 | #define PAL_VERSION 20\r | |
| 1613 | \r | |
| 1614 | \r | |
| 1615 | \r | |
| 1616 | //\r | |
| 1617 | // Vectors of PAL_MC_CLEAR_LOG.pending\r | |
| 1618 | //\r | |
| 1619 | #define PAL_MC_PENDING BIT0\r | |
| 1620 | #define PAL_INIT_PENDING BIT1\r | |
| 1621 | \r | |
| 1622 | /**\r | |
| 1623 | PAL Procedure - PAL_MC_CLEAR_LOG.\r | |
| 1624 | \r | |
| 1625 | Clear all error information from processor error logging\r | |
| 1a2f870c | 1626 | registers. It is required by Itanium processors. The PAL procedure supports\r |
| a7b64584 | 1627 | the Static Registers calling convention. It could be called at\r |
| 1628 | physical mode and virtual mode.\r | |
| 1629 | \r | |
| 1630 | @param Index Index of PAL_MC_CLEAR_LOG within the list of\r | |
| 1631 | PAL procedures.\r | |
| 1632 | \r | |
| 1633 | @retval 0 Call completed without error\r | |
| 1634 | @retval -2 Invalid argument\r | |
| 1635 | @retval -3 Call completed with error.\r | |
| 1636 | \r | |
| 1637 | @return R9 64-bit vector denoting whether an event is\r | |
| 1638 | pending. See PAL_MC_CLEAR_LOG.pending above.\r | |
| 1639 | \r | |
| 1640 | **/\r | |
| 1641 | #define PAL_MC_CLEAR_LOG 21\r | |
| 1642 | \r | |
| 1643 | /**\r | |
| 1644 | PAL Procedure - PAL_MC_DRAIN.\r | |
| 1645 | \r | |
| 1646 | Ensure that all operations that could cause an MCA have\r | |
| 1a2f870c | 1647 | completed. It is required by Itanium processors. The PAL procedure supports\r |
| a7b64584 | 1648 | the Static Registers calling convention. It could be called at\r |
| 1649 | physical mode and virtual mode.\r | |
| 1650 | \r | |
| 1651 | @param Index Index of PAL_MC_DRAIN within the list of PAL\r | |
| 1652 | procedures.\r | |
| 1653 | \r | |
| 1654 | @retval 0 Call completed without error\r | |
| 1655 | @retval -2 Invalid argument\r | |
| 1656 | @retval -3 Call completed with error.\r | |
| 1657 | \r | |
| 1658 | **/\r | |
| 1659 | #define PAL_MC_DRAIN 22\r | |
| 1660 | \r | |
| 1661 | \r | |
| 1662 | /**\r | |
| 1663 | PAL Procedure - PAL_MC_DYNAMIC_STATE.\r | |
| 1664 | \r | |
| 1665 | Return Processor Dynamic State for logging by SAL. It is\r | |
| 1666 | optional. The PAL procedure supports the Static Registers\r | |
| 1667 | calling convention. It could be called at physical mode.\r | |
| 1668 | \r | |
| 1669 | @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL\r | |
| 1670 | procedures.\r | |
| 1671 | @param Offset Offset of the next 8 bytes of Dynamic Processor\r | |
| 1672 | State to return. (multiple of 8).\r | |
| 1673 | \r | |
| 1674 | @retval 0 Call completed without error\r | |
| 1675 | @retval -1 Unimplemented procedure.\r | |
| 1676 | @retval -2 Invalid argument\r | |
| 1677 | @retval -3 Call completed with error.\r | |
| 1678 | \r | |
| 1679 | @return R9 Unsigned 64-bit integer denoting bytes of Dynamic\r | |
| 1680 | Processor State returned.\r | |
| 1681 | @return R10 Next 8 bytes of Dynamic Processor State.\r | |
| 1682 | \r | |
| 1683 | **/\r | |
| 1684 | #define PAL_MC_DYNAMIC_STATE 24\r | |
| 1685 | \r | |
| 1686 | \r | |
| 1687 | \r | |
| 1688 | //\r | |
| 1689 | // Values of PAL_MC_ERROR_INFO.InfoIndex.\r | |
| 1690 | //\r | |
| 1691 | #define PAL_PROCESSOR_ERROR_MAP 0\r | |
| 1692 | #define PAL_PROCESSOR_STATE_PARAM 1\r | |
| 1693 | #define PAL_STRUCTURE_SPECIFIC_ERROR 2\r | |
| 1694 | \r | |
| a7b64584 | 1695 | typedef struct {\r |
| 992f22b9 LG |
1696 | UINT64 CoreId:4; ///< Bit3:0, Processor core ID (default is 0 for\r |
| 1697 | ///< processors with a single core)\r | |
| 1698 | \r | |
| 1699 | UINT64 ThreadId:4; ///< Bit7:4, Logical thread ID (default is 0 for\r | |
| 1700 | ///< processors that execute a single thread)\r | |
| 1701 | \r | |
| 1702 | UINT64 InfoOfInsCache:4; ///< Bit11:8, Error information is\r | |
| 1703 | ///< available for 1st, 2nd, 3rd, and 4th\r | |
| 1704 | ///< level instruction caches.\r | |
| 1705 | \r | |
| 1706 | UINT64 InfoOfDataCache:4; ///< Bit15:12, Error information is\r | |
| 1707 | ///< available for 1st, 2nd, 3rd, and 4th\r | |
| 1708 | ///< level data/unified caches.\r | |
| 1709 | \r | |
| 1710 | UINT64 InfoOfInsTlb:4; ///< Bit19:16 Error information is available\r | |
| 1711 | ///< for 1st, 2nd, 3rd, and 4th level\r | |
| 1712 | ///< instruction TLB.\r | |
| 1713 | \r | |
| 1714 | UINT64 InfoOfDataTlb:4; ///< Bit23:20, Error information is available\r | |
| 1715 | ///< for 1st, 2nd, 3rd, and 4th level\r | |
| 1716 | ///< data/unified TLB\r | |
| 1717 | \r | |
| 1718 | UINT64 InfoOfProcessorBus:4; ///< Bit27:24 Error information is\r | |
| 1719 | ///< available for the 1st, 2nd, 3rd,\r | |
| 1720 | ///< and 4th level processor bus\r | |
| 1721 | ///< hierarchy.\r | |
| 1722 | UINT64 InfoOfRegisterFile:4; ///< Bit31:28 Error information is\r | |
| 1723 | ///< available on register file\r | |
| 1724 | ///< structures.\r | |
| 1725 | UINT64 InfoOfMicroArch:4; ///< Bit47:32, Error information is\r | |
| 1726 | ///< available on micro-architectural\r | |
| 1727 | ///< structures.\r | |
| a7b64584 | 1728 | UINT64 Reserved:16;\r |
| 1729 | } PAL_MC_ERROR_INFO_LEVEL_INDEX;\r | |
| 1730 | \r | |
| 1731 | //\r | |
| 1732 | // Value of PAL_MC_ERROR_INFO.ErrorTypeIndex\r | |
| 1733 | //\r | |
| 1734 | #define PAL_ERR_INFO_BY_LEVEL_INDEX 0\r | |
| 1735 | #define PAL_ERR_INFO_TARGET_ADDRESS 1\r | |
| 1736 | #define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2\r | |
| 1737 | #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3\r | |
| 1738 | #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4\r | |
| 1739 | \r | |
| a7b64584 | 1740 | typedef struct {\r |
| 992f22b9 LG |
1741 | UINT64 Operation:4; ///< Bit3:0, Type of cache operation that caused\r |
| 1742 | ///< the machine check: 0 - unknown or internal\r | |
| 1743 | ///< error 1 - load 2 - store 3 - instruction\r | |
| 1744 | ///< fetch or instruction prefetch 4 - data\r | |
| 1745 | ///< prefetch (both hardware and software) 5 -\r | |
| 1746 | ///< snoop (coherency check) 6 - cast out\r | |
| 1747 | ///< (explicit or implicit write-back of a cache\r | |
| 1748 | ///< line) 7 - move in (cache line fill)\r | |
| 1749 | \r | |
| 1750 | UINT64 FailedCacheLevel:2; ///< Bit5:4 Level of cache where the\r | |
| 1751 | ///< error occurred. A value of 0\r | |
| 1752 | ///< indicates the first level of cache.\r | |
| a7b64584 | 1753 | UINT64 Reserved1:2;\r |
| 992f22b9 LG |
1754 | UINT64 FailedInDataPart:1; ///< Bit8, Failure located in the data part of the cache line.\r |
| 1755 | UINT64 FailedInTagPart:1; ///< Bit9, Failure located in the tag part of the cache line.\r | |
| 1756 | UINT64 FailedInDataCache:1; ///< Bit10, Failure located in the data cache\r | |
| 7e6a7a63 | 1757 | \r |
| 992f22b9 LG |
1758 | UINT64 FailedInInsCache:1; ///< Bit11, Failure located in the\r |
| 1759 | ///< instruction cache.\r | |
| 7e6a7a63 | 1760 | \r |
| 992f22b9 LG |
1761 | UINT64 Mesi:3; ///< Bit14:12, 0 - cache line is invalid. 1 - cache\r |
| 1762 | ///< line is held shared. 2 - cache line is held\r | |
| 1763 | ///< exclusive. 3 - cache line is modified. All other\r | |
| 1764 | ///< values are reserved.\r | |
| 7e6a7a63 | 1765 | \r |
| 992f22b9 LG |
1766 | UINT64 MesiIsValid:1; ///< Bit15, The mesi field in the cache_check\r |
| 1767 | ///< parameter is valid.\r | |
| 7e6a7a63 | 1768 | \r |
| 992f22b9 LG |
1769 | UINT64 FailedWay:5; ///< Bit20:16, Failure located in the way of\r |
| 1770 | ///< the cache indicated by this value.\r | |
| 7e6a7a63 | 1771 | \r |
| 992f22b9 LG |
1772 | UINT64 WayIndexIsValid:1; ///< Bit21, The way and index field in the\r |
| 1773 | ///< cache_check parameter is valid.\r | |
| a7b64584 | 1774 | \r |
| 1775 | UINT64 Reserved2:1;\r | |
| 992f22b9 LG |
1776 | UINT64 MultipleBitsError:1; ///< Bit23, A multiple-bit error was\r |
| 1777 | ///< detected, and data was poisoned for\r | |
| 1778 | ///< the corresponding cache line during\r | |
| 1779 | ///< castout.\r | |
| a7b64584 | 1780 | UINT64 Reserved3:8;\r |
| 992f22b9 LG |
1781 | UINT64 IndexOfCacheLineError:20; ///< Bit51:32, Index of the cache\r |
| 1782 | ///< line where the error occurred.\r | |
| a7b64584 | 1783 | UINT64 Reserved4:2;\r |
| a7b64584 | 1784 | \r |
| 992f22b9 LG |
1785 | UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value\r |
| 1786 | ///< is set to zero, the instruction that\r | |
| 1787 | ///< generated the machine check was an\r | |
| 1788 | ///< Intel Itanium instruction. If this bit\r | |
| 1789 | ///< is set to one, the instruction that\r | |
| 1790 | ///< generated the machine check was IA-32\r | |
| 1791 | ///< instruction.\r | |
| 1792 | \r | |
| 1793 | UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the\r | |
| 1794 | ///< cache_check parameter is valid.\r | |
| 1795 | \r | |
| 1796 | UINT64 PrivilegeLevel:2; ///< Bit57:56, Privilege level. The\r | |
| 1797 | ///< privilege level of the instruction\r | |
| 1798 | ///< bundle responsible for generating the\r | |
| 1799 | ///< machine check.\r | |
| 1800 | \r | |
| 1801 | UINT64 PrivilegeLevelIsValide:1; ///< Bit58, The pl field of the\r | |
| 1802 | ///< cache_check parameter is\r | |
| 1803 | ///< valid.\r | |
| 1804 | \r | |
| 1805 | UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit\r | |
| 1806 | ///< is set to one to indicate that the machine\r | |
| 1807 | ///< check has been corrected.\r | |
| 1808 | \r | |
| 1809 | UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:\r | |
| 1810 | ///< This bit is set to one to\r | |
| 1811 | ///< indicate that a valid target\r | |
| 1812 | ///< address has been logged.\r | |
| 1813 | \r | |
| 1814 | UINT64 RequesterIdentifier:1; ///< Bit61, Requester identifier: This\r | |
| 1815 | ///< bit is set to one to indicate that\r | |
| 1816 | ///< a valid requester identifier has\r | |
| 1817 | ///< been logged.\r | |
| 1818 | \r | |
| 1819 | UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This\r | |
| 1820 | ///< bit is set to one to indicate that\r | |
| 1821 | ///< a valid responder identifier has\r | |
| 1822 | ///< been logged.\r | |
| 1823 | \r | |
| 1824 | UINT64 PreciseInsPointer:1; ///< Bit63, Precise instruction pointer.\r | |
| 1825 | ///< This bit is set to one to indicate\r | |
| 1826 | ///< that a valid precise instruction\r | |
| 1827 | ///< pointer has been logged.\r | |
| a7b64584 | 1828 | \r |
| 1829 | } PAL_CACHE_CHECK_INFO;\r | |
| 1830 | \r | |
| a7b64584 | 1831 | \r |
| a7b64584 | 1832 | typedef struct {\r |
| 992f22b9 LG |
1833 | UINT64 FailedSlot:8; ///< Bit7:0, Slot number of the translation\r |
| 1834 | ///< register where the failure occurred.\r | |
| 1835 | UINT64 FailedSlotIsValid:1; ///< Bit8, The tr_slot field in the\r | |
| 1836 | ///< TLB_check parameter is valid.\r | |
| a7b64584 | 1837 | UINT64 Reserved1 :1;\r |
| 992f22b9 LG |
1838 | UINT64 TlbLevel:2; ///< Bit11:10, The level of the TLB where the\r |
| 1839 | ///< error occurred. A value of 0 indicates the\r | |
| 1840 | ///< first level of TLB\r | |
| a7b64584 | 1841 | UINT64 Reserved2 :4;\r |
| 7e6a7a63 | 1842 | \r |
| 992f22b9 LG |
1843 | UINT64 FailedInDataTr:1; ///< Bit16, Error occurred in the data\r |
| 1844 | ///< translation registers.\r | |
| 1845 | \r | |
| 1846 | UINT64 FailedInInsTr:1; ///< Bit17, Error occurred in the instruction\r | |
| 1847 | ///< translation registers\r | |
| 1848 | \r | |
| 1849 | UINT64 FailedInDataTc:1; ///< Bit18, Error occurred in data\r | |
| 1850 | ///< translation cache.\r | |
| 1851 | \r | |
| 1852 | UINT64 FailedInInsTc:1; ///< Bit19, Error occurred in the instruction\r | |
| 1853 | ///< translation cache.\r | |
| 1854 | \r | |
| 1855 | UINT64 FailedOperation:4; ///< Bit23:20, Type of cache operation that\r | |
| 1856 | ///< caused the machine check: 0 - unknown\r | |
| 1857 | ///< 1 - TLB access due to load instruction\r | |
| 1858 | ///< 2 - TLB access due to store\r | |
| 1859 | ///< instruction 3 - TLB access due to\r | |
| 1860 | ///< instruction fetch or instruction\r | |
| 1861 | ///< prefetch 4 - TLB access due to data\r | |
| 1862 | ///< prefetch (both hardware and software)\r | |
| 1863 | ///< 5 - TLB shoot down access 6 - TLB\r | |
| 1864 | ///< probe instruction (probe, tpa) 7 -\r | |
| 1865 | ///< move in (VHPT fill) 8 - purge (insert\r | |
| 1866 | ///< operation that purges entries or a TLB\r | |
| 1867 | ///< purge instruction) All other values\r | |
| 1868 | ///< are reserved.\r | |
| 7e6a7a63 | 1869 | \r |
| a7b64584 | 1870 | UINT64 Reserved3:30;\r |
| 992f22b9 LG |
1871 | UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value\r |
| 1872 | ///< is set to zero, the instruction that\r | |
| 1873 | ///< generated the machine check was an\r | |
| 1874 | ///< Intel Itanium instruction. If this bit\r | |
| 1875 | ///< is set to one, the instruction that\r | |
| 1876 | ///< generated the machine check was IA-32\r | |
| 1877 | ///< instruction.\r | |
| 1878 | \r | |
| 1879 | UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the\r | |
| 1880 | ///< TLB_check parameter is valid.\r | |
| 1881 | \r | |
| 1882 | UINT64 PrivelegeLevel:2; ///< Bit57:56, Privilege level. The\r | |
| 1883 | ///< privilege level of the instruction\r | |
| 1884 | ///< bundle responsible for generating the\r | |
| 1885 | ///< machine check.\r | |
| 1886 | \r | |
| 1887 | UINT64 PrivelegeLevelIsValid:1; ///< Bit58, The pl field of the\r | |
| 1888 | ///< TLB_check parameter is valid.\r | |
| 1889 | \r | |
| 1890 | UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit\r | |
| 1891 | ///< is set to one to indicate that the machine\r | |
| 1892 | ///< check has been corrected.\r | |
| 1893 | \r | |
| 1894 | UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:\r | |
| 1895 | ///< This bit is set to one to\r | |
| 1896 | ///< indicate that a valid target\r | |
| 1897 | ///< address has been logged.\r | |
| 1898 | \r | |
| 1899 | UINT64 RequesterIdentifier:1; ///< Bit61 Requester identifier: This\r | |
| 1900 | ///< bit is set to one to indicate that\r | |
| 1901 | ///< a valid requester identifier has\r | |
| 1902 | ///< been logged.\r | |
| 1903 | \r | |
| 1904 | UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This\r | |
| 1905 | ///< bit is set to one to indicate that\r | |
| 1906 | ///< a valid responder identifier has\r | |
| 1907 | ///< been logged.\r | |
| 1908 | \r | |
| 1909 | UINT64 PreciseInsPointer:1; ///< Bit63 Precise instruction pointer.\r | |
| 1910 | ///< This bit is set to one to indicate\r | |
| 1911 | ///< that a valid precise instruction\r | |
| 1912 | ///< pointer has been logged.\r | |
| a7b64584 | 1913 | } PAL_TLB_CHECK_INFO;\r |
| 1914 | \r | |
| 1915 | /**\r | |
| 1916 | PAL Procedure - PAL_MC_ERROR_INFO.\r | |
| 1917 | \r | |
| 1918 | Return Processor Machine Check Information and Processor\r | |
| 1a2f870c | 1919 | Static State for logging by SAL. It is required by Itanium processors. The\r |
| a7b64584 | 1920 | PAL procedure supports the Static Registers calling\r |
| 1921 | convention. It could be called at physical and virtual mode.\r | |
| 1922 | \r | |
| 1923 | @param Index Index of PAL_MC_ERROR_INFO within the list of PAL\r | |
| 1924 | procedures.\r | |
| 1925 | @param InfoIndex Unsigned 64-bit integer identifying the\r | |
| 1926 | error information that is being requested.\r | |
| 1927 | See PAL_MC_ERROR_INFO.InfoIndex.\r | |
| 1928 | @param LevelIndex 8-byte formatted value identifying the\r | |
| 1929 | structure to return error information\r | |
| 1930 | on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.\r | |
| 1931 | @param ErrorTypeIndex Unsigned 64-bit integer denoting the\r | |
| 1932 | type of error information that is\r | |
| 1933 | being requested for the structure\r | |
| 1934 | identified in LevelIndex.\r | |
| 1935 | \r | |
| 1936 | @retval 0 Call completed without error\r | |
| 1937 | @retval -2 Invalid argument\r | |
| 1938 | @retval -3 Call completed with error.\r | |
| 1939 | @retval -6 Argument was valid, but no error\r | |
| 1940 | information was available\r | |
| 1941 | \r | |
| 1942 | @return R9 Error information returned. The format of this\r | |
| 1943 | value is dependant on the input values passed.\r | |
| 1944 | @return R10 If this value is zero, all the error information\r | |
| 1945 | specified by err_type_index has been returned. If\r | |
| 1946 | this value is one, more structure-specific error\r | |
| 1947 | information is available and the caller needs to\r | |
| 1948 | make this procedure call again with level_index\r | |
| 1949 | unchanged and err_type_index, incremented.\r | |
| 1950 | \r | |
| 1951 | **/\r | |
| 1952 | #define PAL_MC_ERROR_INFO 25\r | |
| 1953 | \r | |
| 1954 | /**\r | |
| 1955 | PAL Procedure - PAL_MC_EXPECTED.\r | |
| 1956 | \r | |
| 1957 | Set/Reset Expected Machine Check Indicator. It is required by\r | |
| 1a2f870c | 1958 | Itanium processors. The PAL procedure supports the Static Registers calling\r |
| a7b64584 | 1959 | convention. It could be called at physical mode.\r |
| 1960 | \r | |
| 1961 | @param Index Index of PAL_MC_EXPECTED within the list of PAL\r | |
| 1962 | procedures.\r | |
| 1963 | @param Expected Unsigned integer with a value of 0 or 1 to\r | |
| 1964 | set or reset the hardware resource\r | |
| 1965 | PALE_CHECK examines for expected machine\r | |
| 1966 | checks.\r | |
| 1967 | \r | |
| 1968 | @retval 0 Call completed without error\r | |
| 1969 | @retval -2 Invalid argument\r | |
| 1970 | @retval -3 Call completed with error.\r | |
| 1971 | \r | |
| 1972 | @return R9 Unsigned integer denoting whether a machine check\r | |
| 1973 | was previously expected.\r | |
| 1974 | \r | |
| 1975 | **/\r | |
| 1976 | #define PAL_MC_EXPECTED 23\r | |
| 1977 | \r | |
| 1978 | /**\r | |
| 1979 | PAL Procedure - PAL_MC_REGISTER_MEM.\r | |
| 1980 | \r | |
| 1981 | Register min-state save area with PAL for machine checks and\r | |
| 1a2f870c | 1982 | inits. It is required by Itanium processors. The PAL procedure supports the\r |
| a7b64584 | 1983 | Static Registers calling convention. It could be called at\r |
| 1984 | physical mode.\r | |
| 1985 | \r | |
| 1986 | @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL\r | |
| 1987 | procedures.\r | |
| 1988 | @param Address Physical address of the buffer to be\r | |
| 1989 | registered with PAL.\r | |
| 1990 | \r | |
| 1991 | @retval 0 Call completed without error\r | |
| 1992 | @retval -2 Invalid argument\r | |
| 1993 | @retval -3 Call completed with error.\r | |
| 1994 | \r | |
| 1995 | **/\r | |
| 1996 | #define PAL_MC_REGISTER_MEM 27\r | |
| 1997 | \r | |
| 1998 | /**\r | |
| 1999 | PAL Procedure - PAL_MC_RESUME.\r | |
| 2000 | \r | |
| 2001 | Restore minimal architected state and return to interrupted\r | |
| 1a2f870c | 2002 | process. It is required by Itanium processors. The PAL procedure supports the\r |
| a7b64584 | 2003 | Static Registers calling convention. It could be called at\r |
| 2004 | physical mode.\r | |
| 2005 | \r | |
| 2006 | @param Index Index of PAL_MC_RESUME within the list of PAL\r | |
| 2007 | procedures.\r | |
| 2008 | @param SetCmci Unsigned 64 bit integer denoting whether to\r | |
| 2009 | set the CMC interrupt. A value of 0 indicates\r | |
| 2010 | not to set the interrupt, a value of 1\r | |
| 2011 | indicated to set the interrupt, and all other\r | |
| 2012 | values are reserved.\r | |
| 2013 | @param SavePtr Physical address of min-state save area used\r | |
| 2014 | to used to restore processor state.\r | |
| 2015 | @param NewContext Unsigned 64-bit integer denoting whether\r | |
| 2016 | the caller is returning to a new context.\r | |
| 2017 | A value of 0 indicates the caller is\r | |
| 2018 | returning to the interrupted context, a\r | |
| 2019 | value of 1 indicates that the caller is\r | |
| 2020 | returning to a new context.\r | |
| 2021 | \r | |
| 2022 | @retval -2 Invalid argument\r | |
| 2023 | @retval -3 Call completed with error.\r | |
| 2024 | \r | |
| 2025 | **/\r | |
| 2026 | #define PAL_MC_RESUME 26\r | |
| 2027 | \r | |
| 2028 | /**\r | |
| 2029 | PAL Procedure - PAL_HALT.\r | |
| 2030 | \r | |
| 2031 | Enter the low-power HALT state or an implementation-dependent\r | |
| 2032 | low-power state. It is optinal. The PAL procedure supports the\r | |
| 2033 | Static Registers calling convention. It could be called at\r | |
| 2034 | physical mode.\r | |
| 2035 | \r | |
| 2036 | @param Index Index of PAL_HALT within the list of PAL\r | |
| 2037 | procedures.\r | |
| 2038 | @param HaltState Unsigned 64-bit integer denoting low power\r | |
| 2039 | state requested.\r | |
| 2040 | @param IoDetailPtr 8-byte aligned physical address pointer to\r | |
| 2041 | information on the type of I/O\r | |
| 2042 | (load/store) requested.\r | |
| 2043 | \r | |
| 2044 | @retval 0 Call completed without error\r | |
| 2045 | @retval -1 Unimplemented procedure\r | |
| 2046 | @retval -2 Invalid argument\r | |
| 2047 | @retval -3 Call completed with error.\r | |
| 2048 | \r | |
| 2049 | @return R9 Value returned if a load instruction is requested\r | |
| 2050 | in the io_detail_ptr\r | |
| 2051 | \r | |
| 2052 | **/\r | |
| 2053 | #define PAL_HALT 28\r | |
| 2054 | \r | |
| 2055 | \r | |
| 2056 | /**\r | |
| 2057 | PAL Procedure - PAL_HALT_INFO.\r | |
| 2058 | \r | |
| 2059 | Return the low power capabilities of the processor. It is\r | |
| 1a2f870c | 2060 | required by Itanium processors. The PAL procedure supports the\r |
| a7b64584 | 2061 | Stacked Registers calling convention. It could be called at\r |
| 2062 | physical and virtual mode.\r | |
| 2063 | \r | |
| 2064 | @param Index Index of PAL_HALT_INFO within the list of PAL\r | |
| 2065 | procedures.\r | |
| 2066 | @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned\r | |
| 2067 | on an 8-byte boundary.\r | |
| 2068 | \r | |
| 2069 | @retval 0 Call completed without error\r | |
| 2070 | @retval -2 Invalid argument\r | |
| 2071 | @retval -3 Call completed with error.\r | |
| 2072 | \r | |
| 2073 | **/\r | |
| 2074 | #define PAL_HALT_INFO 257\r | |
| 2075 | \r | |
| 2076 | \r | |
| 2077 | /**\r | |
| 2078 | PAL Procedure - PAL_HALT_LIGHT.\r | |
| 2079 | \r | |
| 2080 | Enter the low power LIGHT HALT state. It is required by\r | |
| 1a2f870c | 2081 | Itanium processors. The PAL procedure supports the Static Registers calling\r |
| a7b64584 | 2082 | convention. It could be called at physical and virtual mode.\r |
| 2083 | \r | |
| 2084 | @param Index Index of PAL_HALT_LIGHT within the list of PAL\r | |
| 2085 | procedures.\r | |
| 2086 | \r | |
| 2087 | @retval 0 Call completed without error\r | |
| 2088 | @retval -2 Invalid argument\r | |
| 2089 | @retval -3 Call completed with error.\r | |
| 2090 | \r | |
| 2091 | **/\r | |
| 2092 | #define PAL_HALT_LIGHT 29\r | |
| 2093 | \r | |
| 2094 | /**\r | |
| 2095 | PAL Procedure - PAL_CACHE_LINE_INIT.\r | |
| 2096 | \r | |
| 2097 | Initialize tags and data of a cache line for processor\r | |
| 1a2f870c | 2098 | testing. It is required by Itanium processors. The PAL procedure supports the\r |
| a7b64584 | 2099 | Static Registers calling convention. It could be called at\r |
| 2100 | physical and virtual mode.\r | |
| 2101 | \r | |
| 2102 | @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL\r | |
| 2103 | procedures.\r | |
| 2104 | @param Address Unsigned 64-bit integer value denoting the\r | |
| 2105 | physical address from which the physical page\r | |
| 2106 | number is to be generated. The address must be\r | |
| 2107 | an implemented physical address, bit 63 must\r | |
| 2108 | be zero.\r | |
| 2109 | @param DataValue 64-bit data value which is used to\r | |
| 2110 | initialize the cache line.\r | |
| 2111 | \r | |
| 2112 | @retval 0 Call completed without error\r | |
| 2113 | @retval -2 Invalid argument\r | |
| 2114 | @retval -3 Call completed with error.\r | |
| 2115 | \r | |
| 2116 | **/\r | |
| 2117 | #define PAL_CACHE_LINE_INIT 31\r | |
| 2118 | \r | |
| 2119 | /**\r | |
| 2120 | PAL Procedure - PAL_CACHE_READ.\r | |
| 2121 | \r | |
| 2122 | Read tag and data of a cache line for diagnostic testing. It\r | |
| 2123 | is optional. The PAL procedure supports the\r | |
| 2124 | Satcked Registers calling convention. It could be called at\r | |
| 2125 | physical mode.\r | |
| 2126 | \r | |
| 2127 | @param Index Index of PAL_CACHE_READ within the list of PAL\r | |
| 2128 | procedures.\r | |
| 2129 | @param LineId 8-byte formatted value describing where in the\r | |
| 2130 | cache to read the data.\r | |
| 2131 | @param Address 64-bit 8-byte aligned physical address from\r | |
| 2132 | which to read the data. The address must be an\r | |
| 2133 | implemented physical address on the processor\r | |
| 2134 | model with bit 63 set to zero.\r | |
| 2135 | \r | |
| 2136 | @retval 1 The word at address was found in the\r | |
| 2137 | cache, but the line was invalid.\r | |
| 2138 | @retval 0 Call completed without error\r | |
| 2139 | @retval -2 Invalid argument\r | |
| 2140 | @retval -3 Call completed with error.\r | |
| 2141 | @retval -5 The word at address was not found in the\r | |
| 2142 | cache.\r | |
| 2143 | @retval -7 The operation requested is not supported\r | |
| 2144 | for this cache_type and level.\r | |
| 2145 | \r | |
| 2146 | @return R9 Right-justified value returned from the cache\r | |
| 2147 | line.\r | |
| 2148 | @return R10 The number of bits returned in data.\r | |
| 2149 | @return R11 The status of the cache line.\r | |
| 2150 | \r | |
| 2151 | **/\r | |
| 2152 | #define PAL_CACHE_READ 259\r | |
| 2153 | \r | |
| 2154 | \r | |
| 2155 | /**\r | |
| 2156 | PAL Procedure - PAL_CACHE_WRITE.\r | |
| 2157 | \r | |
| 2158 | Write tag and data of a cache for diagnostic testing. It is\r | |
| 2159 | optional. The PAL procedure supports the Satcked Registers\r | |
| 2160 | calling convention. It could be called at physical mode.\r | |
| 2161 | \r | |
| 2162 | @param Index Index of PAL_CACHE_WRITE within the list of PAL\r | |
| 2163 | procedures.\r | |
| 2164 | @param LineId 8-byte formatted value describing where in the\r | |
| 2165 | cache to write the data.\r | |
| 2166 | @param Address 64-bit 8-byte aligned physical address at\r | |
| 2167 | which the data should be written. The address\r | |
| 2168 | must be an implemented physical address on the\r | |
| 2169 | processor model with bit 63 set to 0.\r | |
| 2170 | @param Data Unsigned 64-bit integer value to write into\r | |
| 2171 | the specified part of the cache.\r | |
| 2172 | \r | |
| 2173 | @retval 0 Call completed without error\r | |
| 2174 | @retval -2 Invalid argument\r | |
| 2175 | @retval -3 Call completed with error.\r | |
| 2176 | @retval -7 The operation requested is not supported\r | |
| 2177 | for this cache_type and level.\r | |
| 2178 | \r | |
| 2179 | **/\r | |
| 2180 | #define PAL_CACHE_WRITE 260\r | |
| 2181 | \r | |
| 2182 | /**\r | |
| 2183 | PAL Procedure - PAL_TEST_INFO.\r | |
| 2184 | \r | |
| 2185 | Returns alignment and size requirements needed for the memory\r | |
| 2186 | buffer passed to the PAL_TEST_PROC procedure as well as\r | |
| 2187 | information on self-test control words for the processor self\r | |
| 1a2f870c | 2188 | tests. It is required by Itanium processors. The PAL procedure supports the\r |
| a7b64584 | 2189 | Static Registers calling convention. It could be called at\r |
| 2190 | physical mode.\r | |
| 2191 | \r | |
| 2192 | @param Index Index of PAL_TEST_INFO within the list of PAL\r | |
| 2193 | procedures.\r | |
| 2194 | @param TestPhase Unsigned integer that specifies which phase\r | |
| 2195 | of the processor self-test information is\r | |
| 2196 | being requested on. A value of 0 indicates\r | |
| 2197 | the phase two of the processor self-test and\r | |
| 2198 | a value of 1 indicates phase one of the\r | |
| 2199 | processor self-test. All other values are\r | |
| 2200 | reserved.\r | |
| 2201 | \r | |
| 2202 | @retval 0 Call completed without error\r | |
| 2203 | @retval -2 Invalid argument\r | |
| 2204 | @retval -3 Call completed with error.\r | |
| 2205 | \r | |
| 2206 | @return R9 Unsigned 64-bit integer denoting the number of\r | |
| 2207 | bytes of main memory needed to perform the second\r | |
| 2208 | phase of processor self-test.\r | |
| 2209 | @return R10 Unsigned 64-bit integer denoting the alignment\r | |
| 2210 | required for the memory buffer.\r | |
| 2211 | @return R11 48-bit wide bit-field indicating if control of\r | |
| 2212 | the processor self-tests is supported and which\r | |
| 2213 | bits of the test_control field are defined for\r | |
| 2214 | use.\r | |
| 2215 | \r | |
| 2216 | **/\r | |
| 2217 | #define PAL_TEST_INFO 37\r | |
| 2218 | \r | |
| a7b64584 | 2219 | typedef struct {\r |
| 992f22b9 LG |
2220 | UINT64 BufferSize:56; ///< Indicates the size in bytes of the memory\r |
| 2221 | ///< buffer that is passed to this procedure.\r | |
| 2222 | ///< BufferSize must be greater than or equal in\r | |
| 2223 | ///< size to the bytes_needed return value from\r | |
| 2224 | ///< PAL_TEST_INFO, otherwise this procedure will\r | |
| 2225 | ///< return with an invalid argument return\r | |
| 2226 | ///< value.\r | |
| 2227 | \r | |
| 2228 | UINT64 TestPhase:8; ///< Defines which phase of the processor\r | |
| 2229 | ///< self-tests are requested to be run. A value\r | |
| 2230 | ///< of zero indicates to run phase two of the\r | |
| 2231 | ///< processor self-tests. Phase two of the\r | |
| 2232 | ///< processor self-tests are ones that require\r | |
| 2233 | ///< external memory to execute correctly. A\r | |
| 2234 | ///< value of one indicates to run phase one of\r | |
| 2235 | ///< the processor self-tests. Phase one of the\r | |
| 2236 | ///< processor self-tests are tests run during\r | |
| 2237 | ///< PALE_RESET and do not depend on external\r | |
| 2238 | ///< memory to run correctly. When the caller\r | |
| 2239 | ///< requests to have phase one of the processor\r | |
| 2240 | ///< self-test run via this procedure call, a\r | |
| 2241 | ///< memory buffer may be needed to save and\r | |
| 2242 | ///< restore state as required by the PAL calling\r | |
| 2243 | ///< conventions. The procedure PAL_TEST_INFO\r | |
| 2244 | ///< informs the caller about the requirements of\r | |
| 2245 | ///< the memory buffer.\r | |
| a7b64584 | 2246 | } PAL_TEST_INFO_INFO;\r |
| 2247 | \r | |
| a7b64584 | 2248 | typedef struct {\r |
| 992f22b9 LG |
2249 | UINT64 TestControl:47; ///< This is an ordered implementation-specific\r |
| 2250 | ///< control word that allows the user control\r | |
| 2251 | ///< over the length and runtime of the\r | |
| 2252 | ///< processor self-tests. This control word is\r | |
| 2253 | ///< ordered from the longest running tests up\r | |
| 2254 | ///< to the shortest running tests with bit 0\r | |
| 2255 | ///< controlling the longest running test. PAL\r | |
| 2256 | ///< may not implement all 47-bits of the\r | |
| 2257 | ///< test_control word. PAL communicates if a\r | |
| 2258 | ///< bit provides control by placing a zero in\r | |
| 2259 | ///< that bit. If a bit provides no control,\r | |
| 2260 | ///< PAL will place a one in it. PAL will have\r | |
| 2261 | ///< two sets of test_control bits for the two\r | |
| 2262 | ///< phases of the processor self-test. PAL\r | |
| 2263 | ///< provides information about implemented\r | |
| 2264 | ///< test_control bits at the hand-off from PAL\r | |
| 2265 | ///< to SAL for the firmware recovery check.\r | |
| 2266 | ///< These test_control bits provide control\r | |
| 2267 | ///< for phase one of processor self-test. It\r | |
| 2268 | ///< also provides this information via the PAL\r | |
| 2269 | ///< procedure call PAL_TEST_INFO for both the\r | |
| 2270 | ///< phase one and phase two processor tests\r | |
| 2271 | ///< depending on which information the caller\r | |
| 2272 | ///< is requesting. PAL interprets these bits\r | |
| 2273 | ///< as input parameters on two occasions. The\r | |
| 2274 | ///< first time is when SAL passes control back\r | |
| 2275 | ///< to PAL after the firmware recovery check.\r | |
| 2276 | ///< The second time is when a call to\r | |
| 2277 | ///< PAL_TEST_PROC is made. When PAL interprets\r | |
| 2278 | ///< these bits it will only interpret\r | |
| 2279 | ///< implemented test_control bits and will\r | |
| 2280 | ///< ignore the values located in the\r | |
| 2281 | ///< unimplemented test_control bits. PAL\r | |
| 2282 | ///< interprets the implemented bits such that\r | |
| 2283 | ///< if a bit contains a zero, this indicates\r | |
| 2284 | ///< to run the test. If a bit contains a one,\r | |
| 2285 | ///< this indicates to PAL to skip the test. If\r | |
| 2286 | ///< the cs bit indicates that control is not\r | |
| 2287 | ///< available, the test_control bits will be\r | |
| 2288 | ///< ignored or generate an illegal argument in\r | |
| 2289 | ///< procedure calls if the caller sets these\r | |
| 2290 | ///< bits.\r | |
| 7e6a7a63 | 2291 | \r |
| 992f22b9 LG |
2292 | UINT64 ControlSupport:1; ///< This bit defines if an implementation\r |
| 2293 | ///< supports control of the PAL self-tests\r | |
| 2294 | ///< via the self-test control word. If\r | |
| 2295 | ///< this bit is 0, the implementation does\r | |
| 2296 | ///< not support control of the processor\r | |
| 2297 | ///< self-tests via the self-test control\r | |
| 2298 | ///< word. If this bit is 1, the\r | |
| 2299 | ///< implementation does support control of\r | |
| 2300 | ///< the processor self-tests via the\r | |
| 2301 | ///< self-test control word. If control is\r | |
| 2302 | ///< not supported, GR37 will be ignored at\r | |
| 2303 | ///< the hand-off between SAL and PAL after\r | |
| 2304 | ///< the firmware recovery check and the\r | |
| 2305 | ///< PAL procedures related to the\r | |
| 2306 | ///< processor self-tests may return\r | |
| 2307 | ///< illegal arguments if a user tries to\r | |
| 2308 | ///< use the self-test control features.\r | |
| a7b64584 | 2309 | UINT64 Reserved:16;\r |
| 2310 | } PAL_SELF_TEST_CONTROL;\r | |
| 2311 | \r | |
| a7b64584 | 2312 | typedef struct {\r |
| 992f22b9 LG |
2313 | UINT64 Attributes:8; ///< Specifies the memory attributes that are\r |
| 2314 | ///< allowed to be used with the memory buffer\r | |
| 2315 | ///< passed to this procedure. The attributes\r | |
| 2316 | ///< parameter is a vector where each bit\r | |
| 2317 | ///< represents one of the virtual memory\r | |
| 2318 | ///< attributes defined by the architecture.See\r | |
| 2319 | ///< MEMORY_AATRIBUTES. The caller is required\r | |
| 2320 | ///< to support the cacheable attribute for the\r | |
| 2321 | ///< memory buffer, otherwise an invalid\r | |
| 2322 | ///< argument will be returned.\r | |
| a7b64584 | 2323 | UINT64 Reserved:8;\r |
| 992f22b9 LG |
2324 | UINT64 TestControl:48; ///< Is the self-test control word\r |
| 2325 | ///< corresponding to the test_phase passed.\r | |
| 2326 | ///< This test_control directs the coverage and\r | |
| 2327 | ///< runtime of the processor self-tests\r | |
| 2328 | ///< specified by the test_phase input\r | |
| 2329 | ///< argument. Information on if this\r | |
| 2330 | ///< feature is implemented and the number of\r | |
| 2331 | ///< bits supported can be obtained by the\r | |
| 2332 | ///< PAL_TEST_INFO procedure call. If this\r | |
| 2333 | ///< feature is implemented by the processor,\r | |
| 2334 | ///< the caller can selectively skip parts of\r | |
| 2335 | ///< the processor self-test by setting\r | |
| 2336 | ///< test_control bits to a one. If a bit has a\r | |
| 2337 | ///< zero, this test will be run. The values in\r | |
| 2338 | ///< the unimplemented bits are ignored. If\r | |
| 2339 | ///< PAL_TEST_INFO indicated that the self-test\r | |
| 2340 | ///< control word is not implemented, this\r | |
| 2341 | ///< procedure will return with an invalid\r | |
| 2342 | ///< argument status if the caller sets any of\r | |
| 2343 | ///< the test_control bits. See\r | |
| 2344 | ///< PAL_SELF_TEST_CONTROL.\r | |
| a7b64584 | 2345 | } PAL_TEST_CONTROL;\r |
| 2346 | \r | |
| 2347 | /**\r | |
| 2348 | PAL Procedure - PAL_TEST_PROC.\r | |
| 2349 | \r | |
| 1a2f870c | 2350 | Perform late processor self test. It is required by Itanium processors. The\r |
| a7b64584 | 2351 | PAL procedure supports the Static Registers calling\r |
| 2352 | convention. It could be called at physical mode.\r | |
| 2353 | \r | |
| 2354 | @param Index Index of PAL_TEST_PROC within the list of PAL\r | |
| 2355 | procedures.\r | |
| 2356 | @param TestAddress 64-bit physical address of main memory\r | |
| 2357 | area to be used by processor self-test.\r | |
| 2358 | The memory region passed must be\r | |
| 2359 | cacheable, bit 63 must be zero.\r | |
| 2360 | @param TestInfo Input argument specifying the size of the\r | |
| 2361 | memory buffer passed and the phase of the\r | |
| 2362 | processor self-test that should be run. See\r | |
| 2363 | PAL_TEST_INFO.\r | |
| 2364 | @param TestParam Input argument specifying the self-test\r | |
| 2365 | control word and the allowable memory\r | |
| 2366 | attributes that can be used with the memory\r | |
| 2367 | buffer. See PAL_TEST_CONTROL.\r | |
| 2368 | \r | |
| 2369 | @retval 1 Call completed without error, but hardware\r | |
| 2370 | failures occurred during self-test.\r | |
| 2371 | @retval 0 Call completed without error\r | |
| 2372 | @retval -2 Invalid argument\r | |
| 2373 | @retval -3 Call completed with error.\r | |
| 2374 | \r | |
| 2375 | @return R9 Formatted 8-byte value denoting the state of the\r | |
| 2376 | processor after self-test\r | |
| 2377 | \r | |
| 2378 | **/\r | |
| 2379 | #define PAL_TEST_PROC 258\r | |
| 2380 | \r | |
| a7b64584 | 2381 | typedef struct {\r |
| 992f22b9 LG |
2382 | UINT32 NumberOfInterruptControllers; ///< Number of interrupt\r |
| 2383 | ///< controllers currently\r | |
| 2384 | ///< enabled on the system.\r | |
| 7e6a7a63 | 2385 | \r |
| 992f22b9 LG |
2386 | UINT32 NumberOfProcessors; ///< Number of processors currently\r |
| 2387 | ///< enabled on the system.\r | |
| a7b64584 | 2388 | } PAL_PLATFORM_INFO;\r |
| 2389 | \r | |
| 2390 | /**\r | |
| 2391 | PAL Procedure - PAL_COPY_INFO.\r | |
| 2392 | \r | |
| 2393 | Return information needed to relocate PAL procedures and PAL\r | |
| 1a2f870c | 2394 | PMI code to memory. It is required by Itanium processors. The PAL procedure\r |
| a7b64584 | 2395 | supports the Static Registers calling convention. It could be\r |
| 2396 | called at physical mode.\r | |
| 2397 | \r | |
| 2398 | @param Index Index of PAL_COPY_INFO within the list of PAL\r | |
| 2399 | procedures.\r | |
| 2400 | @param CopyType Unsigned integer denoting type of procedures\r | |
| 2401 | for which copy information is requested.\r | |
| 2402 | @param PlatformInfo 8-byte formatted value describing the\r | |
| 2403 | number of processors and the number of\r | |
| 2404 | interrupt controllers currently enabled\r | |
| 2405 | on the system. See PAL_PLATFORM_INFO.\r | |
| 2406 | @param McaProcStateInfo Unsigned integer denoting the number\r | |
| 2407 | of bytes that SAL needs for the\r | |
| 2408 | min-state save area for each\r | |
| 2409 | processor.\r | |
| 2410 | \r | |
| 2411 | @retval 0 Call completed without error\r | |
| 2412 | @retval -2 Invalid argument\r | |
| 2413 | @retval -3 Call completed with error.\r | |
| 2414 | \r | |
| 2415 | @return R9 Unsigned integer denoting the number of bytes of\r | |
| 2416 | PAL information that must be copied to main\r | |
| 2417 | memory.\r | |
| 2418 | @return R10 Unsigned integer denoting the starting alignment\r | |
| 2419 | of the data to be copied.\r | |
| 2420 | \r | |
| 2421 | **/\r | |
| 2422 | #define PAL_COPY_INFO 30\r | |
| 2423 | \r | |
| 2424 | /**\r | |
| 2425 | PAL Procedure - PAL_COPY_PAL.\r | |
| 2426 | \r | |
| 2427 | Relocate PAL procedures and PAL PMI code to memory. It is\r | |
| 1a2f870c | 2428 | required by Itanium processors. The PAL procedure supports the Stacked\r |
| a7b64584 | 2429 | Registers calling convention. It could be called at physical\r |
| 2430 | mode.\r | |
| 2431 | \r | |
| 2432 | @param Index Index of PAL_COPY_PAL within the list of PAL\r | |
| 2433 | procedures.\r | |
| 2434 | @param TargetAddress Physical address of a memory buffer to\r | |
| 2435 | copy relocatable PAL procedures and PAL\r | |
| 2436 | PMI code.\r | |
| 2437 | @param AllocSize Unsigned integer denoting the size of the\r | |
| 2438 | buffer passed by SAL for the copy operation.\r | |
| 2439 | @param CopyOption Unsigned integer indicating whether\r | |
| 2440 | relocatable PAL code and PAL PMI code\r | |
| 2441 | should be copied from firmware address\r | |
| 2442 | space to main memory.\r | |
| 2443 | \r | |
| 2444 | @retval 0 Call completed without error\r | |
| 2445 | @retval -2 Invalid argument\r | |
| 2446 | @retval -3 Call completed with error.\r | |
| 2447 | \r | |
| 2448 | @return R9 Unsigned integer denoting the offset of PAL_PROC\r | |
| 2449 | in the relocatable segment copied.\r | |
| 2450 | \r | |
| 2451 | **/\r | |
| 2452 | #define PAL_COPY_PAL 256\r | |
| 2453 | \r | |
| 2454 | /**\r | |
| 2455 | PAL Procedure - PAL_ENTER_IA_32_ENV.\r | |
| 2456 | \r | |
| 2457 | Enter IA-32 System environment. It is optional. The PAL\r | |
| 2458 | procedure supports the Static Registers calling convention.\r | |
| 2459 | It could be called at physical mode.\r | |
| 2460 | \r | |
| 2461 | Note: Since this is a special call, it does not follow the PAL\r | |
| 2462 | static register calling convention. GR28 contains the index of\r | |
| 2463 | PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other\r | |
| 2464 | input arguments including GR29-GR31 are setup by SAL to values\r | |
| 2465 | as required by the IA-32 operating system defined in Table\r | |
| 2466 | 11-67. The registers that are designated as preserved, scratch,\r | |
| 2467 | input arguments and procedure return values by the static\r | |
| 2468 | procedure calling convention are not followed by this call. For\r | |
| 2469 | instance, GR5 and GR6 need not be preserved since these are\r | |
| 2470 | regarded as scratch by the IA-32 operating system. Note: In an\r | |
| 2471 | MP system, this call must be COMPLETED on the first CPU to enter\r | |
| 2472 | the IA-32 System Environment (may or may not be the BSP) prior\r | |
| 2473 | to being called on the remaining processors in the MP system.\r | |
| 2474 | \r | |
| 2475 | @param Index GR28 contains the index of the\r | |
| 2476 | PAL_ENTER_IA_32_ENV call within the list of PAL\r | |
| 2477 | procedures.\r | |
| 2478 | \r | |
| 2479 | \r | |
| 2480 | @retval The status is returned in GR4.\r | |
| 2481 | -1 - Un-implemented procedure 0 JMPE detected\r | |
| 2482 | at privilege level\r | |
| 2483 | \r | |
| 2484 | 0 - 1 SAL allocated buffer for IA-32 System\r | |
| 2485 | Environment operation is too small\r | |
| 2486 | \r | |
| 2487 | 2 - IA-32 Firmware Checksum Error\r | |
| 2488 | \r | |
| 2489 | 3 - SAL allocated buffer for IA-32 System\r | |
| 2490 | Environment operation is not properly aligned\r | |
| 2491 | \r | |
| 2492 | 4 - Error in SAL MP Info Table\r | |
| 2493 | \r | |
| 2494 | 5 - Error in SAL Memory Descriptor Table\r | |
| 2495 | \r | |
| 2496 | 6 - Error in SAL System Table\r | |
| 2497 | \r | |
| 2498 | 7 - Inconsistent IA-32 state\r | |
| 2499 | \r | |
| 2500 | 8 - IA-32 Firmware Internal Error\r | |
| 2501 | \r | |
| 2502 | 9 - IA-32 Soft Reset (Note: remaining register\r | |
| 2503 | state is undefined for this termination\r | |
| 2504 | reason)\r | |
| 2505 | \r | |
| 2506 | 10 - Machine Check Error\r | |
| 2507 | \r | |
| 2508 | 11 - Error in SAL I/O Intercept Table\r | |
| 2509 | \r | |
| 2510 | 12 - Processor exit due to other processor in\r | |
| 2511 | MP system terminating the IA32 system\r | |
| 2512 | environment. (Note: remaining register state\r | |
| 2513 | is undefined for this termination reason.)\r | |
| 2514 | \r | |
| 2515 | 13 - Itanium architecture-based state\r | |
| 2516 | corruption by either SAL PMI handler or I/O\r | |
| 2517 | Intercept callback function.\r | |
| 2518 | \r | |
| 2519 | \r | |
| 2520 | **/\r | |
| 2521 | #define PAL_ENTER_IA_32_ENV 33\r | |
| 2522 | \r | |
| 2523 | /**\r | |
| 2524 | PAL Procedure - PAL_PMI_ENTRYPOINT.\r | |
| 2525 | \r | |
| 2526 | Register PMI memory entrypoints with processor. It is required\r | |
| 1a2f870c | 2527 | by Itanium processors. The PAL procedure supports the Stacked Registers\r |
| a7b64584 | 2528 | calling convention. It could be called at physical mode.\r |
| 2529 | \r | |
| 2530 | @param Index Index of PAL_PMI_ENTRYPOINT within the list of\r | |
| 2531 | PAL procedures.\r | |
| 2532 | @param SalPmiEntry 256-byte aligned physical address of SAL\r | |
| 2533 | PMI entrypoint in memory.\r | |
| 2534 | \r | |
| 2535 | @retval 0 Call completed without error\r | |
| 2536 | @retval -2 Invalid argument\r | |
| 2537 | @retval -3 Call completed with error.\r | |
| 2538 | \r | |
| 2539 | **/\r | |
| 2540 | #define PAL_PMI_ENTRYPOINT 32\r | |
| 2541 | \r | |
| 2542 | \r | |
| 2543 | /**\r | |
| 2544 | \r | |
| 2545 | The ASCII brand identification string will be copied to the\r | |
| 2546 | address specified in the address input argument. The processor\r | |
| 2547 | brand identification string is defined to be a maximum of 128\r | |
| 2548 | characters long; 127 bytes will contain characters and the 128th\r | |
| 2549 | byte is defined to be NULL (0). A processor may return less than\r | |
| 2550 | the 127 ASCII characters as long as the string is null\r | |
| 2551 | terminated. The string length will be placed in the brand_info\r | |
| 2552 | return argument.\r | |
| 2553 | \r | |
| 2554 | **/\r | |
| 2555 | #define PAL_BRAND_INFO_ID_REQUEST 0\r | |
| 2556 | \r | |
| 2557 | /**\r | |
| 2558 | PAL Procedure - PAL_BRAND_INFO.\r | |
| 2559 | \r | |
| 2560 | Provides processor branding information. It is optional by\r | |
| 1a2f870c | 2561 | Itanium processors. The PAL procedure supports the Stacked Registers calling\r |
| a7b64584 | 2562 | convention. It could be called at physical and Virtual mode.\r |
| 2563 | \r | |
| 2564 | @param Index Index of PAL_BRAND_INFO within the list of PAL\r | |
| 2565 | procedures.\r | |
| 2566 | @param InfoRequest Unsigned 64-bit integer specifying the\r | |
| 2567 | information that is being requested. (See\r | |
| 2568 | PAL_BRAND_INFO_ID_REQUEST)\r | |
| 2569 | @param Address Unsigned 64-bit integer specifying the\r | |
| 2570 | address of the 128-byte block to which the\r | |
| 2571 | processor brand string shall be written.\r | |
| 2572 | \r | |
| 2573 | @retval 0 Call completed without error\r | |
| 2574 | @retval -1 Unimplemented procedure\r | |
| 2575 | @retval -2 Invalid argument\r | |
| 2576 | @retval -3 Call completed with error.\r | |
| 2577 | @retval -6 Input argument is not implemented.\r | |
| 2578 | \r | |
| 2579 | @return R9 Brand information returned. The format of this\r | |
| 2580 | value is dependent on the input values passed.\r | |
| 2581 | \r | |
| 2582 | **/\r | |
| 2583 | #define PAL_BRAND_INFO 274\r | |
| 2584 | \r | |
| 2585 | /**\r | |
| 2586 | PAL Procedure - PAL_GET_HW_POLICY.\r | |
| 2587 | \r | |
| 2588 | Returns the current hardware resource sharing policy of the\r | |
| 1a2f870c | 2589 | processor. It is optional by Itanium processors. The PAL procedure supports\r |
| a7b64584 | 2590 | the Static Registers calling convention. It could be called at\r |
| 2591 | physical and Virtual mode.\r | |
| 2592 | \r | |
| 2593 | \r | |
| 2594 | @param Index Index of PAL_GET_HW_POLICY within the list of PAL\r | |
| 2595 | procedures.\r | |
| 2596 | @param ProcessorNumber Unsigned 64-bit integer that specifies\r | |
| 2597 | for which logical processor\r | |
| 2598 | information is being requested. This\r | |
| 2599 | input argument must be zero for the\r | |
| 2600 | first call to this procedure and can\r | |
| 2601 | be a maximum value of one less than\r | |
| 2602 | the number of logical processors\r | |
| 2603 | impacted by the hardware resource\r | |
| 2604 | sharing policy, which is returned by\r | |
| 2605 | the R10 return value.\r | |
| 2606 | \r | |
| 2607 | @retval 0 Call completed without error\r | |
| 2608 | @retval -1 Unimplemented procedure\r | |
| 2609 | @retval -2 Invalid argument\r | |
| 2610 | @retval -3 Call completed with error.\r | |
| 2611 | @retval -9 Call requires PAL memory buffer.\r | |
| 2612 | \r | |
| 2613 | @return R9 Unsigned 64-bit integer representing the current\r | |
| 2614 | hardware resource sharing policy.\r | |
| 2615 | @return R10 Unsigned 64-bit integer that returns the number\r | |
| 2616 | of logical processors impacted by the policy\r | |
| 2617 | input argument.\r | |
| 2618 | @return R11 Unsigned 64-bit integer containing the logical\r | |
| 2619 | address of one of the logical processors\r | |
| 2620 | impacted by policy modification.\r | |
| 2621 | \r | |
| 2622 | **/\r | |
| 2623 | #define PAL_GET_HW_POLICY 48\r | |
| 2624 | \r | |
| 2625 | \r | |
| 2626 | //\r | |
| 2627 | // Value of PAL_SET_HW_POLICY.Policy\r | |
| 2628 | //\r | |
| 2629 | #define PAL_SET_HW_POLICY_PERFORMANCE 0\r | |
| 2630 | #define PAL_SET_HW_POLICY_FAIRNESS 1\r | |
| 2631 | #define PAL_SET_HW_POLICY_HIGH_PRIORITY 2\r | |
| 2632 | #define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3\r | |
| 2633 | \r | |
| 2634 | /**\r | |
| 2635 | PAL Procedure - PAL_SET_HW_POLICY.\r | |
| 2636 | \r | |
| 2637 | Sets the current hardware resource sharing policy of the\r | |
| 1a2f870c | 2638 | processor. It is optional by Itanium processors. The PAL procedure supports\r |
| a7b64584 | 2639 | the Static Registers calling convention. It could be called at\r |
| 2640 | physical and Virtual mode.\r | |
| 2641 | \r | |
| 2642 | @param Index Index of PAL_SET_HW_POLICY within the list of PAL\r | |
| 2643 | procedures.\r | |
| 2644 | @param Policy Unsigned 64-bit integer specifying the hardware\r | |
| 2645 | resource sharing policy the caller is setting.\r | |
| 2646 | See Value of PAL_SET_HW_POLICY.Policy above.\r | |
| 2647 | \r | |
| 2648 | @retval 1 Call completed successfully but could not\r | |
| 2649 | change the hardware policy since a\r | |
| 2650 | competing logical processor is set in\r | |
| 2651 | exclusive high priority.\r | |
| 2652 | @retval 0 Call completed without error\r | |
| 2653 | @retval -1 Unimplemented procedure\r | |
| 2654 | @retval -2 Invalid argument\r | |
| 2655 | @retval -3 Call completed with error.\r | |
| 2656 | @retval -9 Call requires PAL memory buffer.\r | |
| 2657 | \r | |
| 2658 | **/\r | |
| 2659 | #define PAL_SET_HW_POLICY 49\r | |
| 2660 | \r | |
| a7b64584 | 2661 | typedef struct {\r |
| 992f22b9 LG |
2662 | UINT64 Mode:3; ///< Bit2:0, Indicates the mode of operation for this\r |
| 2663 | ///< procedure: 0 - Query mode 1 - Error inject mode\r | |
| 2664 | ///< (err_inj should also be specified) 2 - Cancel\r | |
| 2665 | ///< outstanding trigger. All other fields in\r | |
| 2666 | ///< PAL_MC_ERROR_TYPE_INFO,\r | |
| 2667 | ///< PAL_MC_ERROR_STRUCTURE_INFO and\r | |
| 2668 | ///< PAL_MC_ERROR_DATA_BUFFER are ignored. All other\r | |
| 2669 | ///< values are reserved.\r | |
| 2670 | \r | |
| 2671 | UINT64 ErrorInjection:3; ///< Bit5:3, indicates the mode of error\r | |
| 2672 | ///< injection: 0 - Error inject only (no\r | |
| 2673 | ///< error consumption) 1 - Error inject\r | |
| 2674 | ///< and consume All other values are\r | |
| 2675 | ///< reserved.\r | |
| 2676 | \r | |
| 2677 | UINT64 ErrorSeverity:2; ///< Bit7:6, indicates the severity desired\r | |
| 2678 | ///< for error injection/query. Definitions\r | |
| 2679 | ///< of the different error severity types\r | |
| 2680 | ///< 0 - Corrected error 1 - Recoverable\r | |
| 2681 | ///< error 2 - Fatal error 3 - Reserved\r | |
| 2682 | \r | |
| 2683 | UINT64 ErrorStructure:5; ///< Bit12:8, Indicates the structure\r | |
| 2684 | ///< identification for error\r | |
| 2685 | ///< injection/query: 0 - Any structure\r | |
| 2686 | ///< (cannot be used during query mode).\r | |
| 2687 | ///< When selected, the structure type used\r | |
| 2688 | ///< for error injection is determined by\r | |
| 2689 | ///< PAL. 1 - Cache 2 - TLB 3 - Register\r | |
| 2690 | ///< file 4 - Bus/System interconnect 5-15\r | |
| 2691 | ///< - Reserved 16-31 - Processor\r | |
| 2692 | ///< specific error injection\r | |
| 2693 | ///< capabilities.ErrorDataBuffer is used\r | |
| 2694 | ///< to specify error types. Please refer\r | |
| 2695 | ///< to the processor specific\r | |
| 2696 | ///< documentation for additional details.\r | |
| 2697 | \r | |
| 2698 | UINT64 StructureHierarchy:3; ///< Bit15:13, Indicates the structure\r | |
| 2699 | ///< hierarchy for error\r | |
| 2700 | ///< injection/query: 0 - Any level of\r | |
| 2701 | ///< hierarchy (cannot be used during\r | |
| 2702 | ///< query mode). When selected, the\r | |
| 2703 | ///< structure hierarchy used for error\r | |
| 2704 | ///< injection is determined by PAL. 1\r | |
| 2705 | ///< - Error structure hierarchy\r | |
| 2706 | ///< level-1 2 - Error structure\r | |
| 2707 | ///< hierarchy level-2 3 - Error\r | |
| 2708 | ///< structure hierarchy level-3 4 -\r | |
| 2709 | ///< Error structure hierarchy level-4\r | |
| 2710 | ///< All other values are reserved.\r | |
| 7e6a7a63 | 2711 | \r |
| e2a5ae07 | 2712 | UINT64 Reserved:32; ///< Reserved 47:16 Reserved\r |
| 2713 | \r | |
| 2714 | UINT64 ImplSpec:16; ///< Bit63:48, Processor specific error injection capabilities.\r | |
| a7b64584 | 2715 | } PAL_MC_ERROR_TYPE_INFO;\r |
| 2716 | \r | |
| 7e6a7a63 | 2717 | typedef struct {\r |
| 992f22b9 LG |
2718 | UINT64 StructInfoIsValid:1; ///< Bit0 When 1, indicates that the\r |
| 2719 | ///< structure information fields\r | |
| 2720 | ///< (c_t,cl_p,cl_id) are valid and\r | |
| 2721 | ///< should be used for error injection.\r | |
| 2722 | ///< When 0, the structure information\r | |
| 2723 | ///< fields are ignored, and the values\r | |
| 2724 | ///< of these fields used for error\r | |
| 2725 | ///< injection are\r | |
| 2726 | ///< implementation-specific.\r | |
| 2727 | \r | |
| 2728 | UINT64 CacheType:2; ///< Bit2:1 Indicates which cache should be used\r | |
| 2729 | ///< for error injection: 0 - Reserved 1 -\r | |
| 2730 | ///< Instruction cache 2 - Data or unified cache\r | |
| 2731 | ///< 3 - Reserved\r | |
| 2732 | \r | |
| 2733 | UINT64 PortionOfCacheLine:3; ///< Bit5:3 Indicates the portion of the\r | |
| 2734 | ///< cache line where the error should\r | |
| 2735 | ///< be injected: 0 - Reserved 1 - Tag\r | |
| 2736 | ///< 2 - Data 3 - mesi All other\r | |
| 2737 | ///< values are reserved.\r | |
| 2738 | \r | |
| 2739 | UINT64 Mechanism:3; ///< Bit8:6 Indicates which mechanism is used to\r | |
| 2740 | ///< identify the cache line to be used for error\r | |
| 2741 | ///< injection: 0 - Reserved 1 - Virtual address\r | |
| 2742 | ///< provided in the inj_addr field of the buffer\r | |
| 2743 | ///< pointed to by err_data_buffer should be used\r | |
| 2744 | ///< to identify the cache line for error\r | |
| 2745 | ///< injection. 2 - Physical address provided in\r | |
| 2746 | ///< the inj_addr field of the buffer pointed to\r | |
| 2747 | ///< by err_data_buffershould be used to identify\r | |
| 2748 | ///< the cache line for error injection. 3 - way\r | |
| 2749 | ///< and index fields provided in err_data_buffer\r | |
| 2750 | ///< should be used to identify the cache line\r | |
| 2751 | ///< for error injection. All other values are\r | |
| 2752 | ///< reserved.\r | |
| 2753 | \r | |
| 2754 | UINT64 DataPoisonOfCacheLine:1; ///< Bit9 When 1, indicates that a\r | |
| 2755 | ///< multiple bit, non-correctable\r | |
| 2756 | ///< error should be injected in the\r | |
| 2757 | ///< cache line specified by cl_id.\r | |
| 2758 | ///< If this injected error is not\r | |
| 2759 | ///< consumed, it may eventually\r | |
| 2760 | ///< cause a data-poisoning event\r | |
| 2761 | ///< resulting in a corrected error\r | |
| 2762 | ///< signal, when the associated\r | |
| 2763 | ///< cache line is cast out (implicit\r | |
| 2764 | ///< or explicit write-back of the\r | |
| 2765 | ///< cache line). The error severity\r | |
| 2766 | ///< specified by err_sev in\r | |
| 2767 | ///< err_type_info must be set to 0\r | |
| 2768 | ///< (corrected error) when this bit\r | |
| 2769 | ///< is set.\r | |
| a7b64584 | 2770 | \r |
| 7e6a7a63 | 2771 | UINT64 Reserved1:22;\r |
| a7b64584 | 2772 | \r |
| 992f22b9 LG |
2773 | UINT64 TrigerInfoIsValid:1; ///< Bit32 When 1, indicates that the\r |
| 2774 | ///< trigger information fields (trigger,\r | |
| 2775 | ///< trigger_pl) are valid and should be\r | |
| 2776 | ///< used for error injection. When 0,\r | |
| 2777 | ///< the trigger information fields are\r | |
| 2778 | ///< ignored and error injection is\r | |
| 2779 | ///< performed immediately.\r | |
| 2780 | \r | |
| 2781 | UINT64 Triger:4; ///< Bit36:33 Indicates the operation type to be\r | |
| 2782 | ///< used as the error trigger condition. The\r | |
| 2783 | ///< address corresponding to the trigger is\r | |
| 2784 | ///< specified in the trigger_addr field of the\r | |
| 2785 | ///< buffer pointed to by err_data_buffer: 0 -\r | |
| 2786 | ///< Instruction memory access. The trigger match\r | |
| 2787 | ///< conditions for this operation type are similar\r | |
| 2788 | ///< to the IBR address breakpoint match conditions\r | |
| 2789 | ///< 1 - Data memory access. The trigger match\r | |
| 2790 | ///< conditions for this operation type are similar\r | |
| 2791 | ///< to the DBR address breakpoint match conditions\r | |
| 2792 | ///< All other values are reserved.\r | |
| 2793 | \r | |
| 2794 | UINT64 PrivilegeOfTriger:3; ///< Bit39:37 Indicates the privilege\r | |
| 2795 | ///< level of the context during which\r | |
| 2796 | ///< the error should be injected: 0 -\r | |
| 2797 | ///< privilege level 0 1 - privilege\r | |
| 2798 | ///< level 1 2 - privilege level 2 3 -\r | |
| 2799 | ///< privilege level 3 All other values\r | |
| 2800 | ///< are reserved. If the implementation\r | |
| 2801 | ///< does not support privilege level\r | |
| 2802 | ///< qualifier for triggers (i.e. if\r | |
| 2803 | ///< trigger_pl is 0 in the capabilities\r | |
| 2804 | ///< vector), this field is ignored and\r | |
| 2805 | ///< triggers can be taken at any\r | |
| 2806 | ///< privilege level.\r | |
| a7b64584 | 2807 | \r |
| a7b64584 | 2808 | UINT64 Reserved2:24;\r |
| 2809 | } PAL_MC_ERROR_STRUCT_INFO;\r | |
| 2810 | \r | |
| 2811 | /**\r | |
| 2812 | \r | |
| 2813 | Buffer Pointed to by err_data_buffer - TLB\r | |
| 2814 | \r | |
| 2815 | **/\r | |
| 2816 | typedef struct {\r | |
| 2817 | UINT64 TrigerAddress;\r | |
| 2818 | UINT64 VirtualPageNumber:52;\r | |
| 2819 | UINT64 Reserved1:8;\r | |
| 2820 | UINT64 RegionId:24;\r | |
| 2821 | UINT64 Reserved2:40;\r | |
| 2822 | } PAL_MC_ERROR_DATA_BUFFER_TLB;\r | |
| 2823 | \r | |
| 2824 | /**\r | |
| 2825 | PAL Procedure - PAL_MC_ERROR_INJECT.\r | |
| 2826 | \r | |
| 2827 | Injects the requested processor error or returns information\r | |
| 2828 | on the supported injection capabilities for this particular\r | |
| 1a2f870c | 2829 | processor implementation. It is optional by Itanium processors. The PAL\r |
| a7b64584 | 2830 | procedure supports the Stacked Registers calling convention.\r |
| 2831 | It could be called at physical and Virtual mode.\r | |
| 2832 | \r | |
| 2833 | @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL\r | |
| 2834 | procedures.\r | |
| 2835 | @param ErrorTypeInfo Unsigned 64-bit integer specifying the\r | |
| 2836 | first level error information which\r | |
| 2837 | identifies the error structure and\r | |
| 2838 | corresponding structure hierarchy, and\r | |
| 2839 | the error severity.\r | |
| 2840 | @param ErrorStructInfo Unsigned 64-bit integer identifying\r | |
| 2841 | the optional structure specific\r | |
| 2842 | information that provides the second\r | |
| 2843 | level details for the requested error.\r | |
| 2844 | @param ErrorDataBuffer 64-bit physical address of a buffer\r | |
| 2845 | providing additional parameters for\r | |
| 2846 | the requested error. The address of\r | |
| 2847 | this buffer must be 8-byte aligned.\r | |
| 2848 | \r | |
| 2849 | @retval 0 Call completed without error\r | |
| 2850 | @retval -1 Unimplemented procedure\r | |
| 2851 | @retval -2 Invalid argument\r | |
| 2852 | @retval -3 Call completed with error.\r | |
| 2853 | @retval -4 Call completed with error; the requested\r | |
| 2854 | error could not be injected due to failure in\r | |
| 2855 | locating the target location in the specified\r | |
| 2856 | structure.\r | |
| 2857 | @retval -5 Argument was valid, but requested error\r | |
| 2858 | injection capability is not supported.\r | |
| 2859 | @retval -9 Call requires PAL memory buffer.\r | |
| 2860 | \r | |
| 2861 | @return R9 64-bit vector specifying the supported error\r | |
| 2862 | injection capabilities for the input argument\r | |
| 2863 | combination of struct_hier, err_struct and\r | |
| 2864 | err_sev fields in ErrorTypeInfo.\r | |
| 2865 | @return R10 64-bit vector specifying the architectural\r | |
| 2866 | resources that are used by the procedure.\r | |
| 2867 | \r | |
| 2868 | **/\r | |
| 2869 | #define PAL_MC_ERROR_INJECT 276\r | |
| 2870 | \r | |
| 2871 | \r | |
| 2872 | //\r | |
| 2873 | // Types of PAL_GET_PSTATE.Type\r | |
| 2874 | //\r | |
| 2875 | #define PAL_GET_PSTATE_RECENT 0\r | |
| 2876 | #define PAL_GET_PSTATE_AVERAGE_NEW_START 1\r | |
| 2877 | #define PAL_GET_PSTATE_AVERAGE 2\r | |
| 2878 | #define PAL_GET_PSTATE_NOW 3\r | |
| 2879 | \r | |
| 2880 | /**\r | |
| 2881 | PAL Procedure - PAL_GET_PSTATE.\r | |
| 2882 | \r | |
| 2883 | Returns the performance index of the processor. It is optional\r | |
| 1a2f870c | 2884 | by Itanium processors. The PAL procedure supports the Stacked Registers\r |
| a7b64584 | 2885 | calling convention. It could be called at physical and Virtual\r |
| 2886 | mode.\r | |
| 2887 | \r | |
| 2888 | @param Index Index of PAL_GET_PSTATE within the list of PAL\r | |
| 2889 | procedures.\r | |
| 2890 | @param Type Type of performance_index value to be returned\r | |
| 2891 | by this procedure.See PAL_GET_PSTATE.Type above.\r | |
| 2892 | \r | |
| 2893 | @retval 1 Call completed without error, but accuracy\r | |
| 2894 | of performance index has been impacted by a\r | |
| 2895 | thermal throttling event, or a\r | |
| 2896 | hardware-initiated event.\r | |
| 2897 | @retval 0 Call completed without error\r | |
| 2898 | @retval -1 Unimplemented procedure\r | |
| 2899 | @retval -2 Invalid argument\r | |
| 2900 | @retval -3 Call completed with error.\r | |
| 2901 | @retval -9 Call requires PAL memory buffer.\r | |
| 2902 | \r | |
| 2903 | @return R9 Unsigned integer denoting the processor\r | |
| 2904 | performance for the time duration since the last\r | |
| 2905 | PAL_GET_PSTATE procedure call was made. The\r | |
| 2906 | value returned is between 0 and 100, and is\r | |
| 2907 | relative to the performance index of the highest\r | |
| 2908 | available P-state.\r | |
| 2909 | \r | |
| 2910 | **/\r | |
| 2911 | #define PAL_GET_PSTATE 262\r | |
| 2912 | \r | |
| 2913 | /**\r | |
| 2914 | \r | |
| 2915 | Layout of PAL_PSTATE_INFO.PStateBuffer\r | |
| 2916 | \r | |
| 2917 | **/\r | |
| 2918 | typedef struct {\r | |
| 2919 | UINT32 PerformanceIndex:7;\r | |
| 2920 | UINT32 Reserved1:5;\r | |
| 2921 | UINT32 TypicalPowerDissipation:20;\r | |
| 2922 | UINT32 TransitionLatency1;\r | |
| 2923 | UINT32 TransitionLatency2;\r | |
| 2924 | UINT32 Reserved2;\r | |
| 2925 | } PAL_PSTATE_INFO_BUFFER;\r | |
| 2926 | \r | |
| 2927 | \r | |
| 2928 | /**\r | |
| 2929 | PAL Procedure - PAL_PSTATE_INFO.\r | |
| 2930 | \r | |
| 2931 | Returns information about the P-states supported by the\r | |
| 1a2f870c | 2932 | processor. It is optional by Itanium processors. The PAL procedure supports\r |
| a7b64584 | 2933 | the Static Registers calling convention. It could be called\r |
| 2934 | at physical and Virtual mode.\r | |
| 2935 | \r | |
| 2936 | @param Index Index of PAL_PSTATE_INFO within the list of PAL\r | |
| 2937 | procedures.\r | |
| 2938 | @param PStateBuffer 64-bit pointer to a 256-byte buffer\r | |
| 2939 | aligned on an 8-byte boundary. See\r | |
| 2940 | PAL_PSTATE_INFO_BUFFER above.\r | |
| 2941 | \r | |
| 2942 | @retval 0 Call completed without error\r | |
| 2943 | @retval -1 Unimplemented procedure\r | |
| 2944 | @retval -2 Invalid argument\r | |
| 2945 | @retval -3 Call completed with error.\r | |
| 2946 | \r | |
| 2947 | @return R9 Unsigned integer denoting the number of P-states\r | |
| 2948 | supported. The maximum value of this field is 16.\r | |
| 2949 | @return R10 Dependency domain information\r | |
| 2950 | \r | |
| 2951 | **/\r | |
| 2952 | #define PAL_PSTATE_INFO 44\r | |
| 2953 | \r | |
| 2954 | \r | |
| 2955 | /**\r | |
| 2956 | PAL Procedure - PAL_SET_PSTATE.\r | |
| 2957 | \r | |
| 2958 | To request a processor transition to a given P-state. It is\r | |
| 1a2f870c | 2959 | optional by Itanium processors. The PAL procedure supports the Stacked\r |
| a7b64584 | 2960 | Registers calling convention. It could be called at physical\r |
| 2961 | and Virtual mode.\r | |
| 2962 | \r | |
| 2963 | @param Index Index of PAL_SET_PSTATE within the list of PAL\r | |
| 2964 | procedures.\r | |
| 2965 | @param PState Unsigned integer denoting the processor\r | |
| 2966 | P-state being requested.\r | |
| 2967 | @param ForcePState Unsigned integer denoting whether the\r | |
| 2968 | P-state change should be forced for the\r | |
| 2969 | logical processor.\r | |
| 2970 | \r | |
| 2971 | @retval 1 Call completed without error, but\r | |
| 2972 | transition request was not accepted\r | |
| 2973 | @retval 0 Call completed without error\r | |
| 2974 | @retval -1 Unimplemented procedure\r | |
| 2975 | @retval -2 Invalid argument\r | |
| 2976 | @retval -3 Call completed with error.\r | |
| 2977 | @retval -9 Call requires PAL memory buffer.\r | |
| 2978 | \r | |
| 2979 | **/\r | |
| 2980 | #define PAL_SET_PSTATE 263\r | |
| 2981 | \r | |
| 2982 | /**\r | |
| 2983 | PAL Procedure - PAL_SHUTDOWN.\r | |
| 2984 | \r | |
| 2985 | Put the logical processor into a low power state which can be\r | |
| 1a2f870c | 2986 | exited only by a reset event. It is optional by Itanium processors. The PAL\r |
| a7b64584 | 2987 | procedure supports the Static Registers calling convention. It\r |
| 2988 | could be called at physical mode.\r | |
| 2989 | \r | |
| 2990 | @param Index Index of PAL_SHUTDOWN within the list of PAL\r | |
| 2991 | procedures.\r | |
| 2992 | @param NotifyPlatform 8-byte aligned physical address\r | |
| 2993 | pointer providing details on how to\r | |
| 2994 | optionally notify the platform that\r | |
| 2995 | the processor is entering a shutdown\r | |
| 2996 | state.\r | |
| 2997 | \r | |
| 2998 | @retval -1 Unimplemented procedure\r | |
| 2999 | @retval -2 Invalid argument\r | |
| 3000 | @retval -3 Call completed with error.\r | |
| 3001 | @retval -9 Call requires PAL memory buffer.\r | |
| 3002 | \r | |
| 3003 | **/\r | |
| 3004 | #define PAL_SHUTDOWN 45\r | |
| 3005 | \r | |
| 3006 | /**\r | |
| 3007 | \r | |
| 3008 | Layout of PAL_MEMORY_BUFFER.ControlWord\r | |
| 3009 | \r | |
| 3010 | **/\r | |
| 3011 | typedef struct {\r | |
| 3012 | UINT64 Registration:1;\r | |
| 3013 | UINT64 ProbeInterrupt:1;\r | |
| 3014 | UINT64 Reserved:62;\r | |
| 3015 | } PAL_MEMORY_CONTROL_WORD;\r | |
| 3016 | \r | |
| 3017 | /**\r | |
| 3018 | PAL Procedure - PAL_MEMORY_BUFFER.\r | |
| 3019 | \r | |
| 3020 | Provides cacheable memory to PAL for exclusive use during\r | |
| 1a2f870c | 3021 | runtime. It is optional by Itanium processors. The PAL procedure supports the\r |
| a7b64584 | 3022 | Static Registers calling convention. It could be called at\r |
| 3023 | physical mode.\r | |
| 3024 | \r | |
| 3025 | @param Index Index of PAL_MEMORY_BUFFER within the list of PAL\r | |
| 3026 | procedures.\r | |
| 3027 | @param BaseAddress Physical address of the memory buffer\r | |
| 3028 | allocated for PAL use.\r | |
| 3029 | @param AllocSize Unsigned integer denoting the size of the\r | |
| 3030 | memory buffer.\r | |
| 3031 | @param ControlWord Formatted bit vector that provides control\r | |
| 3032 | options for this procedure. See\r | |
| 3033 | PAL_MEMORY_CONTROL_WORD above.\r | |
| 3034 | \r | |
| 3035 | @retval 1 Call has not completed a buffer relocation\r | |
| 3036 | due to a pending interrupt\r | |
| 3037 | @retval 0 Call completed without error\r | |
| 3038 | @retval -1 Unimplemented procedure\r | |
| 3039 | @retval -2 Invalid argument\r | |
| 3040 | @retval -3 Call completed with error.\r | |
| 3041 | @retval -9 Call requires PAL memory buffer.\r | |
| 3042 | \r | |
| 3043 | @return R9 Returns the minimum size of the memory buffer\r | |
| 3044 | required if the alloc_size input argument was\r | |
| 3045 | not large enough.\r | |
| 3046 | \r | |
| 3047 | **/\r | |
| 3048 | #define PAL_MEMORY_BUFFER 277\r | |
| 3049 | \r | |
| 3050 | \r | |
| 3051 | /**\r | |
| 3052 | PAL Procedure - PAL_VP_CREATE.\r | |
| 3053 | \r | |
| 3054 | Initializes a new vpd for the operation of a new virtual\r | |
| 1a2f870c | 3055 | processor in the virtual environment. It is optional by Itanium processors.\r |
| a7b64584 | 3056 | The PAL procedure supports the Stacked Registers calling\r |
| 3057 | convention. It could be called at Virtual mode.\r | |
| 3058 | \r | |
| 3059 | @param Index Index of PAL_VP_CREATE within the list of PAL\r | |
| 3060 | procedures.\r | |
| 3061 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
| 3062 | Processor Descriptor (VPD).\r | |
| 3063 | @param HostIva 64-bit host virtual pointer to the host IVT\r | |
| 3064 | for the virtual processor\r | |
| 3065 | @param OptionalHandler 64-bit non-zero host-virtual pointer\r | |
| 3066 | to an optional handler for\r | |
| 3067 | virtualization intercepts.\r | |
| 3068 | \r | |
| 3069 | @retval 0 Call completed without error\r | |
| 3070 | @retval -1 Unimplemented procedure\r | |
| 3071 | @retval -2 Invalid argument\r | |
| 3072 | @retval -3 Call completed with error.\r | |
| 3073 | @retval -9 Call requires PAL memory buffer.\r | |
| 3074 | \r | |
| 3075 | **/\r | |
| 3076 | #define PAL_VP_CREATE 265\r | |
| 3077 | \r | |
| 3078 | /**\r | |
| 3079 | \r | |
| 3080 | Virtual Environment Information Parameter\r | |
| 3081 | \r | |
| 3082 | **/\r | |
| 3083 | typedef struct {\r | |
| 3084 | UINT64 Reserved1:8;\r | |
| 3085 | UINT64 Opcode:1;\r | |
| 3086 | UINT64 Reserved:53;\r | |
| 3087 | } PAL_VP_ENV_INFO_RETURN;\r | |
| 3088 | \r | |
| 3089 | /**\r | |
| 3090 | PAL Procedure - PAL_VP_ENV_INFO.\r | |
| 3091 | \r | |
| 3092 | Returns the parameters needed to enter a virtual environment.\r | |
| 1a2f870c | 3093 | It is optional by Itanium processors. The PAL procedure supports the Stacked\r |
| a7b64584 | 3094 | Registers calling convention. It could be called at Virtual\r |
| 3095 | mode.\r | |
| 3096 | \r | |
| 3097 | @param Index Index of PAL_VP_ENV_INFO within the list of PAL\r | |
| 3098 | procedures.\r | |
| 3099 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
| 3100 | Processor Descriptor (VPD).\r | |
| 3101 | @param HostIva 64-bit host virtual pointer to the host IVT\r | |
| 3102 | for the virtual processor\r | |
| 3103 | @param OptionalHandler 64-bit non-zero host-virtual pointer\r | |
| 3104 | to an optional handler for\r | |
| 3105 | virtualization intercepts.\r | |
| 3106 | \r | |
| 3107 | @retval 0 Call completed without error\r | |
| 3108 | @retval -1 Unimplemented procedure\r | |
| 3109 | @retval -2 Invalid argument\r | |
| 3110 | @retval -3 Call completed with error.\r | |
| 3111 | @retval -9 Call requires PAL memory buffer.\r | |
| 3112 | \r | |
| 3113 | @return R9 Unsigned integer denoting the number of bytes\r | |
| 3114 | required by the PAL virtual environment buffer\r | |
| 3115 | during PAL_VP_INIT_ENV\r | |
| 3116 | @return R10 64-bit vector of virtual environment\r | |
| 3117 | information. See PAL_VP_ENV_INFO_RETURN.\r | |
| 3118 | \r | |
| 3119 | \r | |
| 3120 | **/\r | |
| 3121 | #define PAL_VP_ENV_INFO 266\r | |
| 3122 | \r | |
| 3123 | /**\r | |
| 3124 | PAL Procedure - PAL_VP_EXIT_ENV.\r | |
| 3125 | \r | |
| 3126 | Allows a logical processor to exit a virtual environment.\r | |
| 1a2f870c | 3127 | It is optional by Itanium processors. The PAL procedure supports the Stacked\r |
| a7b64584 | 3128 | Registers calling convention. It could be called at Virtual\r |
| 3129 | mode.\r | |
| 3130 | \r | |
| 3131 | @param Index Index of PAL_VP_EXIT_ENV within the list of PAL\r | |
| 3132 | procedures.\r | |
| 3133 | @param Iva Optional 64-bit host virtual pointer to the IVT\r | |
| 3134 | when this procedure is done\r | |
| 3135 | \r | |
| 3136 | @retval 0 Call completed without error\r | |
| 3137 | @retval -1 Unimplemented procedure\r | |
| 3138 | @retval -2 Invalid argument\r | |
| 3139 | @retval -3 Call completed with error.\r | |
| 3140 | @retval -9 Call requires PAL memory buffer.\r | |
| 3141 | \r | |
| 3142 | **/\r | |
| 3143 | #define PAL_VP_EXIT_ENV 267\r | |
| 3144 | \r | |
| 3145 | \r | |
| 3146 | \r | |
| 3147 | /**\r | |
| 3148 | PAL Procedure - PAL_VP_INIT_ENV.\r | |
| 3149 | \r | |
| 3150 | Allows a logical processor to enter a virtual environment. It\r | |
| 1a2f870c | 3151 | is optional by Itanium processors. The PAL procedure supports the Stacked\r |
| a7b64584 | 3152 | Registers calling convention. It could be called at Virtual\r |
| 3153 | mode.\r | |
| 3154 | \r | |
| 3155 | @param Index Index of PAL_VP_INIT_ENV within the list of PAL\r | |
| 3156 | procedures.\r | |
| 3157 | @param ConfigOptions 64-bit vector of global configuration\r | |
| 3158 | settings.\r | |
| 3159 | @param PhysicalBase Host physical base address of a block of\r | |
| 3160 | contiguous physical memory for the PAL\r | |
| 3161 | virtual environment buffer 1) This\r | |
| 3162 | memory area must be allocated by the VMM\r | |
| 3163 | and be 4K aligned. The first logical\r | |
| 3164 | processor to enter the environment will\r | |
| 3165 | initialize the physical block for\r | |
| 3166 | virtualization operations.\r | |
| 3167 | @param VirtualBase Host virtual base address of the\r | |
| 3168 | corresponding physical memory block for\r | |
| 3169 | the PAL virtual environment buffer : The\r | |
| 3170 | VMM must maintain the host virtual to host\r | |
| 3171 | physical data and instruction translations\r | |
| 3172 | in TRs for addresses within the allocated\r | |
| 3173 | address space. Logical processors in this\r | |
| 3174 | virtual environment will use this address\r | |
| 3175 | when transitioning to virtual mode\r | |
| 3176 | operations.\r | |
| 3177 | \r | |
| 3178 | @retval 0 Call completed without error\r | |
| 3179 | @retval -1 Unimplemented procedure\r | |
| 3180 | @retval -2 Invalid argument\r | |
| 3181 | @retval -3 Call completed with error.\r | |
| 3182 | @retval -9 Call requires PAL memory buffer.\r | |
| 3183 | \r | |
| 3184 | @return R9 Virtualization Service Address - VSA specifies\r | |
| 3185 | the virtual base address of the PAL\r | |
| 3186 | virtualization services in this virtual\r | |
| 3187 | environment.\r | |
| 3188 | \r | |
| 3189 | \r | |
| 3190 | **/\r | |
| 3191 | #define PAL_VP_INIT_ENV 268\r | |
| 3192 | \r | |
| 3193 | \r | |
| 3194 | /**\r | |
| 3195 | PAL Procedure - PAL_VP_REGISTER.\r | |
| 3196 | \r | |
| 3197 | Register a different host IVT and/or a different optional\r | |
| 3198 | virtualization intercept handler for the virtual processor\r | |
| 1a2f870c | 3199 | specified by vpd. It is optional by Itanium processors. The PAL procedure\r |
| a7b64584 | 3200 | supports the Stacked Registers calling convention. It could be\r |
| 3201 | called at Virtual mode.\r | |
| 3202 | \r | |
| 3203 | @param Index Index of PAL_VP_REGISTER within the list of PAL\r | |
| 3204 | procedures.\r | |
| 3205 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
| 3206 | Processor Descriptor (VPD) host_iva 64-bit host\r | |
| 3207 | virtual pointer to the host IVT for the virtual\r | |
| 3208 | processor\r | |
| 3209 | @param OptionalHandler 64-bit non-zero host-virtual pointer\r | |
| 3210 | to an optional handler for\r | |
| 3211 | virtualization intercepts.\r | |
| 3212 | \r | |
| 3213 | @retval 0 Call completed without error\r | |
| 3214 | @retval -1 Unimplemented procedure\r | |
| 3215 | @retval -2 Invalid argument\r | |
| 3216 | @retval -3 Call completed with error.\r | |
| 3217 | @retval -9 Call requires PAL memory buffer.\r | |
| 3218 | \r | |
| 3219 | **/\r | |
| 3220 | #define PAL_VP_REGISTER 269\r | |
| 3221 | \r | |
| 3222 | \r | |
| 3223 | /**\r | |
| 3224 | PAL Procedure - PAL_VP_RESTORE.\r | |
| 3225 | \r | |
| 3226 | Restores virtual processor state for the specified vpd on the\r | |
| 1a2f870c | 3227 | logical processor. It is optional by Itanium processors. The PAL procedure\r |
| a7b64584 | 3228 | supports the Stacked Registers calling convention. It could be\r |
| 3229 | called at Virtual mode.\r | |
| 3230 | \r | |
| 3231 | @param Index Index of PAL_VP_RESTORE within the list of PAL\r | |
| 3232 | procedures.\r | |
| 3233 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
| 3234 | Processor Descriptor (VPD) host_iva 64-bit host\r | |
| 3235 | virtual pointer to the host IVT for the virtual\r | |
| 3236 | processor\r | |
| 3237 | @param PalVector Vector specifies PAL procedure\r | |
| 3238 | implementation-specific state to be\r | |
| 3239 | restored.\r | |
| 3240 | \r | |
| 3241 | @retval 0 Call completed without error\r | |
| 3242 | @retval -1 Unimplemented procedure\r | |
| 3243 | @retval -2 Invalid argument\r | |
| 3244 | @retval -3 Call completed with error.\r | |
| 3245 | @retval -9 Call requires PAL memory buffer.\r | |
| 3246 | \r | |
| 3247 | **/\r | |
| 3248 | #define PAL_VP_RESTORE 270\r | |
| 3249 | \r | |
| 3250 | /**\r | |
| 3251 | PAL Procedure - PAL_VP_SAVE.\r | |
| 3252 | \r | |
| 3253 | Saves virtual processor state for the specified vpd on the\r | |
| 1a2f870c | 3254 | logical processor. It is optional by Itanium processors. The PAL procedure\r |
| a7b64584 | 3255 | supports the Stacked Registers calling convention. It could be\r |
| 3256 | called at Virtual mode.\r | |
| 3257 | \r | |
| 3258 | @param Index Index of PAL_VP_SAVE within the list of PAL\r | |
| 3259 | procedures.\r | |
| 3260 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
| 3261 | Processor Descriptor (VPD) host_iva 64-bit host\r | |
| 3262 | virtual pointer to the host IVT for the virtual\r | |
| 3263 | processor\r | |
| 3264 | @param PalVector Vector specifies PAL procedure\r | |
| 3265 | implementation-specific state to be\r | |
| 3266 | restored.\r | |
| 3267 | \r | |
| 3268 | @retval 0 Call completed without error\r | |
| 3269 | @retval -1 Unimplemented procedure\r | |
| 3270 | @retval -2 Invalid argument\r | |
| 3271 | @retval -3 Call completed with error.\r | |
| 3272 | @retval -9 Call requires PAL memory buffer.\r | |
| 3273 | \r | |
| 3274 | **/\r | |
| 3275 | #define PAL_VP_SAVE 271\r | |
| 3276 | \r | |
| 3277 | \r | |
| 3278 | /**\r | |
| 3279 | PAL Procedure - PAL_VP_TERMINATE.\r | |
| 3280 | \r | |
| 3281 | Terminates operation for the specified virtual processor. It\r | |
| 1a2f870c | 3282 | is optional by Itanium processors. The PAL procedure supports the Stacked\r |
| a7b64584 | 3283 | Registers calling convention. It could be called at Virtual\r |
| 3284 | mode.\r | |
| 3285 | \r | |
| 3286 | @param Index Index of PAL_VP_TERMINATE within the list of PAL\r | |
| 3287 | procedures.\r | |
| 3288 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
| 3289 | Processor Descriptor (VPD)\r | |
| 3290 | @param Iva Optional 64-bit host virtual pointer to the IVT\r | |
| 3291 | when this procedure is done.\r | |
| 3292 | \r | |
| 3293 | @retval 0 Call completed without error\r | |
| 3294 | @retval -1 Unimplemented procedure\r | |
| 3295 | @retval -2 Invalid argument\r | |
| 3296 | @retval -3 Call completed with error.\r | |
| 3297 | @retval -9 Call requires PAL memory buffer.\r | |
| 3298 | \r | |
| 3299 | **/\r | |
| 3300 | #define PAL_VP_TERMINATE 272\r | |
| 3301 | \r | |
| 3302 | #endif\r |