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a7ed1e2e 1/** @file\r
2 Support for PCI 2.2 standard.\r
3\r
bc14bdb3 4 This file includes the definitions in the following specifications,\r
427987f5 5 PCI Local Bus Specification, 2.2\r
6 PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
bc14bdb3 7 PC Card Standard, 8.0\r
8\r
a51a9ea3 9 Copyright (c) 2006 - 2009, Intel Corporation \r
a7ed1e2e 10 All rights reserved. This program and the accompanying materials \r
11 are licensed and made available under the terms and conditions of the BSD License \r
12 which accompanies this distribution. The full text of the license may be found at \r
13 http://opensource.org/licenses/bsd-license.php \r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
17\r
a7ed1e2e 18**/\r
19\r
42eedea9 20#ifndef _PCI22_H_\r
21#define _PCI22_H_\r
a7ed1e2e 22\r
a7ed1e2e 23#define PCI_MAX_BUS 255\r
a7ed1e2e 24#define PCI_MAX_DEVICE 31\r
25#define PCI_MAX_FUNC 7\r
26\r
766f4bc1 27#pragma pack(1)\r
427987f5 28\r
29///\r
30/// Common header region in PCI Configuration Space\r
31/// Section 6.1, PCI Local Bus Specification, 2.2\r
32///\r
a7ed1e2e 33typedef struct {\r
34 UINT16 VendorId;\r
35 UINT16 DeviceId;\r
36 UINT16 Command;\r
37 UINT16 Status;\r
38 UINT8 RevisionID;\r
39 UINT8 ClassCode[3];\r
40 UINT8 CacheLineSize;\r
41 UINT8 LatencyTimer;\r
42 UINT8 HeaderType;\r
43 UINT8 BIST;\r
44} PCI_DEVICE_INDEPENDENT_REGION;\r
45\r
427987f5 46///\r
47/// PCI Device header region in PCI Configuration Space\r
48/// Section 6.1, PCI Local Bus Specification, 2.2\r
49///\r
a7ed1e2e 50typedef struct {\r
51 UINT32 Bar[6];\r
52 UINT32 CISPtr;\r
53 UINT16 SubsystemVendorID;\r
54 UINT16 SubsystemID;\r
55 UINT32 ExpansionRomBar;\r
56 UINT8 CapabilityPtr;\r
57 UINT8 Reserved1[3];\r
58 UINT32 Reserved2;\r
59 UINT8 InterruptLine;\r
60 UINT8 InterruptPin;\r
61 UINT8 MinGnt;\r
62 UINT8 MaxLat;\r
63} PCI_DEVICE_HEADER_TYPE_REGION;\r
64\r
427987f5 65///\r
66/// PCI Device Configuration Space\r
67/// Section 6.1, PCI Local Bus Specification, 2.2\r
68///\r
a7ed1e2e 69typedef struct {\r
70 PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
71 PCI_DEVICE_HEADER_TYPE_REGION Device;\r
72} PCI_TYPE00;\r
73\r
bc14bdb3 74///\r
427987f5 75/// PCI-PCI Bridge header region in PCI Configuration Space\r
76/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
bc14bdb3 77///\r
a7ed1e2e 78typedef struct {\r
79 UINT32 Bar[2];\r
80 UINT8 PrimaryBus;\r
81 UINT8 SecondaryBus;\r
82 UINT8 SubordinateBus;\r
83 UINT8 SecondaryLatencyTimer;\r
84 UINT8 IoBase;\r
85 UINT8 IoLimit;\r
86 UINT16 SecondaryStatus;\r
87 UINT16 MemoryBase;\r
88 UINT16 MemoryLimit;\r
89 UINT16 PrefetchableMemoryBase;\r
90 UINT16 PrefetchableMemoryLimit;\r
91 UINT32 PrefetchableBaseUpper32;\r
92 UINT32 PrefetchableLimitUpper32;\r
93 UINT16 IoBaseUpper16;\r
94 UINT16 IoLimitUpper16;\r
95 UINT8 CapabilityPtr;\r
96 UINT8 Reserved[3];\r
97 UINT32 ExpansionRomBAR;\r
98 UINT8 InterruptLine;\r
99 UINT8 InterruptPin;\r
100 UINT16 BridgeControl;\r
101} PCI_BRIDGE_CONTROL_REGISTER;\r
102\r
427987f5 103///\r
104/// PCI-to-PCI Bridge Configuration Space\r
105/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
106///\r
a7ed1e2e 107typedef struct {\r
108 PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
109 PCI_BRIDGE_CONTROL_REGISTER Bridge;\r
110} PCI_TYPE01;\r
111\r
112typedef union {\r
113 PCI_TYPE00 Device;\r
114 PCI_TYPE01 Bridge;\r
115} PCI_TYPE_GENERIC;\r
116\r
bc14bdb3 117/// \r
427987f5 118/// CardBus Conroller Configuration Space, \r
119/// Section 4.5.1, PC Card Standard. 8.0\r
bc14bdb3 120///\r
a7ed1e2e 121typedef struct {\r
bc14bdb3 122 UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base\r
123 UINT8 Cap_Ptr;\r
124 UINT8 Reserved;\r
125 UINT16 SecondaryStatus; ///< Secondary Status\r
126 UINT8 PciBusNumber; ///< PCI Bus Number\r
127 UINT8 CardBusBusNumber; ///< CardBus Bus Number\r
128 UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r
129 UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r
130 UINT32 MemoryBase0; ///< Memory Base Register 0\r
131 UINT32 MemoryLimit0; ///< Memory Limit Register 0\r
a7ed1e2e 132 UINT32 MemoryBase1;\r
133 UINT32 MemoryLimit1;\r
134 UINT32 IoBase0;\r
bc14bdb3 135 UINT32 IoLimit0; ///< I/O Base Register 0\r
136 UINT32 IoBase1; ///< I/O Limit Register 0\r
a7ed1e2e 137 UINT32 IoLimit1;\r
bc14bdb3 138 UINT8 InterruptLine; ///< Interrupt Line\r
139 UINT8 InterruptPin; ///< Interrupt Pin\r
140 UINT16 BridgeControl; ///< Bridge Control\r
a7ed1e2e 141} PCI_CARDBUS_CONTROL_REGISTER;\r
142\r
a2461f6b 143//\r
144// Definitions of PCI class bytes and manipulation macros.\r
145//\r
a7ed1e2e 146#define PCI_CLASS_OLD 0x00\r
bc14bdb3 147#define PCI_CLASS_OLD_OTHER 0x00\r
148#define PCI_CLASS_OLD_VGA 0x01\r
a7ed1e2e 149\r
150#define PCI_CLASS_MASS_STORAGE 0x01\r
bc14bdb3 151#define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r
152#define PCI_CLASS_MASS_STORAGE_IDE 0x01\r
153#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
154#define PCI_CLASS_MASS_STORAGE_IPI 0x03\r
155#define PCI_CLASS_MASS_STORAGE_RAID 0x04\r
156#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r
a7ed1e2e 157\r
158#define PCI_CLASS_NETWORK 0x02\r
bc14bdb3 159#define PCI_CLASS_NETWORK_ETHERNET 0x00 \r
160#define PCI_CLASS_NETWORK_TOKENRING 0x01\r
161#define PCI_CLASS_NETWORK_FDDI 0x02\r
162#define PCI_CLASS_NETWORK_ATM 0x03\r
163#define PCI_CLASS_NETWORK_ISDN 0x04\r
164#define PCI_CLASS_NETWORK_OTHER 0x80\r
a7ed1e2e 165\r
166#define PCI_CLASS_DISPLAY 0x03\r
bc14bdb3 167#define PCI_CLASS_DISPLAY_VGA 0x00\r
168#define PCI_IF_VGA_VGA 0x00\r
169#define PCI_IF_VGA_8514 0x01\r
170#define PCI_CLASS_DISPLAY_XGA 0x01\r
171#define PCI_CLASS_DISPLAY_3D 0x02\r
172#define PCI_CLASS_DISPLAY_OTHER 0x80 \r
bc14bdb3 173\r
174#define PCI_CLASS_MEDIA 0x04\r
175#define PCI_CLASS_MEDIA_VIDEO 0x00\r
176#define PCI_CLASS_MEDIA_AUDIO 0x01\r
177#define PCI_CLASS_MEDIA_TELEPHONE 0x02\r
178#define PCI_CLASS_MEDIA_OTHER 0x80\r
179\r
180#define PCI_CLASS_MEMORY_CONTROLLER 0x05\r
181#define PCI_CLASS_MEMORY_RAM 0x00\r
182#define PCI_CLASS_MEMORY_FLASH 0x01\r
183#define PCI_CLASS_MEMORY_OTHER 0x80\r
184\r
a7ed1e2e 185#define PCI_CLASS_BRIDGE 0x06\r
bc14bdb3 186#define PCI_CLASS_BRIDGE_HOST 0x00\r
187#define PCI_CLASS_BRIDGE_ISA 0x01\r
188#define PCI_CLASS_BRIDGE_EISA 0x02\r
189#define PCI_CLASS_BRIDGE_MCA 0x03\r
190#define PCI_CLASS_BRIDGE_P2P 0x04\r
191#define PCI_IF_BRIDGE_P2P 0x00\r
192#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r
193#define PCI_CLASS_BRIDGE_PCMCIA 0x05\r
194#define PCI_CLASS_BRIDGE_NUBUS 0x06\r
195#define PCI_CLASS_BRIDGE_CARDBUS 0x07\r
196#define PCI_CLASS_BRIDGE_RACEWAY 0x08\r
197#define PCI_CLASS_BRIDGE_OTHER 0x80\r
198#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
199\r
200#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers \r
201#define PCI_SUBCLASS_SERIAL 0x00\r
202#define PCI_IF_GENERIC_XT 0x00\r
203#define PCI_IF_16450 0x01\r
204#define PCI_IF_16550 0x02\r
205#define PCI_IF_16650 0x03\r
206#define PCI_IF_16750 0x04\r
207#define PCI_IF_16850 0x05\r
208#define PCI_IF_16950 0x06\r
209#define PCI_SUBCLASS_PARALLEL 0x01\r
210#define PCI_IF_PARALLEL_PORT 0x00\r
211#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r
212#define PCI_IF_ECP_PARALLEL_PORT 0x02\r
213#define PCI_IF_1284_CONTROLLER 0x03\r
214#define PCI_IF_1284_DEVICE 0xFE\r
215#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
216#define PCI_SUBCLASS_MODEM 0x03\r
217#define PCI_IF_GENERIC_MODEM 0x00\r
218#define PCI_IF_16450_MODEM 0x01\r
219#define PCI_IF_16550_MODEM 0x02\r
220#define PCI_IF_16650_MODEM 0x03\r
221#define PCI_IF_16750_MODEM 0x04\r
222#define PCI_SUBCLASS_SCC_OTHER 0x80\r
a7ed1e2e 223\r
224#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
bc14bdb3 225#define PCI_SUBCLASS_PIC 0x00\r
226#define PCI_IF_8259_PIC 0x00\r
227#define PCI_IF_ISA_PIC 0x01\r
228#define PCI_IF_EISA_PIC 0x02\r
229#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory. \r
230#define PCI_IF_APIC_CONTROLLER2 0x20 \r
231#define PCI_SUBCLASS_DMA 0x01\r
232#define PCI_IF_8237_DMA 0x00\r
233#define PCI_IF_ISA_DMA 0x01\r
234#define PCI_IF_EISA_DMA 0x02\r
235#define PCI_SUBCLASS_TIMER 0x02\r
236#define PCI_IF_8254_TIMER 0x00\r
237#define PCI_IF_ISA_TIMER 0x01\r
238#define PCI_IF_EISA_TIMER 0x02\r
239#define PCI_SUBCLASS_RTC 0x03\r
240#define PCI_IF_GENERIC_RTC 0x00\r
241#define PCI_IF_ISA_RTC 0x00\r
242#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r
243#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r
a7ed1e2e 244\r
245#define PCI_CLASS_INPUT_DEVICE 0x09\r
bc14bdb3 246#define PCI_SUBCLASS_KEYBOARD 0x00\r
247#define PCI_SUBCLASS_PEN 0x01\r
248#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
249#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
250#define PCI_SUBCLASS_GAMEPORT 0x04\r
251#define PCI_IF_GAMEPORT 0x00\r
252#define PCI_IF_GAMEPORT1 0x01\r
253#define PCI_SUBCLASS_INPUT_OTHER 0x80\r
a7ed1e2e 254\r
255#define PCI_CLASS_DOCKING_STATION 0x0A\r
256\r
257#define PCI_CLASS_PROCESSOR 0x0B\r
bc14bdb3 258#define PCI_SUBCLASS_PROC_386 0x00\r
259#define PCI_SUBCLASS_PROC_486 0x01\r
260#define PCI_SUBCLASS_PROC_PENTIUM 0x02\r
261#define PCI_SUBCLASS_PROC_ALPHA 0x10\r
262#define PCI_SUBCLASS_PROC_POWERPC 0x20\r
263#define PCI_SUBCLASS_PROC_MIPS 0x30\r
264#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r
a7ed1e2e 265\r
266#define PCI_CLASS_SERIAL 0x0C\r
bc14bdb3 267#define PCI_CLASS_SERIAL_FIREWIRE 0x00\r
268#define PCI_IF_1394 0x00\r
269#define PCI_IF_1394_OPEN_HCI 0x10\r
270#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r
271#define PCI_CLASS_SERIAL_SSA 0x02\r
272#define PCI_CLASS_SERIAL_USB 0x03\r
273#define PCI_IF_UHCI 0x00\r
274#define PCI_IF_OHCI 0x10\r
275#define PCI_IF_USB_OTHER 0x80\r
276#define PCI_IF_USB_DEVICE 0xFE\r
277#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
278#define PCI_CLASS_SERIAL_SMB 0x05\r
a7ed1e2e 279\r
280#define PCI_CLASS_WIRELESS 0x0D\r
bc14bdb3 281#define PCI_SUBCLASS_IRDA 0x00\r
282#define PCI_SUBCLASS_IR 0x01\r
283#define PCI_SUBCLASS_RF 0x02\r
284#define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r
a7ed1e2e 285\r
286#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
287\r
288#define PCI_CLASS_SATELLITE 0x0F\r
bc14bdb3 289#define PCI_SUBCLASS_TV 0x01\r
290#define PCI_SUBCLASS_AUDIO 0x02\r
291#define PCI_SUBCLASS_VOICE 0x03\r
292#define PCI_SUBCLASS_DATA 0x04\r
a7ed1e2e 293\r
bc14bdb3 294#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r
295#define PCI_SUBCLASS_NET_COMPUT 0x00\r
296#define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r
297#define PCI_SUBCLASS_SECURITY_OTHER 0x80\r
a7ed1e2e 298\r
299#define PCI_CLASS_DPIO 0x11\r
bc14bdb3 300#define PCI_SUBCLASS_DPIO 0x00\r
301#define PCI_SUBCLASS_DPIO_OTHER 0x80\r
a7ed1e2e 302\r
1833218d 303/** \r
304 Macro that checks whether the Base Class code of device matched.\r
305\r
306 @param _p Specified device.\r
307 @param c Base Class code needs matching.\r
308\r
309 @retval TRUE Base Class code matches the specified device.\r
310 @retval FALSE Base Class code doesn't match the specified device. \r
311\r
312**/\r
a7ed1e2e 313#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
1833218d 314/** \r
315 Macro that checks whether the Base Class code and Sub-Class code of device matched.\r
316\r
317 @param _p Specified device.\r
318 @param c Base Class code needs matching.\r
319 @param s Sub-Class code needs matching.\r
320\r
321 @retval TRUE Base Class code and Sub-Class code match the specified device.\r
322 @retval FALSE Base Class code and Sub-Class code don't match the specified device. \r
323\r
324**/\r
a7ed1e2e 325#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
1833218d 326/** \r
327 Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.\r
328\r
329 @param _p Specified device.\r
330 @param c Base Class code needs matching.\r
331 @param s Sub-Class code needs matching.\r
332 @param p Interface code needs matching.\r
333\r
334 @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.\r
335 @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device. \r
336\r
337**/\r
a7ed1e2e 338#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
339\r
1833218d 340/** \r
341 Macro that checks whether device is a display controller.\r
342\r
343 @param _p Specified device.\r
344\r
345 @retval TRUE Device is a display controller.\r
346 @retval FALSE Device is not a display controller.\r
347\r
348**/\r
a7ed1e2e 349#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
1833218d 350/** \r
351 Macro that checks whether device is a VGA-compatible controller.\r
352\r
353 @param _p Specified device.\r
354\r
355 @retval TRUE Device is a VGA-compatible controller.\r
356 @retval FALSE Device is not a VGA-compatible controller.\r
357\r
358**/\r
359#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\r
360/** \r
361 Macro that checks whether device is an 8514-compatible controller.\r
362\r
363 @param _p Specified device.\r
364\r
365 @retval TRUE Device is an 8514-compatible controller.\r
366 @retval FALSE Device is not an 8514-compatible controller.\r
367\r
368**/\r
369#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\r
370/** \r
371 Macro that checks whether device is built before the Class Code field was defined.\r
372\r
373 @param _p Specified device.\r
374\r
375 @retval TRUE Device is an old device.\r
376 @retval FALSE Device is not an old device.\r
377\r
378**/\r
a7ed1e2e 379#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
1833218d 380/** \r
381 Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.\r
382\r
383 @param _p Specified device.\r
384\r
385 @retval TRUE Device is an old VGA-compatible device.\r
386 @retval FALSE Device is not an old VGA-compatible device.\r
387\r
388**/\r
a7ed1e2e 389#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
1833218d 390/** \r
391 Macro that checks whether device is an IDE controller.\r
392\r
393 @param _p Specified device.\r
394\r
395 @retval TRUE Device is an IDE controller.\r
396 @retval FALSE Device is not an IDE controller.\r
397\r
398**/\r
a7ed1e2e 399#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
1833218d 400/** \r
401 Macro that checks whether device is a SCSI bus controller.\r
402\r
403 @param _p Specified device.\r
404\r
405 @retval TRUE Device is a SCSI bus controller.\r
406 @retval FALSE Device is not a SCSI bus controller.\r
407\r
408**/\r
409#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\r
410/** \r
411 Macro that checks whether device is a RAID controller.\r
412\r
413 @param _p Specified device.\r
414\r
415 @retval TRUE Device is a RAID controller.\r
416 @retval FALSE Device is not a RAID controller.\r
417\r
418**/\r
419#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\r
420/** \r
421 Macro that checks whether device is an ISA bridge.\r
422\r
423 @param _p Specified device.\r
424\r
425 @retval TRUE Device is an ISA bridge.\r
426 @retval FALSE Device is not an ISA bridge.\r
427\r
428**/\r
429#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\r
430/** \r
431 Macro that checks whether device is a PCI-to-PCI bridge.\r
432\r
433 @param _p Specified device.\r
434\r
435 @retval TRUE Device is a PCI-to-PCI bridge.\r
436 @retval FALSE Device is not a PCI-to-PCI bridge.\r
437\r
438**/\r
439#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\r
440/** \r
441 Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.\r
442\r
443 @param _p Specified device.\r
444\r
445 @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.\r
446 @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.\r
447\r
448**/\r
449#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\r
450/** \r
451 Macro that checks whether device is a 16550-compatible serial controller.\r
452\r
453 @param _p Specified device.\r
454\r
455 @retval TRUE Device is a 16550-compatible serial controller.\r
456 @retval FALSE Device is not a 16550-compatible serial controller.\r
457\r
458**/\r
a7ed1e2e 459#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
1833218d 460/** \r
461 Macro that checks whether device is a Universal Serial Bus controller.\r
462\r
463 @param _p Specified device.\r
464\r
465 @retval TRUE Device is a Universal Serial Bus controller.\r
466 @retval FALSE Device is not a Universal Serial Bus controller.\r
467\r
468**/\r
a7ed1e2e 469#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
470\r
bc14bdb3 471//\r
472// the definition of Header Type \r
473//\r
a7ed1e2e 474#define HEADER_TYPE_DEVICE 0x00\r
475#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
476#define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r
a7ed1e2e 477#define HEADER_TYPE_MULTI_FUNCTION 0x80\r
bc14bdb3 478//\r
479// Mask of Header type\r
480//\r
a7ed1e2e 481#define HEADER_LAYOUT_CODE 0x7f\r
1833218d 482/** \r
483 Macro that checks whether device is a PCI-PCI bridge.\r
484\r
485 @param _p Specified device.\r
486\r
487 @retval TRUE Device is a PCI-PCI bridge.\r
488 @retval FALSE Device is not a PCI-PCI bridge.\r
a7ed1e2e 489\r
1833218d 490**/\r
a7ed1e2e 491#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
1833218d 492/** \r
493 Macro that checks whether device is a CardBus bridge.\r
494\r
495 @param _p Specified device.\r
496\r
497 @retval TRUE Device is a CardBus bridge.\r
498 @retval FALSE Device is not a CardBus bridge.\r
499\r
500**/\r
a7ed1e2e 501#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
1833218d 502/** \r
503 Macro that checks whether device is a multiple functions device.\r
504\r
505 @param _p Specified device.\r
506\r
507 @retval TRUE Device is a multiple functions device.\r
508 @retval FALSE Device is not a multiple functions device.\r
509\r
510**/\r
a7ed1e2e 511#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
512\r
bc14bdb3 513///\r
514/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,\r
515///\r
a7ed1e2e 516#define PCI_BRIDGE_ROMBAR 0x38\r
517\r
518#define PCI_MAX_BAR 0x0006\r
519#define PCI_MAX_CONFIG_OFFSET 0x0100\r
520\r
521#define PCI_VENDOR_ID_OFFSET 0x00\r
522#define PCI_DEVICE_ID_OFFSET 0x02\r
523#define PCI_COMMAND_OFFSET 0x04\r
524#define PCI_PRIMARY_STATUS_OFFSET 0x06\r
525#define PCI_REVISION_ID_OFFSET 0x08\r
526#define PCI_CLASSCODE_OFFSET 0x09\r
527#define PCI_CACHELINE_SIZE_OFFSET 0x0C\r
528#define PCI_LATENCY_TIMER_OFFSET 0x0D\r
529#define PCI_HEADER_TYPE_OFFSET 0x0E\r
530#define PCI_BIST_OFFSET 0x0F\r
531#define PCI_BASE_ADDRESSREG_OFFSET 0x10\r
532#define PCI_CARDBUS_CIS_OFFSET 0x28\r
bc14bdb3 533#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r
a7ed1e2e 534#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r
bc14bdb3 535#define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r
a7ed1e2e 536#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r
537#define PCI_EXPANSION_ROM_BASE 0x30\r
538#define PCI_CAPBILITY_POINTER_OFFSET 0x34\r
bc14bdb3 539#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r
540#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r
541#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r
542#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r
a7ed1e2e 543\r
a2461f6b 544//\r
545// defined in PCI-to-PCI Bridge Architecture Specification\r
546//\r
bc14bdb3 547#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r
548#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r
549#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r
550#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E \r
551#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E \r
a7ed1e2e 552\r
bc14bdb3 553///\r
554/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
555///\r
a7ed1e2e 556#define PCI_INT_LINE_UNKNOWN 0xFF \r
557\r
1833218d 558///\r
559/// PCI Access Data Format\r
560///\r
a7ed1e2e 561typedef union {\r
562 struct {\r
563 UINT32 Reg : 8;\r
564 UINT32 Func : 3;\r
565 UINT32 Dev : 5;\r
566 UINT32 Bus : 8;\r
567 UINT32 Reserved : 7;\r
568 UINT32 Enable : 1;\r
569 } Bits;\r
570 UINT32 Uint32;\r
571} PCI_CONFIG_ACCESS_CF8;\r
572\r
766f4bc1 573#pragma pack()\r
574\r
bc14bdb3 575#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r
576#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r
577#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r
578#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r
579#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r
580#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r
581#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r
582#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r
583#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r
584#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r
a7ed1e2e 585\r
a2461f6b 586//\r
587// defined in PCI-to-PCI Bridge Architecture Specification\r
588//\r
bc14bdb3 589#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\r
590#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\r
591#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\r
592#define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008\r
593#define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010\r
594#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020\r
595#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040\r
596#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080\r
597#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100\r
598#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200\r
599#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\r
600#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\r
601\r
a2461f6b 602//\r
603// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
604//\r
bc14bdb3 605#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r
606#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r
607#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r
608#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r
a7ed1e2e 609\r
610//\r
611// Following are the PCI status control bit\r
612//\r
bc14bdb3 613#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r
614#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r
615#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r
616#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r
a7ed1e2e 617\r
bc14bdb3 618///\r
619/// defined in PC Card Standard\r
620///\r
a7ed1e2e 621#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
622\r
766f4bc1 623#pragma pack(1)\r
a7ed1e2e 624//\r
625// PCI Capability List IDs and records\r
626//\r
627#define EFI_PCI_CAPABILITY_ID_PMI 0x01\r
628#define EFI_PCI_CAPABILITY_ID_AGP 0x02\r
629#define EFI_PCI_CAPABILITY_ID_VPD 0x03\r
630#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
631#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
632#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
a2461f6b 633\r
427987f5 634///\r
635/// Capabilities List Header\r
636/// Section 6.7, PCI Local Bus Specification, 2.2\r
637///\r
a7ed1e2e 638typedef struct {\r
639 UINT8 CapabilityID;\r
640 UINT8 NextItemPtr;\r
641} EFI_PCI_CAPABILITY_HDR;\r
642\r
1bc5d021 643///\r
427987f5 644/// Power Management Register Block Definition \r
645/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
1bc5d021 646///\r
a7ed1e2e 647typedef struct {\r
648 EFI_PCI_CAPABILITY_HDR Hdr;\r
649 UINT16 PMC;\r
650 UINT16 PMCSR;\r
651 UINT8 BridgeExtention;\r
652 UINT8 Data;\r
653} EFI_PCI_CAPABILITY_PMI;\r
654\r
1bc5d021 655///\r
427987f5 656/// A.G.P Capability\r
657/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r
1bc5d021 658///\r
a7ed1e2e 659typedef struct {\r
660 EFI_PCI_CAPABILITY_HDR Hdr;\r
661 UINT8 Rev;\r
662 UINT8 Reserved;\r
663 UINT32 Status;\r
664 UINT32 Command;\r
665} EFI_PCI_CAPABILITY_AGP;\r
666\r
1bc5d021 667///\r
427987f5 668/// VPD Capability Structure\r
669/// Appendix I, PCI Local Bus Specification, 2.2\r
1bc5d021 670///\r
a7ed1e2e 671typedef struct {\r
672 EFI_PCI_CAPABILITY_HDR Hdr;\r
673 UINT16 AddrReg;\r
674 UINT32 DataReg;\r
675} EFI_PCI_CAPABILITY_VPD;\r
676\r
1bc5d021 677///\r
427987f5 678/// Slot Numbering Capabilities Register\r
679/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2\r
1bc5d021 680///\r
a7ed1e2e 681typedef struct {\r
682 EFI_PCI_CAPABILITY_HDR Hdr;\r
683 UINT8 ExpnsSlotReg;\r
684 UINT8 ChassisNo;\r
685} EFI_PCI_CAPABILITY_SLOTID;\r
686\r
1bc5d021 687///\r
427987f5 688/// Message Capability Structure for 32-bit Message Address\r
689/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
1bc5d021 690///\r
a7ed1e2e 691typedef struct {\r
692 EFI_PCI_CAPABILITY_HDR Hdr;\r
693 UINT16 MsgCtrlReg;\r
694 UINT32 MsgAddrReg;\r
695 UINT16 MsgDataReg;\r
696} EFI_PCI_CAPABILITY_MSI32;\r
697\r
427987f5 698///\r
699/// Message Capability Structure for 64-bit Message Address\r
700/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
701///\r
a7ed1e2e 702typedef struct {\r
703 EFI_PCI_CAPABILITY_HDR Hdr;\r
704 UINT16 MsgCtrlReg;\r
705 UINT32 MsgAddrRegLsdw;\r
706 UINT32 MsgAddrRegMsdw;\r
707 UINT16 MsgDataReg;\r
708} EFI_PCI_CAPABILITY_MSI64;\r
709\r
1bc5d021 710///\r
427987f5 711/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, \r
712/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r
1bc5d021 713///\r
a7ed1e2e 714typedef struct {\r
715 EFI_PCI_CAPABILITY_HDR Hdr;\r
1bc5d021 716 ///\r
717 /// not finished - fields need to go here\r
718 ///\r
a7ed1e2e 719} EFI_PCI_CAPABILITY_HOTPLUG;\r
720\r
a7ed1e2e 721#define DEVICE_ID_NOCARE 0xFFFF\r
722\r
723#define PCI_ACPI_UNUSED 0\r
724#define PCI_BAR_NOCHANGE 0\r
725#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL\r
726#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL\r
727#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r
728#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r
729\r
730#define PCI_BAR_IDX0 0x00\r
731#define PCI_BAR_IDX1 0x01\r
732#define PCI_BAR_IDX2 0x02\r
733#define PCI_BAR_IDX3 0x03\r
734#define PCI_BAR_IDX4 0x04\r
735#define PCI_BAR_IDX5 0x05\r
736#define PCI_BAR_ALL 0xFF\r
737\r
bc14bdb3 738///\r
739/// EFI PCI Option ROM definitions\r
740/// \r
741#define EFI_ROOT_BRIDGE_LIST 'eprb' \r
742#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r
afcf4907 743\r
bc14bdb3 744#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
13c31065 745#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r
bc14bdb3 746#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
a2461f6b 747#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\r
bc14bdb3 748\r
427987f5 749///\r
750/// Standard PCI Expansion ROM Header\r
751/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
752///\r
bc14bdb3 753typedef struct {\r
754 UINT16 Signature; ///< 0xaa55\r
755 UINT8 Reserved[0x16];\r
756 UINT16 PcirOffset;\r
757} PCI_EXPANSION_ROM_HEADER;\r
758\r
427987f5 759///\r
760/// Legacy ROM Header Extensions\r
761/// Section 6.3.3.1, PCI Local Bus Specification, 2.2\r
762///\r
bc14bdb3 763typedef struct {\r
764 UINT16 Signature; ///< 0xaa55\r
765 UINT8 Size512;\r
766 UINT8 InitEntryPoint[3];\r
767 UINT8 Reserved[0x12];\r
768 UINT16 PcirOffset;\r
769} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
770\r
427987f5 771///\r
772/// PCI Data Structure Format\r
773/// Section 6.3.1.2, PCI Local Bus Specification, 2.2\r
774///\r
bc14bdb3 775typedef struct {\r
776 UINT32 Signature; ///< "PCIR"\r
777 UINT16 VendorId;\r
778 UINT16 DeviceId;\r
779 UINT16 Reserved0;\r
780 UINT16 Length;\r
781 UINT8 Revision;\r
782 UINT8 ClassCode[3];\r
783 UINT16 ImageLength;\r
784 UINT16 CodeRevision;\r
785 UINT8 CodeType;\r
786 UINT8 Indicator;\r
787 UINT16 Reserved1;\r
788} PCI_DATA_STRUCTURE;\r
789\r
790///\r
427987f5 791/// EFI PCI Expansion ROM Header\r
792/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
bc14bdb3 793///\r
afcf4907 794typedef struct {\r
bc14bdb3 795 UINT16 Signature; ///< 0xaa55\r
afcf4907 796 UINT16 InitializationSize;\r
bc14bdb3 797 UINT32 EfiSignature; ///< 0x0EF1\r
afcf4907 798 UINT16 EfiSubsystem;\r
799 UINT16 EfiMachineType;\r
800 UINT16 CompressionType;\r
801 UINT8 Reserved[8];\r
802 UINT16 EfiImageHeaderOffset;\r
803 UINT16 PcirOffset;\r
804} EFI_PCI_EXPANSION_ROM_HEADER;\r
805\r
806typedef union {\r
807 UINT8 *Raw;\r
808 PCI_EXPANSION_ROM_HEADER *Generic;\r
809 EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r
810 EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r
811} EFI_PCI_ROM_HEADER;\r
812\r
766f4bc1 813#pragma pack()\r
814\r
a7ed1e2e 815#endif\r
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