[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pci22.h

/** @file\r
  Support for PCI 2.2 standard.\r
\r
  Copyright (c) 2006 - 2007, Intel Corporation                                                         \r
  All rights reserved. This program and the accompanying materials                          \r
  are licensed and made available under the terms and conditions of the BSD License         \r
  which accompanies this distribution.  The full text of the license may be found at        \r
  http://opensource.org/licenses/bsd-license.php                                            \r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
**/\r
\r
#ifndef _PCI22_H\r
#define _PCI22_H\r
\r
#define PCI_MAX_SEGMENT 0\r
\r
#define PCI_MAX_BUS     255\r
\r
#define PCI_MAX_DEVICE  31\r
#define PCI_MAX_FUNC    7\r
\r
//\r
// Command\r
//\r
#define PCI_VGA_PALETTE_SNOOP_DISABLED  0x20\r
\r
#pragma pack(push, 1)\r
typedef struct {\r
  UINT16  VendorId;\r
  UINT16  DeviceId;\r
  UINT16  Command;\r
  UINT16  Status;\r
  UINT8   RevisionID;\r
  UINT8   ClassCode[3];\r
  UINT8   CacheLineSize;\r
  UINT8   LatencyTimer;\r
  UINT8   HeaderType;\r
  UINT8   BIST;\r
} PCI_DEVICE_INDEPENDENT_REGION;\r
\r
typedef struct {\r
  UINT32  Bar[6];\r
  UINT32  CISPtr;\r
  UINT16  SubsystemVendorID;\r
  UINT16  SubsystemID;\r
  UINT32  ExpansionRomBar;\r
  UINT8   CapabilityPtr;\r
  UINT8   Reserved1[3];\r
  UINT32  Reserved2;\r
  UINT8   InterruptLine;\r
  UINT8   InterruptPin;\r
  UINT8   MinGnt;\r
  UINT8   MaxLat;\r
} PCI_DEVICE_HEADER_TYPE_REGION;\r
\r
typedef struct {\r
  PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
  PCI_DEVICE_HEADER_TYPE_REGION Device;\r
} PCI_TYPE00;\r
\r
typedef struct {\r
  UINT32  Bar[2];\r
  UINT8   PrimaryBus;\r
  UINT8   SecondaryBus;\r
  UINT8   SubordinateBus;\r
  UINT8   SecondaryLatencyTimer;\r
  UINT8   IoBase;\r
  UINT8   IoLimit;\r
  UINT16  SecondaryStatus;\r
  UINT16  MemoryBase;\r
  UINT16  MemoryLimit;\r
  UINT16  PrefetchableMemoryBase;\r
  UINT16  PrefetchableMemoryLimit;\r
  UINT32  PrefetchableBaseUpper32;\r
  UINT32  PrefetchableLimitUpper32;\r
  UINT16  IoBaseUpper16;\r
  UINT16  IoLimitUpper16;\r
  UINT8   CapabilityPtr;\r
  UINT8   Reserved[3];\r
  UINT32  ExpansionRomBAR;\r
  UINT8   InterruptLine;\r
  UINT8   InterruptPin;\r
  UINT16  BridgeControl;\r
} PCI_BRIDGE_CONTROL_REGISTER;\r
\r
typedef struct {\r
  PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
  PCI_BRIDGE_CONTROL_REGISTER   Bridge;\r
} PCI_TYPE01;\r
\r
typedef union {\r
  PCI_TYPE00  Device;\r
  PCI_TYPE01  Bridge;\r
} PCI_TYPE_GENERIC;\r
\r
typedef struct {\r
  UINT32  CardBusSocketReg; // Cardus Socket/ExCA Base\r
  // Address Register\r
  //\r
  UINT16  Reserved;\r
  UINT16  SecondaryStatus;      // Secondary Status\r
  UINT8   PciBusNumber;         // PCI Bus Number\r
  UINT8   CardBusBusNumber;     // CardBus Bus Number\r
  UINT8   SubordinateBusNumber; // Subordinate Bus Number\r
  UINT8   CardBusLatencyTimer;  // CardBus Latency Timer\r
  UINT32  MemoryBase0;          // Memory Base Register 0\r
  UINT32  MemoryLimit0;         // Memory Limit Register 0\r
  UINT32  MemoryBase1;\r
  UINT32  MemoryLimit1;\r
  UINT32  IoBase0;\r
  UINT32  IoLimit0;             // I/O Base Register 0\r
  UINT32  IoBase1;              // I/O Limit Register 0\r
  UINT32  IoLimit1;\r
  UINT8   InterruptLine;        // Interrupt Line\r
  UINT8   InterruptPin;         // Interrupt Pin\r
  UINT16  BridgeControl;        // Bridge Control\r
} PCI_CARDBUS_CONTROL_REGISTER;\r
\r
//\r
// Definitions of PCI class bytes and manipulation macros.\r
//\r
#define PCI_CLASS_OLD                 0x00\r
#define PCI_CLASS_OLD_OTHER           0x00\r
#define PCI_CLASS_OLD_VGA             0x01\r
\r
#define PCI_CLASS_MASS_STORAGE        0x01\r
#define PCI_CLASS_MASS_STORAGE_SCSI   0x00\r
#define PCI_CLASS_MASS_STORAGE_IDE    0x01  // obsolete\r
#define PCI_CLASS_IDE                 0x01\r
#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
#define PCI_CLASS_MASS_STORAGE_IPI    0x03\r
#define PCI_CLASS_MASS_STORAGE_RAID   0x04\r
#define PCI_CLASS_MASS_STORAGE_OTHER  0x80\r
\r
#define PCI_CLASS_NETWORK             0x02\r
#define PCI_CLASS_NETWORK_ETHERNET    0x00\r
#define PCI_CLASS_ETHERNET            0x00  // obsolete\r
#define PCI_CLASS_NETWORK_TOKENRING   0x01\r
#define PCI_CLASS_NETWORK_FDDI        0x02\r
#define PCI_CLASS_NETWORK_ATM         0x03\r
#define PCI_CLASS_NETWORK_ISDN        0x04\r
#define PCI_CLASS_NETWORK_OTHER       0x80\r
\r
#define PCI_CLASS_DISPLAY             0x03\r
#define PCI_CLASS_DISPLAY_CTRL        0x03  // obsolete\r
#define PCI_CLASS_DISPLAY_VGA         0x00\r
#define PCI_CLASS_VGA                 0x00  // obsolete\r
#define PCI_CLASS_DISPLAY_XGA         0x01\r
#define PCI_CLASS_DISPLAY_3D          0x02\r
#define PCI_CLASS_DISPLAY_OTHER       0x80\r
#define PCI_CLASS_DISPLAY_GFX         0x80\r
#define PCI_CLASS_GFX                 0x80  // obsolete\r
#define PCI_CLASS_BRIDGE              0x06\r
#define PCI_CLASS_BRIDGE_HOST         0x00\r
#define PCI_CLASS_BRIDGE_ISA          0x01\r
#define PCI_CLASS_ISA                 0x01  // obsolete\r
#define PCI_CLASS_BRIDGE_EISA         0x02\r
#define PCI_CLASS_BRIDGE_MCA          0x03\r
#define PCI_CLASS_BRIDGE_P2P          0x04\r
#define PCI_CLASS_BRIDGE_PCMCIA       0x05\r
#define PCI_CLASS_BRIDGE_NUBUS        0x06\r
#define PCI_CLASS_BRIDGE_CARDBUS      0x07\r
#define PCI_CLASS_BRIDGE_RACEWAY      0x08\r
#define PCI_CLASS_BRIDGE_ISA_PDECODE  0x80\r
#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80  // obsolete\r
\r
#define PCI_CLASS_SCC                 0x07  // Simple communications controllers \r
#define PCI_SUBCLASS_SERIAL           0x00\r
#define PCI_IF_GENERIC_XT             0x00\r
#define PCI_IF_16450                  0x01\r
#define PCI_IF_16550                  0x02\r
#define PCI_IF_16650                  0x03\r
#define PCI_IF_16750                  0x04\r
#define PCI_IF_16850                  0x05\r
#define PCI_IF_16950                  0x06\r
#define PCI_SUBCLASS_PARALLEL         0x01\r
#define PCI_IF_PARALLEL_PORT          0x00\r
#define PCI_IF_BI_DIR_PARALLEL_PORT   0x01\r
#define PCI_IF_ECP_PARALLEL_PORT      0x02\r
#define PCI_IF_1284_CONTROLLER        0x03\r
#define PCI_IF_1284_DEVICE            0xFE\r
#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
#define PCI_SUBCLASS_MODEM            0x03\r
#define PCI_IF_GENERIC_MODEM          0x00\r
#define PCI_IF_16450_MODEM            0x01\r
#define PCI_IF_16550_MODEM            0x02\r
#define PCI_IF_16650_MODEM            0x03\r
#define PCI_IF_16750_MODEM            0x04\r
#define PCI_SUBCLASS_OTHER            0x80\r
\r
#define PCI_CLASS_SYSTEM_PERIPHERAL   0x08\r
#define PCI_SUBCLASS_PIC              0x00\r
#define PCI_IF_8259_PIC               0x00\r
#define PCI_IF_ISA_PIC                0x01\r
#define PCI_IF_EISA_PIC               0x02\r
#define PCI_IF_APIC_CONTROLLER        0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.  \r
#define PCI_IF_APIC_CONTROLLER2       0x20 \r
#define PCI_SUBCLASS_TIMER            0x02\r
#define PCI_IF_8254_TIMER             0x00\r
#define PCI_IF_ISA_TIMER              0x01\r
#define PCI_EISA_TIMER                0x02\r
#define PCI_SUBCLASS_RTC              0x03\r
#define PCI_IF_GENERIC_RTC            0x00\r
#define PCI_IF_ISA_RTC                0x00\r
#define PCI_SUBCLASS_PNP_CONTROLLER   0x04 // HotPlug Controller\r
\r
#define PCI_CLASS_INPUT_DEVICE        0x09\r
#define PCI_SUBCLASS_KEYBOARD         0x00\r
#define PCI_SUBCLASS_PEN              0x01\r
#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
#define PCI_SUBCLASS_SCAN_CONTROLLER  0x03\r
#define PCI_SUBCLASS_GAMEPORT         0x04\r
\r
#define PCI_CLASS_DOCKING_STATION     0x0A\r
\r
#define PCI_CLASS_PROCESSOR           0x0B\r
#define PCI_SUBCLASS_PROC_386         0x00\r
#define PCI_SUBCLASS_PROC_486         0x01\r
#define PCI_SUBCLASS_PROC_PENTIUM     0x02\r
#define PCI_SUBCLASS_PROC_ALPHA       0x10\r
#define PCI_SUBCLASS_PROC_POWERPC     0x20\r
#define PCI_SUBCLASS_PROC_MIPS        0x30\r
#define PCI_SUBCLASS_PROC_CO_PORC     0x40 // Co-Processor\r
\r
#define PCI_CLASS_SERIAL              0x0C\r
#define PCI_CLASS_SERIAL_FIREWIRE     0x00\r
#define PCI_CLASS_SERIAL_ACCESS_BUS   0x01\r
#define PCI_CLASS_SERIAL_SSA          0x02\r
#define PCI_CLASS_SERIAL_USB          0x03\r
#define PCI_IF_EHCI                   0x20\r
#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
#define PCI_CLASS_SERIAL_SMB          0x05\r
\r
#define PCI_CLASS_WIRELESS            0x0D\r
#define PCI_SUBCLASS_IRDA             0x00\r
#define PCI_SUBCLASS_IR               0x01\r
#define PCI_SUBCLASS_RF               0x02\r
\r
#define PCI_CLASS_INTELLIGENT_IO      0x0E\r
\r
#define PCI_CLASS_SATELLITE           0x0F\r
#define PCI_SUBCLASS_TV               0x01\r
#define PCI_SUBCLASS_AUDIO            0x02\r
#define PCI_SUBCLASS_VOICE            0x03\r
#define PCI_SUBCLASS_DATA             0x04\r
\r
#define PCI_SECURITY_CONTROLLER       0x10 // Encryption and decryption controller\r
#define PCI_SUBCLASS_NET_COMPUT       0x00\r
#define PCI_SUBCLASS_ENTERTAINMENT    0x10 \r
\r
#define PCI_CLASS_DPIO                0x11\r
\r
#define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))\r
#define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
#define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
\r
#define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
#define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)\r
#define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)\r
#define IS_PCI_GFX(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)\r
#define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)\r
#define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
#define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
#define IS_PCI_SCSI(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)\r
#define IS_PCI_RAID(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)\r
#define IS_PCI_LPC(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)\r
#define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)\r
#define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)\r
#define IS_PCI_16550_SERIAL(_p)       IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
#define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
\r
#define HEADER_TYPE_DEVICE            0x00\r
#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
#define HEADER_TYPE_CARDBUS_BRIDGE    0x02\r
\r
#define HEADER_TYPE_MULTI_FUNCTION    0x80\r
#define HEADER_LAYOUT_CODE            0x7f\r
\r
#define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
#define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
#define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
\r
#define PCI_DEVICE_ROMBAR             0x30\r
#define PCI_BRIDGE_ROMBAR             0x38\r
\r
#define PCI_MAX_BAR                   0x0006\r
#define PCI_MAX_CONFIG_OFFSET         0x0100\r
\r
#define PCI_VENDOR_ID_OFFSET                        0x00\r
#define PCI_DEVICE_ID_OFFSET                        0x02\r
#define PCI_COMMAND_OFFSET                          0x04\r
#define PCI_PRIMARY_STATUS_OFFSET                   0x06\r
#define PCI_REVISION_ID_OFFSET                      0x08\r
#define PCI_CLASSCODE_OFFSET                        0x09\r
#define PCI_CACHELINE_SIZE_OFFSET                   0x0C\r
#define PCI_LATENCY_TIMER_OFFSET                    0x0D\r
#define PCI_HEADER_TYPE_OFFSET                      0x0E\r
#define PCI_BIST_OFFSET                             0x0F\r
#define PCI_BASE_ADDRESSREG_OFFSET                  0x10\r
#define PCI_CARDBUS_CIS_OFFSET                      0x28\r
#define PCI_SVID_OFFSET                             0x2C // SubSystem Vendor id\r
#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C\r
#define PCI_SID_OFFSET                              0x2E // SubSystem ID\r
#define PCI_SUBSYSTEM_ID_OFFSET                     0x2E\r
#define PCI_EXPANSION_ROM_BASE                      0x30\r
#define PCI_CAPBILITY_POINTER_OFFSET                0x34\r
#define PCI_INT_LINE_OFFSET                         0x3C // Interrupt Line Register\r
#define PCI_INT_PIN_OFFSET                          0x3D // Interrupt Pin Register\r
#define PCI_MAXGNT_OFFSET                           0x3E // Max Grant Register\r
#define PCI_MAXLAT_OFFSET                           0x3F // Max Latency Register\r
\r
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E\r
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E\r
\r
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18\r
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19\r
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a\r
\r
//\r
// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
//\r
#define PCI_INT_LINE_UNKNOWN                        0xFF               \r
\r
typedef union {\r
  struct {\r
    UINT32  Reg : 8;\r
    UINT32  Func : 3;\r
    UINT32  Dev : 5;\r
    UINT32  Bus : 8;\r
    UINT32  Reserved : 7;\r
    UINT32  Enable : 1;\r
  } Bits;\r
  UINT32  Uint32;\r
} PCI_CONFIG_ACCESS_CF8;\r
\r
#pragma pack()\r
\r
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55\r
#define PCI_DATA_STRUCTURE_SIGNATURE                    EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')\r
#define PCI_CODE_TYPE_PCAT_IMAGE                        0x00\r
#define PCI_CODE_TYPE_EFI_IMAGE                         0x03\r
#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001\r
\r
#define EFI_PCI_COMMAND_IO_SPACE                        0x0001\r
#define EFI_PCI_COMMAND_MEMORY_SPACE                    0x0002\r
#define EFI_PCI_COMMAND_BUS_MASTER                      0x0004\r
#define EFI_PCI_COMMAND_SPECIAL_CYCLE                   0x0008\r
#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     0x0010\r
#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               0x0020\r
#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            0x0040\r
#define EFI_PCI_COMMAND_STEPPING_CONTROL                0x0080\r
#define EFI_PCI_COMMAND_SERR                            0x0100\r
#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               0x0200\r
\r
#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    0x0001\r
#define EFI_PCI_BRIDGE_CONTROL_SERR                     0x0002\r
#define EFI_PCI_BRIDGE_CONTROL_ISA                      0x0004\r
#define EFI_PCI_BRIDGE_CONTROL_VGA                      0x0008\r
#define EFI_PCI_BRIDGE_CONTROL_VGA_16                   0x0010\r
#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             0x0020\r
#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      0x0040\r
#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        0x0080\r
#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    0x0100\r
#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  0x0200\r
#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             0x0400\r
#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       0x0800\r
\r
//\r
// Following are the PCI-CARDBUS bridge control bit\r
//\r
#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE       0x0080\r
#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE   0x0100\r
#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE   0x0200\r
#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400\r
\r
//\r
// Following are the PCI status control bit\r
//\r
#define EFI_PCI_STATUS_CAPABILITY             0x0010\r
#define EFI_PCI_STATUS_66MZ_CAPABLE           0x0020\r
#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE     0x0080\r
#define EFI_PCI_MASTER_DATA_PARITY_ERROR      0x0100\r
\r
#define EFI_PCI_CAPABILITY_PTR                0x34\r
#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT16  Signature;    // 0xaa55\r
  UINT8   Reserved[0x16];\r
  UINT16  PcirOffset;\r
} PCI_EXPANSION_ROM_HEADER;\r
\r
typedef struct {\r
  UINT16  Signature;    // 0xaa55\r
  UINT8   Size512;\r
  UINT8   InitEntryPoint[3];\r
  UINT8   Reserved[0x12];\r
  UINT16  PcirOffset;\r
} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
\r
typedef struct {\r
  UINT32  Signature;    // "PCIR"\r
  UINT16  VendorId;\r
  UINT16  DeviceId;\r
  UINT16  Reserved0;\r
  UINT16  Length;\r
  UINT8   Revision;\r
  UINT8   ClassCode[3];\r
  UINT16  ImageLength;\r
  UINT16  CodeRevision;\r
  UINT8   CodeType;\r
  UINT8   Indicator;\r
  UINT16  Reserved1;\r
} PCI_DATA_STRUCTURE;\r
\r
//\r
// PCI Capability List IDs and records\r
//\r
#define EFI_PCI_CAPABILITY_ID_PMI     0x01\r
#define EFI_PCI_CAPABILITY_ID_AGP     0x02\r
#define EFI_PCI_CAPABILITY_ID_VPD     0x03\r
#define EFI_PCI_CAPABILITY_ID_SLOTID  0x04\r
#define EFI_PCI_CAPABILITY_ID_MSI     0x05\r
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
#define EFI_PCI_CAPABILITY_ID_PCIX    0x07\r
\r
typedef struct {\r
  UINT8 CapabilityID;\r
  UINT8 NextItemPtr;\r
} EFI_PCI_CAPABILITY_HDR;\r
\r
//\r
// Capability EFI_PCI_CAPABILITY_ID_PMI\r
//\r
typedef struct {\r
  EFI_PCI_CAPABILITY_HDR  Hdr;\r
  UINT16                  PMC;\r
  UINT16                  PMCSR;\r
  UINT8                   BridgeExtention;\r
  UINT8                   Data;\r
} EFI_PCI_CAPABILITY_PMI;\r
\r
//\r
// Capability EFI_PCI_CAPABILITY_ID_AGP\r
//\r
typedef struct {\r
  EFI_PCI_CAPABILITY_HDR  Hdr;\r
  UINT8                   Rev;\r
  UINT8                   Reserved;\r
  UINT32                  Status;\r
  UINT32                  Command;\r
} EFI_PCI_CAPABILITY_AGP;\r
\r
//\r
// Capability EFI_PCI_CAPABILITY_ID_VPD\r
//\r
typedef struct {\r
  EFI_PCI_CAPABILITY_HDR  Hdr;\r
  UINT16                  AddrReg;\r
  UINT32                  DataReg;\r
} EFI_PCI_CAPABILITY_VPD;\r
\r
//\r
// Capability EFI_PCI_CAPABILITY_ID_SLOTID\r
//\r
typedef struct {\r
  EFI_PCI_CAPABILITY_HDR  Hdr;\r
  UINT8                   ExpnsSlotReg;\r
  UINT8                   ChassisNo;\r
} EFI_PCI_CAPABILITY_SLOTID;\r
\r
//\r
// Capability EFI_PCI_CAPABILITY_ID_MSI\r
//\r
typedef struct {\r
  EFI_PCI_CAPABILITY_HDR  Hdr;\r
  UINT16                  MsgCtrlReg;\r
  UINT32                  MsgAddrReg;\r
  UINT16                  MsgDataReg;\r
} EFI_PCI_CAPABILITY_MSI32;\r
\r
typedef struct {\r
  EFI_PCI_CAPABILITY_HDR  Hdr;\r
  UINT16                  MsgCtrlReg;\r
  UINT32                  MsgAddrRegLsdw;\r
  UINT32                  MsgAddrRegMsdw;\r
  UINT16                  MsgDataReg;\r
} EFI_PCI_CAPABILITY_MSI64;\r
\r
//\r
// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG\r
//\r
typedef struct {\r
  EFI_PCI_CAPABILITY_HDR  Hdr;\r
  //\r
  // not finished - fields need to go here\r
  //\r
} EFI_PCI_CAPABILITY_HOTPLUG;\r
\r
//\r
// Capability EFI_PCI_CAPABILITY_ID_PCIX\r
//\r
typedef struct {\r
  EFI_PCI_CAPABILITY_HDR  Hdr;\r
  UINT16                  CommandReg;\r
  UINT32                  StatusReg;\r
} EFI_PCI_CAPABILITY_PCIX;\r
\r
typedef struct {\r
  EFI_PCI_CAPABILITY_HDR  Hdr;\r
  UINT16                  SecStatusReg;\r
  UINT32                  StatusReg;\r
  UINT32                  SplitTransCtrlRegUp;\r
  UINT32                  SplitTransCtrlRegDn;\r
} EFI_PCI_CAPABILITY_PCIX_BRDG;\r
\r
#define DEVICE_ID_NOCARE    0xFFFF\r
\r
#define PCI_ACPI_UNUSED     0\r
#define PCI_BAR_NOCHANGE    0\r
#define PCI_BAR_OLD_ALIGN   0xFFFFFFFFFFFFFFFFULL\r
#define PCI_BAR_EVEN_ALIGN  0xFFFFFFFFFFFFFFFEULL\r
#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r
#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r
\r
#define PCI_BAR_IDX0        0x00\r
#define PCI_BAR_IDX1        0x01\r
#define PCI_BAR_IDX2        0x02\r
#define PCI_BAR_IDX3        0x03\r
#define PCI_BAR_IDX4        0x04\r
#define PCI_BAR_IDX5        0x05\r
#define PCI_BAR_ALL         0xFF\r
\r
#pragma pack(pop)\r
\r
#endif\r
Commit	Line	Data
a7ed1e2e	1	/** @file\r
	2	Support for PCI 2.2 standard.\r
	3	\r
	4	Copyright (c) 2006 - 2007, Intel Corporation \r
	5	All rights reserved. This program and the accompanying materials \r
	6	are licensed and made available under the terms and conditions of the BSD License \r
	7	which accompanies this distribution. The full text of the license may be found at \r
	8	http://opensource.org/licenses/bsd-license.php \r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	\r
a7ed1e2e	13	**/\r
	14	\r
	15	#ifndef _PCI22_H\r
	16	#define _PCI22_H\r
	17	\r
	18	#define PCI_MAX_SEGMENT 0\r
	19	\r
	20	#define PCI_MAX_BUS 255\r
	21	\r
	22	#define PCI_MAX_DEVICE 31\r
	23	#define PCI_MAX_FUNC 7\r
	24	\r
	25	//\r
	26	// Command\r
	27	//\r
	28	#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20\r
	29	\r
	30	#pragma pack(push, 1)\r
	31	typedef struct {\r
	32	UINT16 VendorId;\r
	33	UINT16 DeviceId;\r
	34	UINT16 Command;\r
	35	UINT16 Status;\r
	36	UINT8 RevisionID;\r
	37	UINT8 ClassCode[3];\r
	38	UINT8 CacheLineSize;\r
	39	UINT8 LatencyTimer;\r
	40	UINT8 HeaderType;\r
	41	UINT8 BIST;\r
	42	} PCI_DEVICE_INDEPENDENT_REGION;\r
	43	\r
	44	typedef struct {\r
	45	UINT32 Bar[6];\r
	46	UINT32 CISPtr;\r
	47	UINT16 SubsystemVendorID;\r
	48	UINT16 SubsystemID;\r
	49	UINT32 ExpansionRomBar;\r
	50	UINT8 CapabilityPtr;\r
	51	UINT8 Reserved1[3];\r
	52	UINT32 Reserved2;\r
	53	UINT8 InterruptLine;\r
	54	UINT8 InterruptPin;\r
	55	UINT8 MinGnt;\r
	56	UINT8 MaxLat;\r
	57	} PCI_DEVICE_HEADER_TYPE_REGION;\r
	58	\r
	59	typedef struct {\r
	60	PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
	61	PCI_DEVICE_HEADER_TYPE_REGION Device;\r
	62	} PCI_TYPE00;\r
	63	\r
	64	typedef struct {\r
	65	UINT32 Bar[2];\r
	66	UINT8 PrimaryBus;\r
	67	UINT8 SecondaryBus;\r
	68	UINT8 SubordinateBus;\r
	69	UINT8 SecondaryLatencyTimer;\r
	70	UINT8 IoBase;\r
	71	UINT8 IoLimit;\r
	72	UINT16 SecondaryStatus;\r
	73	UINT16 MemoryBase;\r
	74	UINT16 MemoryLimit;\r
	75	UINT16 PrefetchableMemoryBase;\r
	76	UINT16 PrefetchableMemoryLimit;\r
77	UINT32 PrefetchableBaseUpper32;\r
78	UINT32 PrefetchableLimitUpper32;\r
79	UINT16 IoBaseUpper16;\r
80	UINT16 IoLimitUpper16;\r
81	UINT8 CapabilityPtr;\r
82	UINT8 Reserved[3];\r
83	UINT32 ExpansionRomBAR;\r
84	UINT8 InterruptLine;\r
85	UINT8 InterruptPin;\r
86	UINT16 BridgeControl;\r
87	} PCI_BRIDGE_CONTROL_REGISTER;\r
88	\r
89	typedef struct {\r
90	PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
91	PCI_BRIDGE_CONTROL_REGISTER Bridge;\r
92	} PCI_TYPE01;\r
93	\r
94	typedef union {\r
95	PCI_TYPE00 Device;\r
96	PCI_TYPE01 Bridge;\r
97	} PCI_TYPE_GENERIC;\r
98	\r
99	typedef struct {\r
100	UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base\r
101	// Address Register\r
102	//\r
103	UINT16 Reserved;\r
104	UINT16 SecondaryStatus; // Secondary Status\r
105	UINT8 PciBusNumber; // PCI Bus Number\r
106	UINT8 CardBusBusNumber; // CardBus Bus Number\r
107	UINT8 SubordinateBusNumber; // Subordinate Bus Number\r
108	UINT8 CardBusLatencyTimer; // CardBus Latency Timer\r
109	UINT32 MemoryBase0; // Memory Base Register 0\r
110	UINT32 MemoryLimit0; // Memory Limit Register 0\r
111	UINT32 MemoryBase1;\r
112	UINT32 MemoryLimit1;\r
113	UINT32 IoBase0;\r
114	UINT32 IoLimit0; // I/O Base Register 0\r
115	UINT32 IoBase1; // I/O Limit Register 0\r
116	UINT32 IoLimit1;\r
117	UINT8 InterruptLine; // Interrupt Line\r
118	UINT8 InterruptPin; // Interrupt Pin\r
119	UINT16 BridgeControl; // Bridge Control\r
120	} PCI_CARDBUS_CONTROL_REGISTER;\r
121	\r
122	//\r
123	// Definitions of PCI class bytes and manipulation macros.\r
124	//\r
125	#define PCI_CLASS_OLD 0x00\r
126	#define PCI_CLASS_OLD_OTHER 0x00\r
127	#define PCI_CLASS_OLD_VGA 0x01\r
128	\r
129	#define PCI_CLASS_MASS_STORAGE 0x01\r
130	#define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r
131	#define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete\r
132	#define PCI_CLASS_IDE 0x01\r
133	#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
134	#define PCI_CLASS_MASS_STORAGE_IPI 0x03\r
135	#define PCI_CLASS_MASS_STORAGE_RAID 0x04\r
136	#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r
137	\r
138	#define PCI_CLASS_NETWORK 0x02\r
139	#define PCI_CLASS_NETWORK_ETHERNET 0x00\r
140	#define PCI_CLASS_ETHERNET 0x00 // obsolete\r
141	#define PCI_CLASS_NETWORK_TOKENRING 0x01\r
142	#define PCI_CLASS_NETWORK_FDDI 0x02\r
143	#define PCI_CLASS_NETWORK_ATM 0x03\r
144	#define PCI_CLASS_NETWORK_ISDN 0x04\r
145	#define PCI_CLASS_NETWORK_OTHER 0x80\r
146	\r
147	#define PCI_CLASS_DISPLAY 0x03\r
148	#define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete\r
149	#define PCI_CLASS_DISPLAY_VGA 0x00\r
150	#define PCI_CLASS_VGA 0x00 // obsolete\r
151	#define PCI_CLASS_DISPLAY_XGA 0x01\r
152	#define PCI_CLASS_DISPLAY_3D 0x02\r
153	#define PCI_CLASS_DISPLAY_OTHER 0x80\r
154	#define PCI_CLASS_DISPLAY_GFX 0x80\r
155	#define PCI_CLASS_GFX 0x80 // obsolete\r
156	#define PCI_CLASS_BRIDGE 0x06\r
157	#define PCI_CLASS_BRIDGE_HOST 0x00\r
158	#define PCI_CLASS_BRIDGE_ISA 0x01\r
159	#define PCI_CLASS_ISA 0x01 // obsolete\r
160	#define PCI_CLASS_BRIDGE_EISA 0x02\r
161	#define PCI_CLASS_BRIDGE_MCA 0x03\r
162	#define PCI_CLASS_BRIDGE_P2P 0x04\r
163	#define PCI_CLASS_BRIDGE_PCMCIA 0x05\r
164	#define PCI_CLASS_BRIDGE_NUBUS 0x06\r
165	#define PCI_CLASS_BRIDGE_CARDBUS 0x07\r
166	#define PCI_CLASS_BRIDGE_RACEWAY 0x08\r
167	#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
168	#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete\r
169	\r
170	#define PCI_CLASS_SCC 0x07 // Simple communications controllers \r
171	#define PCI_SUBCLASS_SERIAL 0x00\r
172	#define PCI_IF_GENERIC_XT 0x00\r
173	#define PCI_IF_16450 0x01\r
174	#define PCI_IF_16550 0x02\r
175	#define PCI_IF_16650 0x03\r
176	#define PCI_IF_16750 0x04\r
177	#define PCI_IF_16850 0x05\r
178	#define PCI_IF_16950 0x06\r
179	#define PCI_SUBCLASS_PARALLEL 0x01\r
180	#define PCI_IF_PARALLEL_PORT 0x00\r
181	#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r
182	#define PCI_IF_ECP_PARALLEL_PORT 0x02\r
183	#define PCI_IF_1284_CONTROLLER 0x03\r
184	#define PCI_IF_1284_DEVICE 0xFE\r
185	#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
186	#define PCI_SUBCLASS_MODEM 0x03\r
187	#define PCI_IF_GENERIC_MODEM 0x00\r
188	#define PCI_IF_16450_MODEM 0x01\r
189	#define PCI_IF_16550_MODEM 0x02\r
190	#define PCI_IF_16650_MODEM 0x03\r
191	#define PCI_IF_16750_MODEM 0x04\r
192	#define PCI_SUBCLASS_OTHER 0x80\r
193	\r
194	#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
195	#define PCI_SUBCLASS_PIC 0x00\r
196	#define PCI_IF_8259_PIC 0x00\r
197	#define PCI_IF_ISA_PIC 0x01\r
198	#define PCI_IF_EISA_PIC 0x02\r
199	#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory. \r
200	#define PCI_IF_APIC_CONTROLLER2 0x20 \r
201	#define PCI_SUBCLASS_TIMER 0x02\r
202	#define PCI_IF_8254_TIMER 0x00\r
203	#define PCI_IF_ISA_TIMER 0x01\r
204	#define PCI_EISA_TIMER 0x02\r
205	#define PCI_SUBCLASS_RTC 0x03\r
206	#define PCI_IF_GENERIC_RTC 0x00\r
207	#define PCI_IF_ISA_RTC 0x00\r
208	#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller\r
209	\r
210	#define PCI_CLASS_INPUT_DEVICE 0x09\r
211	#define PCI_SUBCLASS_KEYBOARD 0x00\r
212	#define PCI_SUBCLASS_PEN 0x01\r
213	#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
214	#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
215	#define PCI_SUBCLASS_GAMEPORT 0x04\r
216	\r
217	#define PCI_CLASS_DOCKING_STATION 0x0A\r
218	\r
219	#define PCI_CLASS_PROCESSOR 0x0B\r
220	#define PCI_SUBCLASS_PROC_386 0x00\r
221	#define PCI_SUBCLASS_PROC_486 0x01\r
222	#define PCI_SUBCLASS_PROC_PENTIUM 0x02\r
223	#define PCI_SUBCLASS_PROC_ALPHA 0x10\r
224	#define PCI_SUBCLASS_PROC_POWERPC 0x20\r
225	#define PCI_SUBCLASS_PROC_MIPS 0x30\r
226	#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor\r
227	\r
228	#define PCI_CLASS_SERIAL 0x0C\r
229	#define PCI_CLASS_SERIAL_FIREWIRE 0x00\r
230	#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r
231	#define PCI_CLASS_SERIAL_SSA 0x02\r
232	#define PCI_CLASS_SERIAL_USB 0x03\r
233	#define PCI_IF_EHCI 0x20\r
234	#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
235	#define PCI_CLASS_SERIAL_SMB 0x05\r
236	\r
237	#define PCI_CLASS_WIRELESS 0x0D\r
238	#define PCI_SUBCLASS_IRDA 0x00\r
239	#define PCI_SUBCLASS_IR 0x01\r
240	#define PCI_SUBCLASS_RF 0x02\r
241	\r
242	#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
243	\r
244	#define PCI_CLASS_SATELLITE 0x0F\r
245	#define PCI_SUBCLASS_TV 0x01\r
246	#define PCI_SUBCLASS_AUDIO 0x02\r
247	#define PCI_SUBCLASS_VOICE 0x03\r
248	#define PCI_SUBCLASS_DATA 0x04\r
249	\r
250	#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller\r
251	#define PCI_SUBCLASS_NET_COMPUT 0x00\r
252	#define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r
253	\r
254	#define PCI_CLASS_DPIO 0x11\r
255	\r
256	#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
257	#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
258	#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
259	\r
260	#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
261	#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)\r
262	#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)\r
263	#define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)\r
264	#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
265	#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
266	#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
267	#define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)\r
268	#define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)\r
269	#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)\r
270	#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)\r
271	#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)\r
272	#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
273	#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
274	\r
275	#define HEADER_TYPE_DEVICE 0x00\r
276	#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
277	#define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r
278	\r
279	#define HEADER_TYPE_MULTI_FUNCTION 0x80\r
280	#define HEADER_LAYOUT_CODE 0x7f\r
281	\r
282	#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
283	#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
284	#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
285	\r
286	#define PCI_DEVICE_ROMBAR 0x30\r
287	#define PCI_BRIDGE_ROMBAR 0x38\r
288	\r
289	#define PCI_MAX_BAR 0x0006\r
290	#define PCI_MAX_CONFIG_OFFSET 0x0100\r
291	\r
292	#define PCI_VENDOR_ID_OFFSET 0x00\r
293	#define PCI_DEVICE_ID_OFFSET 0x02\r
294	#define PCI_COMMAND_OFFSET 0x04\r
295	#define PCI_PRIMARY_STATUS_OFFSET 0x06\r
296	#define PCI_REVISION_ID_OFFSET 0x08\r
297	#define PCI_CLASSCODE_OFFSET 0x09\r
298	#define PCI_CACHELINE_SIZE_OFFSET 0x0C\r
299	#define PCI_LATENCY_TIMER_OFFSET 0x0D\r
300	#define PCI_HEADER_TYPE_OFFSET 0x0E\r
301	#define PCI_BIST_OFFSET 0x0F\r
302	#define PCI_BASE_ADDRESSREG_OFFSET 0x10\r
303	#define PCI_CARDBUS_CIS_OFFSET 0x28\r
304	#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id\r
305	#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r
306	#define PCI_SID_OFFSET 0x2E // SubSystem ID\r
307	#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r
308	#define PCI_EXPANSION_ROM_BASE 0x30\r
309	#define PCI_CAPBILITY_POINTER_OFFSET 0x34\r
310	#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register\r
311	#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register\r
312	#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register\r
313	#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register\r
314	\r
315	#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E\r
316	#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E\r
317	\r
318	#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18\r
319	#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19\r
320	#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a\r
321	\r
322	//\r
323	// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
324	//\r
325	#define PCI_INT_LINE_UNKNOWN 0xFF \r
326	\r
327	typedef union {\r
328	struct {\r
329	UINT32 Reg : 8;\r
330	UINT32 Func : 3;\r
331	UINT32 Dev : 5;\r
332	UINT32 Bus : 8;\r
333	UINT32 Reserved : 7;\r
334	UINT32 Enable : 1;\r
335	} Bits;\r
336	UINT32 Uint32;\r
337	} PCI_CONFIG_ACCESS_CF8;\r
338	\r
339	#pragma pack()\r
340	\r
341	#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
342	#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')\r
343	#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
344	#define PCI_CODE_TYPE_EFI_IMAGE 0x03\r
345	#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001\r
346	\r
347	#define EFI_PCI_COMMAND_IO_SPACE 0x0001\r
348	#define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002\r
349	#define EFI_PCI_COMMAND_BUS_MASTER 0x0004\r
350	#define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008\r
351	#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010\r
352	#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020\r
353	#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040\r
354	#define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080\r
355	#define EFI_PCI_COMMAND_SERR 0x0100\r
356	#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200\r
357	\r
358	#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001\r
359	#define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002\r
360	#define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004\r
361	#define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008\r
362	#define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010\r
363	#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020\r
364	#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040\r
365	#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080\r
366	#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100\r
367	#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200\r
368	#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400\r
369	#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800\r
370	\r
371	//\r
372	// Following are the PCI-CARDBUS bridge control bit\r
373	//\r
374	#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080\r
375	#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100\r
376	#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200\r
377	#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400\r
378	\r
379	//\r
380	// Following are the PCI status control bit\r
381	//\r
382	#define EFI_PCI_STATUS_CAPABILITY 0x0010\r
383	#define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020\r
384	#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080\r
385	#define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100\r
386	\r
387	#define EFI_PCI_CAPABILITY_PTR 0x34\r
388	#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
389	\r
390	#pragma pack(1)\r
391	typedef struct {\r
392	UINT16 Signature; // 0xaa55\r
393	UINT8 Reserved[0x16];\r
394	UINT16 PcirOffset;\r
395	} PCI_EXPANSION_ROM_HEADER;\r
396	\r
397	typedef struct {\r
398	UINT16 Signature; // 0xaa55\r
399	UINT8 Size512;\r
400	UINT8 InitEntryPoint[3];\r
401	UINT8 Reserved[0x12];\r
402	UINT16 PcirOffset;\r
403	} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
404	\r
405	typedef struct {\r
406	UINT32 Signature; // "PCIR"\r
407	UINT16 VendorId;\r
408	UINT16 DeviceId;\r
409	UINT16 Reserved0;\r
410	UINT16 Length;\r
411	UINT8 Revision;\r
412	UINT8 ClassCode[3];\r
413	UINT16 ImageLength;\r
414	UINT16 CodeRevision;\r
415	UINT8 CodeType;\r
416	UINT8 Indicator;\r
417	UINT16 Reserved1;\r
418	} PCI_DATA_STRUCTURE;\r
419	\r
420	//\r
421	// PCI Capability List IDs and records\r
422	//\r
423	#define EFI_PCI_CAPABILITY_ID_PMI 0x01\r
424	#define EFI_PCI_CAPABILITY_ID_AGP 0x02\r
425	#define EFI_PCI_CAPABILITY_ID_VPD 0x03\r
426	#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
427	#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
428	#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
429	#define EFI_PCI_CAPABILITY_ID_PCIX 0x07\r
430	\r
431	typedef struct {\r
432	UINT8 CapabilityID;\r
433	UINT8 NextItemPtr;\r
434	} EFI_PCI_CAPABILITY_HDR;\r
435	\r
436	//\r
437	// Capability EFI_PCI_CAPABILITY_ID_PMI\r
438	//\r
439	typedef struct {\r
440	EFI_PCI_CAPABILITY_HDR Hdr;\r
441	UINT16 PMC;\r
442	UINT16 PMCSR;\r
443	UINT8 BridgeExtention;\r
444	UINT8 Data;\r
445	} EFI_PCI_CAPABILITY_PMI;\r
446	\r
447	//\r
448	// Capability EFI_PCI_CAPABILITY_ID_AGP\r
449	//\r
450	typedef struct {\r
451	EFI_PCI_CAPABILITY_HDR Hdr;\r
452	UINT8 Rev;\r
453	UINT8 Reserved;\r
454	UINT32 Status;\r
455	UINT32 Command;\r
456	} EFI_PCI_CAPABILITY_AGP;\r
457	\r
458	//\r
459	// Capability EFI_PCI_CAPABILITY_ID_VPD\r
460	//\r
461	typedef struct {\r
462	EFI_PCI_CAPABILITY_HDR Hdr;\r
463	UINT16 AddrReg;\r
464	UINT32 DataReg;\r
465	} EFI_PCI_CAPABILITY_VPD;\r
466	\r
467	//\r
468	// Capability EFI_PCI_CAPABILITY_ID_SLOTID\r
469	//\r
470	typedef struct {\r
471	EFI_PCI_CAPABILITY_HDR Hdr;\r
472	UINT8 ExpnsSlotReg;\r
473	UINT8 ChassisNo;\r
474	} EFI_PCI_CAPABILITY_SLOTID;\r
475	\r
476	//\r
477	// Capability EFI_PCI_CAPABILITY_ID_MSI\r
478	//\r
479	typedef struct {\r
480	EFI_PCI_CAPABILITY_HDR Hdr;\r
481	UINT16 MsgCtrlReg;\r
482	UINT32 MsgAddrReg;\r
483	UINT16 MsgDataReg;\r
484	} EFI_PCI_CAPABILITY_MSI32;\r
485	\r
486	typedef struct {\r
487	EFI_PCI_CAPABILITY_HDR Hdr;\r
488	UINT16 MsgCtrlReg;\r
489	UINT32 MsgAddrRegLsdw;\r
490	UINT32 MsgAddrRegMsdw;\r
491	UINT16 MsgDataReg;\r
492	} EFI_PCI_CAPABILITY_MSI64;\r
493	\r
494	//\r
495	// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG\r
496	//\r
497	typedef struct {\r
498	EFI_PCI_CAPABILITY_HDR Hdr;\r
499	//\r
500	// not finished - fields need to go here\r
501	//\r
502	} EFI_PCI_CAPABILITY_HOTPLUG;\r
503	\r
504	//\r
505	// Capability EFI_PCI_CAPABILITY_ID_PCIX\r
506	//\r
507	typedef struct {\r
508	EFI_PCI_CAPABILITY_HDR Hdr;\r
509	UINT16 CommandReg;\r
510	UINT32 StatusReg;\r
511	} EFI_PCI_CAPABILITY_PCIX;\r
512	\r
513	typedef struct {\r
514	EFI_PCI_CAPABILITY_HDR Hdr;\r
515	UINT16 SecStatusReg;\r
516	UINT32 StatusReg;\r
517	UINT32 SplitTransCtrlRegUp;\r
518	UINT32 SplitTransCtrlRegDn;\r
519	} EFI_PCI_CAPABILITY_PCIX_BRDG;\r
520	\r
521	#define DEVICE_ID_NOCARE 0xFFFF\r
522	\r
523	#define PCI_ACPI_UNUSED 0\r
524	#define PCI_BAR_NOCHANGE 0\r
525	#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL\r
526	#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL\r
527	#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r
528	#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r
529	\r
530	#define PCI_BAR_IDX0 0x00\r
531	#define PCI_BAR_IDX1 0x01\r
532	#define PCI_BAR_IDX2 0x02\r
533	#define PCI_BAR_IDX3 0x03\r
534	#define PCI_BAR_IDX4 0x04\r
535	#define PCI_BAR_IDX5 0x05\r
536	#define PCI_BAR_ALL 0xFF\r
537	\r
538	#pragma pack(pop)\r
539	\r
540	#endif\r