| a7ed1e2e |
1 | /** @file\r |
| 2 | Support for PCI 2.2 standard.\r |
| 3 | \r |
| bc14bdb3 |
4 | This file includes the definitions in the following specifications,\r |
| 5 | PCI Local Bus Specification, 2.0\r |
| 6 | PCI-to-PCI Bridge Architecture Specification,\r |
| 7 | PC Card Standard, 8.0\r |
| 8 | \r |
| 9 | Copyright (c) 2006 - 2008, Intel Corporation \r |
| a7ed1e2e |
10 | All rights reserved. This program and the accompanying materials \r |
| 11 | are licensed and made available under the terms and conditions of the BSD License \r |
| 12 | which accompanies this distribution. The full text of the license may be found at \r |
| 13 | http://opensource.org/licenses/bsd-license.php \r |
| 14 | \r |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 17 | \r |
| a7ed1e2e |
18 | **/\r |
| 19 | \r |
| 42eedea9 |
20 | #ifndef _PCI22_H_\r |
| 21 | #define _PCI22_H_\r |
| a7ed1e2e |
22 | \r |
| 23 | #define PCI_MAX_SEGMENT 0\r |
| a7ed1e2e |
24 | #define PCI_MAX_BUS 255\r |
| a7ed1e2e |
25 | #define PCI_MAX_DEVICE 31\r |
| 26 | #define PCI_MAX_FUNC 7\r |
| 27 | \r |
| a7ed1e2e |
28 | \r |
| a7ed1e2e |
29 | typedef struct {\r |
| 30 | UINT16 VendorId;\r |
| 31 | UINT16 DeviceId;\r |
| 32 | UINT16 Command;\r |
| 33 | UINT16 Status;\r |
| 34 | UINT8 RevisionID;\r |
| 35 | UINT8 ClassCode[3];\r |
| 36 | UINT8 CacheLineSize;\r |
| 37 | UINT8 LatencyTimer;\r |
| 38 | UINT8 HeaderType;\r |
| 39 | UINT8 BIST;\r |
| 40 | } PCI_DEVICE_INDEPENDENT_REGION;\r |
| 41 | \r |
| 42 | typedef struct {\r |
| 43 | UINT32 Bar[6];\r |
| 44 | UINT32 CISPtr;\r |
| 45 | UINT16 SubsystemVendorID;\r |
| 46 | UINT16 SubsystemID;\r |
| 47 | UINT32 ExpansionRomBar;\r |
| 48 | UINT8 CapabilityPtr;\r |
| 49 | UINT8 Reserved1[3];\r |
| 50 | UINT32 Reserved2;\r |
| 51 | UINT8 InterruptLine;\r |
| 52 | UINT8 InterruptPin;\r |
| 53 | UINT8 MinGnt;\r |
| 54 | UINT8 MaxLat;\r |
| 55 | } PCI_DEVICE_HEADER_TYPE_REGION;\r |
| 56 | \r |
| 57 | typedef struct {\r |
| 58 | PCI_DEVICE_INDEPENDENT_REGION Hdr;\r |
| 59 | PCI_DEVICE_HEADER_TYPE_REGION Device;\r |
| 60 | } PCI_TYPE00;\r |
| 61 | \r |
| bc14bdb3 |
62 | ///\r |
| 63 | /// defined in PCI-to-PCI Bridge Architecture Specification\r |
| 64 | ///\r |
| a7ed1e2e |
65 | typedef struct {\r |
| 66 | UINT32 Bar[2];\r |
| 67 | UINT8 PrimaryBus;\r |
| 68 | UINT8 SecondaryBus;\r |
| 69 | UINT8 SubordinateBus;\r |
| 70 | UINT8 SecondaryLatencyTimer;\r |
| 71 | UINT8 IoBase;\r |
| 72 | UINT8 IoLimit;\r |
| 73 | UINT16 SecondaryStatus;\r |
| 74 | UINT16 MemoryBase;\r |
| 75 | UINT16 MemoryLimit;\r |
| 76 | UINT16 PrefetchableMemoryBase;\r |
| 77 | UINT16 PrefetchableMemoryLimit;\r |
| 78 | UINT32 PrefetchableBaseUpper32;\r |
| 79 | UINT32 PrefetchableLimitUpper32;\r |
| 80 | UINT16 IoBaseUpper16;\r |
| 81 | UINT16 IoLimitUpper16;\r |
| 82 | UINT8 CapabilityPtr;\r |
| 83 | UINT8 Reserved[3];\r |
| 84 | UINT32 ExpansionRomBAR;\r |
| 85 | UINT8 InterruptLine;\r |
| 86 | UINT8 InterruptPin;\r |
| 87 | UINT16 BridgeControl;\r |
| 88 | } PCI_BRIDGE_CONTROL_REGISTER;\r |
| 89 | \r |
| 90 | typedef struct {\r |
| 91 | PCI_DEVICE_INDEPENDENT_REGION Hdr;\r |
| 92 | PCI_BRIDGE_CONTROL_REGISTER Bridge;\r |
| 93 | } PCI_TYPE01;\r |
| 94 | \r |
| 95 | typedef union {\r |
| 96 | PCI_TYPE00 Device;\r |
| 97 | PCI_TYPE01 Bridge;\r |
| 98 | } PCI_TYPE_GENERIC;\r |
| 99 | \r |
| bc14bdb3 |
100 | /// \r |
| 101 | /// CardBus Conroller Configuration Space, defined in PC Card Standard. 8.0\r |
| 102 | ///\r |
| a7ed1e2e |
103 | typedef struct {\r |
| bc14bdb3 |
104 | UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base\r |
| 105 | UINT8 Cap_Ptr;\r |
| 106 | UINT8 Reserved;\r |
| 107 | UINT16 SecondaryStatus; ///< Secondary Status\r |
| 108 | UINT8 PciBusNumber; ///< PCI Bus Number\r |
| 109 | UINT8 CardBusBusNumber; ///< CardBus Bus Number\r |
| 110 | UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r |
| 111 | UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r |
| 112 | UINT32 MemoryBase0; ///< Memory Base Register 0\r |
| 113 | UINT32 MemoryLimit0; ///< Memory Limit Register 0\r |
| a7ed1e2e |
114 | UINT32 MemoryBase1;\r |
| 115 | UINT32 MemoryLimit1;\r |
| 116 | UINT32 IoBase0;\r |
| bc14bdb3 |
117 | UINT32 IoLimit0; ///< I/O Base Register 0\r |
| 118 | UINT32 IoBase1; ///< I/O Limit Register 0\r |
| a7ed1e2e |
119 | UINT32 IoLimit1;\r |
| bc14bdb3 |
120 | UINT8 InterruptLine; ///< Interrupt Line\r |
| 121 | UINT8 InterruptPin; ///< Interrupt Pin\r |
| 122 | UINT16 BridgeControl; ///< Bridge Control\r |
| a7ed1e2e |
123 | } PCI_CARDBUS_CONTROL_REGISTER;\r |
| 124 | \r |
| 54569f0f |
125 | //\r |
| 126 | // Definitions of PCI class bytes and manipulation macros.\r |
| 127 | //\r |
| a7ed1e2e |
128 | #define PCI_CLASS_OLD 0x00\r |
| bc14bdb3 |
129 | #define PCI_CLASS_OLD_OTHER 0x00\r |
| 130 | #define PCI_CLASS_OLD_VGA 0x01\r |
| a7ed1e2e |
131 | \r |
| 132 | #define PCI_CLASS_MASS_STORAGE 0x01\r |
| bc14bdb3 |
133 | #define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r |
| 134 | #define PCI_CLASS_MASS_STORAGE_IDE 0x01\r |
| 135 | #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r |
| 136 | #define PCI_CLASS_MASS_STORAGE_IPI 0x03\r |
| 137 | #define PCI_CLASS_MASS_STORAGE_RAID 0x04\r |
| 138 | #define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r |
| a7ed1e2e |
139 | \r |
| 140 | #define PCI_CLASS_NETWORK 0x02\r |
| bc14bdb3 |
141 | #define PCI_CLASS_NETWORK_ETHERNET 0x00 \r |
| 142 | #define PCI_CLASS_NETWORK_TOKENRING 0x01\r |
| 143 | #define PCI_CLASS_NETWORK_FDDI 0x02\r |
| 144 | #define PCI_CLASS_NETWORK_ATM 0x03\r |
| 145 | #define PCI_CLASS_NETWORK_ISDN 0x04\r |
| 146 | #define PCI_CLASS_NETWORK_OTHER 0x80\r |
| a7ed1e2e |
147 | \r |
| 148 | #define PCI_CLASS_DISPLAY 0x03\r |
| bc14bdb3 |
149 | #define PCI_CLASS_DISPLAY_VGA 0x00\r |
| 150 | #define PCI_IF_VGA_VGA 0x00\r |
| 151 | #define PCI_IF_VGA_8514 0x01\r |
| 152 | #define PCI_CLASS_DISPLAY_XGA 0x01\r |
| 153 | #define PCI_CLASS_DISPLAY_3D 0x02\r |
| 154 | #define PCI_CLASS_DISPLAY_OTHER 0x80 \r |
| 155 | #define PCI_CLASS_DISPLAY_GFX 0x80\r |
| 156 | \r |
| 157 | #define PCI_CLASS_MEDIA 0x04\r |
| 158 | #define PCI_CLASS_MEDIA_VIDEO 0x00\r |
| 159 | #define PCI_CLASS_MEDIA_AUDIO 0x01\r |
| 160 | #define PCI_CLASS_MEDIA_TELEPHONE 0x02\r |
| 161 | #define PCI_CLASS_MEDIA_OTHER 0x80\r |
| 162 | \r |
| 163 | #define PCI_CLASS_MEMORY_CONTROLLER 0x05\r |
| 164 | #define PCI_CLASS_MEMORY_RAM 0x00\r |
| 165 | #define PCI_CLASS_MEMORY_FLASH 0x01\r |
| 166 | #define PCI_CLASS_MEMORY_OTHER 0x80\r |
| 167 | \r |
| a7ed1e2e |
168 | #define PCI_CLASS_BRIDGE 0x06\r |
| bc14bdb3 |
169 | #define PCI_CLASS_BRIDGE_HOST 0x00\r |
| 170 | #define PCI_CLASS_BRIDGE_ISA 0x01\r |
| 171 | #define PCI_CLASS_BRIDGE_EISA 0x02\r |
| 172 | #define PCI_CLASS_BRIDGE_MCA 0x03\r |
| 173 | #define PCI_CLASS_BRIDGE_P2P 0x04\r |
| 174 | #define PCI_IF_BRIDGE_P2P 0x00\r |
| 175 | #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r |
| 176 | #define PCI_CLASS_BRIDGE_PCMCIA 0x05\r |
| 177 | #define PCI_CLASS_BRIDGE_NUBUS 0x06\r |
| 178 | #define PCI_CLASS_BRIDGE_CARDBUS 0x07\r |
| 179 | #define PCI_CLASS_BRIDGE_RACEWAY 0x08\r |
| 180 | #define PCI_CLASS_BRIDGE_OTHER 0x80\r |
| 181 | #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r |
| 182 | \r |
| 183 | #define PCI_CLASS_SCC 0x07 ///< Simple communications controllers \r |
| 184 | #define PCI_SUBCLASS_SERIAL 0x00\r |
| 185 | #define PCI_IF_GENERIC_XT 0x00\r |
| 186 | #define PCI_IF_16450 0x01\r |
| 187 | #define PCI_IF_16550 0x02\r |
| 188 | #define PCI_IF_16650 0x03\r |
| 189 | #define PCI_IF_16750 0x04\r |
| 190 | #define PCI_IF_16850 0x05\r |
| 191 | #define PCI_IF_16950 0x06\r |
| 192 | #define PCI_SUBCLASS_PARALLEL 0x01\r |
| 193 | #define PCI_IF_PARALLEL_PORT 0x00\r |
| 194 | #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r |
| 195 | #define PCI_IF_ECP_PARALLEL_PORT 0x02\r |
| 196 | #define PCI_IF_1284_CONTROLLER 0x03\r |
| 197 | #define PCI_IF_1284_DEVICE 0xFE\r |
| 198 | #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r |
| 199 | #define PCI_SUBCLASS_MODEM 0x03\r |
| 200 | #define PCI_IF_GENERIC_MODEM 0x00\r |
| 201 | #define PCI_IF_16450_MODEM 0x01\r |
| 202 | #define PCI_IF_16550_MODEM 0x02\r |
| 203 | #define PCI_IF_16650_MODEM 0x03\r |
| 204 | #define PCI_IF_16750_MODEM 0x04\r |
| 205 | #define PCI_SUBCLASS_SCC_OTHER 0x80\r |
| a7ed1e2e |
206 | \r |
| 207 | #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r |
| bc14bdb3 |
208 | #define PCI_SUBCLASS_PIC 0x00\r |
| 209 | #define PCI_IF_8259_PIC 0x00\r |
| 210 | #define PCI_IF_ISA_PIC 0x01\r |
| 211 | #define PCI_IF_EISA_PIC 0x02\r |
| 212 | #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory. \r |
| 213 | #define PCI_IF_APIC_CONTROLLER2 0x20 \r |
| 214 | #define PCI_SUBCLASS_DMA 0x01\r |
| 215 | #define PCI_IF_8237_DMA 0x00\r |
| 216 | #define PCI_IF_ISA_DMA 0x01\r |
| 217 | #define PCI_IF_EISA_DMA 0x02\r |
| 218 | #define PCI_SUBCLASS_TIMER 0x02\r |
| 219 | #define PCI_IF_8254_TIMER 0x00\r |
| 220 | #define PCI_IF_ISA_TIMER 0x01\r |
| 221 | #define PCI_IF_EISA_TIMER 0x02\r |
| 222 | #define PCI_SUBCLASS_RTC 0x03\r |
| 223 | #define PCI_IF_GENERIC_RTC 0x00\r |
| 224 | #define PCI_IF_ISA_RTC 0x00\r |
| 225 | #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r |
| 226 | #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r |
| a7ed1e2e |
227 | \r |
| 228 | #define PCI_CLASS_INPUT_DEVICE 0x09\r |
| bc14bdb3 |
229 | #define PCI_SUBCLASS_KEYBOARD 0x00\r |
| 230 | #define PCI_SUBCLASS_PEN 0x01\r |
| 231 | #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r |
| 232 | #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r |
| 233 | #define PCI_SUBCLASS_GAMEPORT 0x04\r |
| 234 | #define PCI_IF_GAMEPORT 0x00\r |
| 235 | #define PCI_IF_GAMEPORT1 0x01\r |
| 236 | #define PCI_SUBCLASS_INPUT_OTHER 0x80\r |
| a7ed1e2e |
237 | \r |
| 238 | #define PCI_CLASS_DOCKING_STATION 0x0A\r |
| 239 | \r |
| 240 | #define PCI_CLASS_PROCESSOR 0x0B\r |
| bc14bdb3 |
241 | #define PCI_SUBCLASS_PROC_386 0x00\r |
| 242 | #define PCI_SUBCLASS_PROC_486 0x01\r |
| 243 | #define PCI_SUBCLASS_PROC_PENTIUM 0x02\r |
| 244 | #define PCI_SUBCLASS_PROC_ALPHA 0x10\r |
| 245 | #define PCI_SUBCLASS_PROC_POWERPC 0x20\r |
| 246 | #define PCI_SUBCLASS_PROC_MIPS 0x30\r |
| 247 | #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r |
| a7ed1e2e |
248 | \r |
| 249 | #define PCI_CLASS_SERIAL 0x0C\r |
| bc14bdb3 |
250 | #define PCI_CLASS_SERIAL_FIREWIRE 0x00\r |
| 251 | #define PCI_IF_1394 0x00\r |
| 252 | #define PCI_IF_1394_OPEN_HCI 0x10\r |
| 253 | #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r |
| 254 | #define PCI_CLASS_SERIAL_SSA 0x02\r |
| 255 | #define PCI_CLASS_SERIAL_USB 0x03\r |
| 256 | #define PCI_IF_UHCI 0x00\r |
| 257 | #define PCI_IF_OHCI 0x10\r |
| 258 | #define PCI_IF_USB_OTHER 0x80\r |
| 259 | #define PCI_IF_USB_DEVICE 0xFE\r |
| 260 | #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r |
| 261 | #define PCI_CLASS_SERIAL_SMB 0x05\r |
| a7ed1e2e |
262 | \r |
| 263 | #define PCI_CLASS_WIRELESS 0x0D\r |
| bc14bdb3 |
264 | #define PCI_SUBCLASS_IRDA 0x00\r |
| 265 | #define PCI_SUBCLASS_IR 0x01\r |
| 266 | #define PCI_SUBCLASS_RF 0x02\r |
| 267 | #define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r |
| a7ed1e2e |
268 | \r |
| 269 | #define PCI_CLASS_INTELLIGENT_IO 0x0E\r |
| 270 | \r |
| 271 | #define PCI_CLASS_SATELLITE 0x0F\r |
| bc14bdb3 |
272 | #define PCI_SUBCLASS_TV 0x01\r |
| 273 | #define PCI_SUBCLASS_AUDIO 0x02\r |
| 274 | #define PCI_SUBCLASS_VOICE 0x03\r |
| 275 | #define PCI_SUBCLASS_DATA 0x04\r |
| a7ed1e2e |
276 | \r |
| bc14bdb3 |
277 | #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r |
| 278 | #define PCI_SUBCLASS_NET_COMPUT 0x00\r |
| 279 | #define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r |
| 280 | #define PCI_SUBCLASS_SECURITY_OTHER 0x80\r |
| a7ed1e2e |
281 | \r |
| 282 | #define PCI_CLASS_DPIO 0x11\r |
| bc14bdb3 |
283 | #define PCI_SUBCLASS_DPIO 0x00\r |
| 284 | #define PCI_SUBCLASS_DPIO_OTHER 0x80\r |
| a7ed1e2e |
285 | \r |
| 286 | #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r |
| 287 | #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r |
| 288 | #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r |
| 289 | \r |
| 290 | #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r |
| 291 | #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)\r |
| 292 | #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)\r |
| 293 | #define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)\r |
| 294 | #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r |
| 295 | #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r |
| 296 | #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r |
| 297 | #define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)\r |
| 298 | #define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)\r |
| 299 | #define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)\r |
| 300 | #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)\r |
| 301 | #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)\r |
| 302 | #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r |
| 303 | #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r |
| 304 | \r |
| bc14bdb3 |
305 | //\r |
| 306 | // the definition of Header Type \r |
| 307 | //\r |
| a7ed1e2e |
308 | #define HEADER_TYPE_DEVICE 0x00\r |
| 309 | #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r |
| 310 | #define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r |
| a7ed1e2e |
311 | #define HEADER_TYPE_MULTI_FUNCTION 0x80\r |
| bc14bdb3 |
312 | //\r |
| 313 | // Mask of Header type\r |
| 314 | //\r |
| a7ed1e2e |
315 | #define HEADER_LAYOUT_CODE 0x7f\r |
| 316 | \r |
| 317 | #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r |
| 318 | #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r |
| 319 | #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r |
| 320 | \r |
| bc14bdb3 |
321 | ///\r |
| 322 | /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,\r |
| 323 | ///\r |
| a7ed1e2e |
324 | #define PCI_BRIDGE_ROMBAR 0x38\r |
| 325 | \r |
| 326 | #define PCI_MAX_BAR 0x0006\r |
| 327 | #define PCI_MAX_CONFIG_OFFSET 0x0100\r |
| 328 | \r |
| 329 | #define PCI_VENDOR_ID_OFFSET 0x00\r |
| 330 | #define PCI_DEVICE_ID_OFFSET 0x02\r |
| 331 | #define PCI_COMMAND_OFFSET 0x04\r |
| 332 | #define PCI_PRIMARY_STATUS_OFFSET 0x06\r |
| 333 | #define PCI_REVISION_ID_OFFSET 0x08\r |
| 334 | #define PCI_CLASSCODE_OFFSET 0x09\r |
| 335 | #define PCI_CACHELINE_SIZE_OFFSET 0x0C\r |
| 336 | #define PCI_LATENCY_TIMER_OFFSET 0x0D\r |
| 337 | #define PCI_HEADER_TYPE_OFFSET 0x0E\r |
| 338 | #define PCI_BIST_OFFSET 0x0F\r |
| 339 | #define PCI_BASE_ADDRESSREG_OFFSET 0x10\r |
| 340 | #define PCI_CARDBUS_CIS_OFFSET 0x28\r |
| bc14bdb3 |
341 | #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r |
| a7ed1e2e |
342 | #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r |
| bc14bdb3 |
343 | #define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r |
| a7ed1e2e |
344 | #define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r |
| 345 | #define PCI_EXPANSION_ROM_BASE 0x30\r |
| 346 | #define PCI_CAPBILITY_POINTER_OFFSET 0x34\r |
| bc14bdb3 |
347 | #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r |
| 348 | #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r |
| 349 | #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r |
| 350 | #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r |
| a7ed1e2e |
351 | \r |
| 54569f0f |
352 | //\r |
| 353 | // defined in PCI-to-PCI Bridge Architecture Specification\r |
| 354 | //\r |
| bc14bdb3 |
355 | #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r |
| 356 | #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r |
| 357 | #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r |
| 358 | #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E \r |
| 359 | #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E \r |
| a7ed1e2e |
360 | \r |
| bc14bdb3 |
361 | ///\r |
| 362 | /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r |
| 363 | ///\r |
| a7ed1e2e |
364 | #define PCI_INT_LINE_UNKNOWN 0xFF \r |
| 365 | \r |
| 366 | typedef union {\r |
| 367 | struct {\r |
| 368 | UINT32 Reg : 8;\r |
| 369 | UINT32 Func : 3;\r |
| 370 | UINT32 Dev : 5;\r |
| 371 | UINT32 Bus : 8;\r |
| 372 | UINT32 Reserved : 7;\r |
| 373 | UINT32 Enable : 1;\r |
| 374 | } Bits;\r |
| 375 | UINT32 Uint32;\r |
| 376 | } PCI_CONFIG_ACCESS_CF8;\r |
| 377 | \r |
| bc14bdb3 |
378 | #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r |
| 379 | #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r |
| 380 | #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r |
| 381 | #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r |
| 382 | #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r |
| 383 | #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r |
| 384 | #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r |
| 385 | #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r |
| 386 | #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r |
| 387 | #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r |
| a7ed1e2e |
388 | \r |
| 54569f0f |
389 | //\r |
| 390 | // defined in PCI-to-PCI Bridge Architecture Specification\r |
| 391 | //\r |
| bc14bdb3 |
392 | #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\r |
| 393 | #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\r |
| 394 | #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\r |
| 395 | #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008\r |
| 396 | #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010\r |
| 397 | #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020\r |
| 398 | #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040\r |
| 399 | #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080\r |
| 400 | #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100\r |
| 401 | #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200\r |
| 402 | #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\r |
| 403 | #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\r |
| 404 | \r |
| 54569f0f |
405 | //\r |
| 406 | // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r |
| 407 | //\r |
| bc14bdb3 |
408 | #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r |
| 409 | #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r |
| 410 | #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r |
| 411 | #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r |
| a7ed1e2e |
412 | \r |
| 413 | //\r |
| 414 | // Following are the PCI status control bit\r |
| 415 | //\r |
| bc14bdb3 |
416 | #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r |
| 417 | #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r |
| 418 | #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r |
| 419 | #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r |
| a7ed1e2e |
420 | \r |
| bc14bdb3 |
421 | ///\r |
| 422 | /// defined in PC Card Standard\r |
| 423 | ///\r |
| a7ed1e2e |
424 | #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r |
| 425 | \r |
| a7ed1e2e |
426 | //\r |
| 427 | // PCI Capability List IDs and records\r |
| 428 | //\r |
| 429 | #define EFI_PCI_CAPABILITY_ID_PMI 0x01\r |
| 430 | #define EFI_PCI_CAPABILITY_ID_AGP 0x02\r |
| 431 | #define EFI_PCI_CAPABILITY_ID_VPD 0x03\r |
| 432 | #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r |
| 433 | #define EFI_PCI_CAPABILITY_ID_MSI 0x05\r |
| 434 | #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r |
| 54569f0f |
435 | \r |
| a7ed1e2e |
436 | typedef struct {\r |
| 437 | UINT8 CapabilityID;\r |
| 438 | UINT8 NextItemPtr;\r |
| 439 | } EFI_PCI_CAPABILITY_HDR;\r |
| 440 | \r |
| 1bc5d021 |
441 | ///\r |
| bc14bdb3 |
442 | /// Capability EFI_PCI_CAPABILITY_ID_PMI, defined in PCI Power Management Interface Specifiction\r |
| 1bc5d021 |
443 | ///\r |
| a7ed1e2e |
444 | typedef struct {\r |
| 445 | EFI_PCI_CAPABILITY_HDR Hdr;\r |
| 446 | UINT16 PMC;\r |
| 447 | UINT16 PMCSR;\r |
| 448 | UINT8 BridgeExtention;\r |
| 449 | UINT8 Data;\r |
| 450 | } EFI_PCI_CAPABILITY_PMI;\r |
| 451 | \r |
| 1bc5d021 |
452 | ///\r |
| bc14bdb3 |
453 | /// Capability EFI_PCI_CAPABILITY_ID_AGP, defined in Accelerated Graphics Port Interface Specification\r |
| 1bc5d021 |
454 | ///\r |
| a7ed1e2e |
455 | typedef struct {\r |
| 456 | EFI_PCI_CAPABILITY_HDR Hdr;\r |
| 457 | UINT8 Rev;\r |
| 458 | UINT8 Reserved;\r |
| 459 | UINT32 Status;\r |
| 460 | UINT32 Command;\r |
| 461 | } EFI_PCI_CAPABILITY_AGP;\r |
| 462 | \r |
| 1bc5d021 |
463 | ///\r |
| bc14bdb3 |
464 | /// Capability EFI_PCI_CAPABILITY_ID_VPD, in PCI2.2 Spec.\r |
| 1bc5d021 |
465 | ///\r |
| a7ed1e2e |
466 | typedef struct {\r |
| 467 | EFI_PCI_CAPABILITY_HDR Hdr;\r |
| 468 | UINT16 AddrReg;\r |
| 469 | UINT32 DataReg;\r |
| 470 | } EFI_PCI_CAPABILITY_VPD;\r |
| 471 | \r |
| 1bc5d021 |
472 | ///\r |
| bc14bdb3 |
473 | /// Capability EFI_PCI_CAPABILITY_ID_SLOTID, defined in PCI-to-PCI Bridge Architeture Specification\r |
| 1bc5d021 |
474 | ///\r |
| a7ed1e2e |
475 | typedef struct {\r |
| 476 | EFI_PCI_CAPABILITY_HDR Hdr;\r |
| 477 | UINT8 ExpnsSlotReg;\r |
| 478 | UINT8 ChassisNo;\r |
| 479 | } EFI_PCI_CAPABILITY_SLOTID;\r |
| 480 | \r |
| 1bc5d021 |
481 | ///\r |
| bc14bdb3 |
482 | /// Capability EFI_PCI_CAPABILITY_ID_MSI, defined in PCI2.2\r |
| 1bc5d021 |
483 | ///\r |
| a7ed1e2e |
484 | typedef struct {\r |
| 485 | EFI_PCI_CAPABILITY_HDR Hdr;\r |
| 486 | UINT16 MsgCtrlReg;\r |
| 487 | UINT32 MsgAddrReg;\r |
| 488 | UINT16 MsgDataReg;\r |
| 489 | } EFI_PCI_CAPABILITY_MSI32;\r |
| 490 | \r |
| 491 | typedef struct {\r |
| 492 | EFI_PCI_CAPABILITY_HDR Hdr;\r |
| 493 | UINT16 MsgCtrlReg;\r |
| 494 | UINT32 MsgAddrRegLsdw;\r |
| 495 | UINT32 MsgAddrRegMsdw;\r |
| 496 | UINT16 MsgDataReg;\r |
| 497 | } EFI_PCI_CAPABILITY_MSI64;\r |
| 498 | \r |
| 1bc5d021 |
499 | ///\r |
| bc14bdb3 |
500 | /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, defined in CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r |
| 1bc5d021 |
501 | ///\r |
| a7ed1e2e |
502 | typedef struct {\r |
| 503 | EFI_PCI_CAPABILITY_HDR Hdr;\r |
| 1bc5d021 |
504 | ///\r |
| 505 | /// not finished - fields need to go here\r |
| 506 | ///\r |
| a7ed1e2e |
507 | } EFI_PCI_CAPABILITY_HOTPLUG;\r |
| 508 | \r |
| a7ed1e2e |
509 | #define DEVICE_ID_NOCARE 0xFFFF\r |
| 510 | \r |
| 511 | #define PCI_ACPI_UNUSED 0\r |
| 512 | #define PCI_BAR_NOCHANGE 0\r |
| 513 | #define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL\r |
| 514 | #define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL\r |
| 515 | #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r |
| 516 | #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r |
| 517 | \r |
| 518 | #define PCI_BAR_IDX0 0x00\r |
| 519 | #define PCI_BAR_IDX1 0x01\r |
| 520 | #define PCI_BAR_IDX2 0x02\r |
| 521 | #define PCI_BAR_IDX3 0x03\r |
| 522 | #define PCI_BAR_IDX4 0x04\r |
| 523 | #define PCI_BAR_IDX5 0x05\r |
| 524 | #define PCI_BAR_ALL 0xFF\r |
| 525 | \r |
| bc14bdb3 |
526 | ///\r |
| 527 | /// EFI PCI Option ROM definitions\r |
| 528 | /// \r |
| 529 | #define EFI_ROOT_BRIDGE_LIST 'eprb' \r |
| 530 | #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r |
| afcf4907 |
531 | \r |
| 532 | typedef struct {\r |
| 533 | UINT8 Register;\r |
| 534 | UINT8 Function;\r |
| 535 | UINT8 Device;\r |
| 536 | UINT8 Bus;\r |
| 537 | UINT8 Reserved[4];\r |
| 538 | } DEFIO_PCI_ADDR;\r |
| 539 | \r |
| bc14bdb3 |
540 | #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r |
| 13c31065 |
541 | #define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r |
| bc14bdb3 |
542 | #define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r |
| 543 | #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///<defined in UEFI spec.\r |
| 544 | \r |
| 545 | typedef struct {\r |
| 546 | UINT16 Signature; ///< 0xaa55\r |
| 547 | UINT8 Reserved[0x16];\r |
| 548 | UINT16 PcirOffset;\r |
| 549 | } PCI_EXPANSION_ROM_HEADER;\r |
| 550 | \r |
| 551 | typedef struct {\r |
| 552 | UINT16 Signature; ///< 0xaa55\r |
| 553 | UINT8 Size512;\r |
| 554 | UINT8 InitEntryPoint[3];\r |
| 555 | UINT8 Reserved[0x12];\r |
| 556 | UINT16 PcirOffset;\r |
| 557 | } EFI_LEGACY_EXPANSION_ROM_HEADER;\r |
| 558 | \r |
| 559 | typedef struct {\r |
| 560 | UINT32 Signature; ///< "PCIR"\r |
| 561 | UINT16 VendorId;\r |
| 562 | UINT16 DeviceId;\r |
| 563 | UINT16 Reserved0;\r |
| 564 | UINT16 Length;\r |
| 565 | UINT8 Revision;\r |
| 566 | UINT8 ClassCode[3];\r |
| 567 | UINT16 ImageLength;\r |
| 568 | UINT16 CodeRevision;\r |
| 569 | UINT8 CodeType;\r |
| 570 | UINT8 Indicator;\r |
| 571 | UINT16 Reserved1;\r |
| 572 | } PCI_DATA_STRUCTURE;\r |
| 573 | \r |
| 574 | ///\r |
| 575 | /// defined in EFI/UEFI Spec\r |
| 576 | ///\r |
| afcf4907 |
577 | typedef struct {\r |
| bc14bdb3 |
578 | UINT16 Signature; ///< 0xaa55\r |
| afcf4907 |
579 | UINT16 InitializationSize;\r |
| bc14bdb3 |
580 | UINT32 EfiSignature; ///< 0x0EF1\r |
| afcf4907 |
581 | UINT16 EfiSubsystem;\r |
| 582 | UINT16 EfiMachineType;\r |
| 583 | UINT16 CompressionType;\r |
| 584 | UINT8 Reserved[8];\r |
| 585 | UINT16 EfiImageHeaderOffset;\r |
| 586 | UINT16 PcirOffset;\r |
| 587 | } EFI_PCI_EXPANSION_ROM_HEADER;\r |
| 588 | \r |
| 589 | typedef union {\r |
| 590 | UINT8 *Raw;\r |
| 591 | PCI_EXPANSION_ROM_HEADER *Generic;\r |
| 592 | EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r |
| 593 | EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r |
| 594 | } EFI_PCI_ROM_HEADER;\r |
| 595 | \r |
| a7ed1e2e |
596 | #endif\r |
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