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a7ed1e2e | 1 | /** @file\r |
2 | Support for PCI 2.2 standard.\r | |
3 | \r | |
bc14bdb3 | 4 | This file includes the definitions in the following specifications,\r |
5 | PCI Local Bus Specification, 2.0\r | |
6 | PCI-to-PCI Bridge Architecture Specification,\r | |
7 | PC Card Standard, 8.0\r | |
8 | \r | |
9 | Copyright (c) 2006 - 2008, Intel Corporation \r | |
a7ed1e2e | 10 | All rights reserved. This program and the accompanying materials \r |
11 | are licensed and made available under the terms and conditions of the BSD License \r | |
12 | which accompanies this distribution. The full text of the license may be found at \r | |
13 | http://opensource.org/licenses/bsd-license.php \r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
17 | \r | |
a7ed1e2e | 18 | **/\r |
19 | \r | |
42eedea9 | 20 | #ifndef _PCI22_H_\r |
21 | #define _PCI22_H_\r | |
a7ed1e2e | 22 | \r |
23 | #define PCI_MAX_SEGMENT 0\r | |
a7ed1e2e | 24 | #define PCI_MAX_BUS 255\r |
a7ed1e2e | 25 | #define PCI_MAX_DEVICE 31\r |
26 | #define PCI_MAX_FUNC 7\r | |
27 | \r | |
a7ed1e2e | 28 | \r |
373b5cf9 | 29 | #pragma pack(1)\r |
a7ed1e2e | 30 | typedef struct {\r |
31 | UINT16 VendorId;\r | |
32 | UINT16 DeviceId;\r | |
33 | UINT16 Command;\r | |
34 | UINT16 Status;\r | |
35 | UINT8 RevisionID;\r | |
36 | UINT8 ClassCode[3];\r | |
37 | UINT8 CacheLineSize;\r | |
38 | UINT8 LatencyTimer;\r | |
39 | UINT8 HeaderType;\r | |
40 | UINT8 BIST;\r | |
41 | } PCI_DEVICE_INDEPENDENT_REGION;\r | |
42 | \r | |
43 | typedef struct {\r | |
44 | UINT32 Bar[6];\r | |
45 | UINT32 CISPtr;\r | |
46 | UINT16 SubsystemVendorID;\r | |
47 | UINT16 SubsystemID;\r | |
48 | UINT32 ExpansionRomBar;\r | |
49 | UINT8 CapabilityPtr;\r | |
50 | UINT8 Reserved1[3];\r | |
51 | UINT32 Reserved2;\r | |
52 | UINT8 InterruptLine;\r | |
53 | UINT8 InterruptPin;\r | |
54 | UINT8 MinGnt;\r | |
55 | UINT8 MaxLat;\r | |
56 | } PCI_DEVICE_HEADER_TYPE_REGION;\r | |
57 | \r | |
58 | typedef struct {\r | |
59 | PCI_DEVICE_INDEPENDENT_REGION Hdr;\r | |
60 | PCI_DEVICE_HEADER_TYPE_REGION Device;\r | |
61 | } PCI_TYPE00;\r | |
62 | \r | |
bc14bdb3 | 63 | ///\r |
64 | /// defined in PCI-to-PCI Bridge Architecture Specification\r | |
65 | ///\r | |
a7ed1e2e | 66 | typedef struct {\r |
67 | UINT32 Bar[2];\r | |
68 | UINT8 PrimaryBus;\r | |
69 | UINT8 SecondaryBus;\r | |
70 | UINT8 SubordinateBus;\r | |
71 | UINT8 SecondaryLatencyTimer;\r | |
72 | UINT8 IoBase;\r | |
73 | UINT8 IoLimit;\r | |
74 | UINT16 SecondaryStatus;\r | |
75 | UINT16 MemoryBase;\r | |
76 | UINT16 MemoryLimit;\r | |
77 | UINT16 PrefetchableMemoryBase;\r | |
78 | UINT16 PrefetchableMemoryLimit;\r | |
79 | UINT32 PrefetchableBaseUpper32;\r | |
80 | UINT32 PrefetchableLimitUpper32;\r | |
81 | UINT16 IoBaseUpper16;\r | |
82 | UINT16 IoLimitUpper16;\r | |
83 | UINT8 CapabilityPtr;\r | |
84 | UINT8 Reserved[3];\r | |
85 | UINT32 ExpansionRomBAR;\r | |
86 | UINT8 InterruptLine;\r | |
87 | UINT8 InterruptPin;\r | |
88 | UINT16 BridgeControl;\r | |
89 | } PCI_BRIDGE_CONTROL_REGISTER;\r | |
90 | \r | |
91 | typedef struct {\r | |
92 | PCI_DEVICE_INDEPENDENT_REGION Hdr;\r | |
93 | PCI_BRIDGE_CONTROL_REGISTER Bridge;\r | |
94 | } PCI_TYPE01;\r | |
95 | \r | |
96 | typedef union {\r | |
97 | PCI_TYPE00 Device;\r | |
98 | PCI_TYPE01 Bridge;\r | |
99 | } PCI_TYPE_GENERIC;\r | |
100 | \r | |
bc14bdb3 | 101 | /// \r |
102 | /// CardBus Conroller Configuration Space, defined in PC Card Standard. 8.0\r | |
103 | ///\r | |
a7ed1e2e | 104 | typedef struct {\r |
bc14bdb3 | 105 | UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base\r |
106 | UINT8 Cap_Ptr;\r | |
107 | UINT8 Reserved;\r | |
108 | UINT16 SecondaryStatus; ///< Secondary Status\r | |
109 | UINT8 PciBusNumber; ///< PCI Bus Number\r | |
110 | UINT8 CardBusBusNumber; ///< CardBus Bus Number\r | |
111 | UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r | |
112 | UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r | |
113 | UINT32 MemoryBase0; ///< Memory Base Register 0\r | |
114 | UINT32 MemoryLimit0; ///< Memory Limit Register 0\r | |
a7ed1e2e | 115 | UINT32 MemoryBase1;\r |
116 | UINT32 MemoryLimit1;\r | |
117 | UINT32 IoBase0;\r | |
bc14bdb3 | 118 | UINT32 IoLimit0; ///< I/O Base Register 0\r |
119 | UINT32 IoBase1; ///< I/O Limit Register 0\r | |
a7ed1e2e | 120 | UINT32 IoLimit1;\r |
bc14bdb3 | 121 | UINT8 InterruptLine; ///< Interrupt Line\r |
122 | UINT8 InterruptPin; ///< Interrupt Pin\r | |
123 | UINT16 BridgeControl; ///< Bridge Control\r | |
a7ed1e2e | 124 | } PCI_CARDBUS_CONTROL_REGISTER;\r |
125 | \r | |
bc14bdb3 | 126 | ///\r |
127 | /// Definitions of PCI class bytes and manipulation macros.\r | |
128 | ///\r | |
a7ed1e2e | 129 | #define PCI_CLASS_OLD 0x00\r |
bc14bdb3 | 130 | #define PCI_CLASS_OLD_OTHER 0x00\r |
131 | #define PCI_CLASS_OLD_VGA 0x01\r | |
a7ed1e2e | 132 | \r |
133 | #define PCI_CLASS_MASS_STORAGE 0x01\r | |
bc14bdb3 | 134 | #define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r |
135 | #define PCI_CLASS_MASS_STORAGE_IDE 0x01\r | |
136 | #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r | |
137 | #define PCI_CLASS_MASS_STORAGE_IPI 0x03\r | |
138 | #define PCI_CLASS_MASS_STORAGE_RAID 0x04\r | |
139 | #define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r | |
a7ed1e2e | 140 | \r |
141 | #define PCI_CLASS_NETWORK 0x02\r | |
bc14bdb3 | 142 | #define PCI_CLASS_NETWORK_ETHERNET 0x00 \r |
143 | #define PCI_CLASS_NETWORK_TOKENRING 0x01\r | |
144 | #define PCI_CLASS_NETWORK_FDDI 0x02\r | |
145 | #define PCI_CLASS_NETWORK_ATM 0x03\r | |
146 | #define PCI_CLASS_NETWORK_ISDN 0x04\r | |
147 | #define PCI_CLASS_NETWORK_OTHER 0x80\r | |
a7ed1e2e | 148 | \r |
149 | #define PCI_CLASS_DISPLAY 0x03\r | |
bc14bdb3 | 150 | #define PCI_CLASS_DISPLAY_VGA 0x00\r |
151 | #define PCI_IF_VGA_VGA 0x00\r | |
152 | #define PCI_IF_VGA_8514 0x01\r | |
153 | #define PCI_CLASS_DISPLAY_XGA 0x01\r | |
154 | #define PCI_CLASS_DISPLAY_3D 0x02\r | |
155 | #define PCI_CLASS_DISPLAY_OTHER 0x80 \r | |
156 | #define PCI_CLASS_DISPLAY_GFX 0x80\r | |
157 | \r | |
158 | #define PCI_CLASS_MEDIA 0x04\r | |
159 | #define PCI_CLASS_MEDIA_VIDEO 0x00\r | |
160 | #define PCI_CLASS_MEDIA_AUDIO 0x01\r | |
161 | #define PCI_CLASS_MEDIA_TELEPHONE 0x02\r | |
162 | #define PCI_CLASS_MEDIA_OTHER 0x80\r | |
163 | \r | |
164 | #define PCI_CLASS_MEMORY_CONTROLLER 0x05\r | |
165 | #define PCI_CLASS_MEMORY_RAM 0x00\r | |
166 | #define PCI_CLASS_MEMORY_FLASH 0x01\r | |
167 | #define PCI_CLASS_MEMORY_OTHER 0x80\r | |
168 | \r | |
a7ed1e2e | 169 | #define PCI_CLASS_BRIDGE 0x06\r |
bc14bdb3 | 170 | #define PCI_CLASS_BRIDGE_HOST 0x00\r |
171 | #define PCI_CLASS_BRIDGE_ISA 0x01\r | |
172 | #define PCI_CLASS_BRIDGE_EISA 0x02\r | |
173 | #define PCI_CLASS_BRIDGE_MCA 0x03\r | |
174 | #define PCI_CLASS_BRIDGE_P2P 0x04\r | |
175 | #define PCI_IF_BRIDGE_P2P 0x00\r | |
176 | #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r | |
177 | #define PCI_CLASS_BRIDGE_PCMCIA 0x05\r | |
178 | #define PCI_CLASS_BRIDGE_NUBUS 0x06\r | |
179 | #define PCI_CLASS_BRIDGE_CARDBUS 0x07\r | |
180 | #define PCI_CLASS_BRIDGE_RACEWAY 0x08\r | |
181 | #define PCI_CLASS_BRIDGE_OTHER 0x80\r | |
182 | #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r | |
183 | \r | |
184 | #define PCI_CLASS_SCC 0x07 ///< Simple communications controllers \r | |
185 | #define PCI_SUBCLASS_SERIAL 0x00\r | |
186 | #define PCI_IF_GENERIC_XT 0x00\r | |
187 | #define PCI_IF_16450 0x01\r | |
188 | #define PCI_IF_16550 0x02\r | |
189 | #define PCI_IF_16650 0x03\r | |
190 | #define PCI_IF_16750 0x04\r | |
191 | #define PCI_IF_16850 0x05\r | |
192 | #define PCI_IF_16950 0x06\r | |
193 | #define PCI_SUBCLASS_PARALLEL 0x01\r | |
194 | #define PCI_IF_PARALLEL_PORT 0x00\r | |
195 | #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r | |
196 | #define PCI_IF_ECP_PARALLEL_PORT 0x02\r | |
197 | #define PCI_IF_1284_CONTROLLER 0x03\r | |
198 | #define PCI_IF_1284_DEVICE 0xFE\r | |
199 | #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r | |
200 | #define PCI_SUBCLASS_MODEM 0x03\r | |
201 | #define PCI_IF_GENERIC_MODEM 0x00\r | |
202 | #define PCI_IF_16450_MODEM 0x01\r | |
203 | #define PCI_IF_16550_MODEM 0x02\r | |
204 | #define PCI_IF_16650_MODEM 0x03\r | |
205 | #define PCI_IF_16750_MODEM 0x04\r | |
206 | #define PCI_SUBCLASS_SCC_OTHER 0x80\r | |
a7ed1e2e | 207 | \r |
208 | #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r | |
bc14bdb3 | 209 | #define PCI_SUBCLASS_PIC 0x00\r |
210 | #define PCI_IF_8259_PIC 0x00\r | |
211 | #define PCI_IF_ISA_PIC 0x01\r | |
212 | #define PCI_IF_EISA_PIC 0x02\r | |
213 | #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory. \r | |
214 | #define PCI_IF_APIC_CONTROLLER2 0x20 \r | |
215 | #define PCI_SUBCLASS_DMA 0x01\r | |
216 | #define PCI_IF_8237_DMA 0x00\r | |
217 | #define PCI_IF_ISA_DMA 0x01\r | |
218 | #define PCI_IF_EISA_DMA 0x02\r | |
219 | #define PCI_SUBCLASS_TIMER 0x02\r | |
220 | #define PCI_IF_8254_TIMER 0x00\r | |
221 | #define PCI_IF_ISA_TIMER 0x01\r | |
222 | #define PCI_IF_EISA_TIMER 0x02\r | |
223 | #define PCI_SUBCLASS_RTC 0x03\r | |
224 | #define PCI_IF_GENERIC_RTC 0x00\r | |
225 | #define PCI_IF_ISA_RTC 0x00\r | |
226 | #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r | |
227 | #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r | |
a7ed1e2e | 228 | \r |
229 | #define PCI_CLASS_INPUT_DEVICE 0x09\r | |
bc14bdb3 | 230 | #define PCI_SUBCLASS_KEYBOARD 0x00\r |
231 | #define PCI_SUBCLASS_PEN 0x01\r | |
232 | #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r | |
233 | #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r | |
234 | #define PCI_SUBCLASS_GAMEPORT 0x04\r | |
235 | #define PCI_IF_GAMEPORT 0x00\r | |
236 | #define PCI_IF_GAMEPORT1 0x01\r | |
237 | #define PCI_SUBCLASS_INPUT_OTHER 0x80\r | |
a7ed1e2e | 238 | \r |
239 | #define PCI_CLASS_DOCKING_STATION 0x0A\r | |
240 | \r | |
241 | #define PCI_CLASS_PROCESSOR 0x0B\r | |
bc14bdb3 | 242 | #define PCI_SUBCLASS_PROC_386 0x00\r |
243 | #define PCI_SUBCLASS_PROC_486 0x01\r | |
244 | #define PCI_SUBCLASS_PROC_PENTIUM 0x02\r | |
245 | #define PCI_SUBCLASS_PROC_ALPHA 0x10\r | |
246 | #define PCI_SUBCLASS_PROC_POWERPC 0x20\r | |
247 | #define PCI_SUBCLASS_PROC_MIPS 0x30\r | |
248 | #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r | |
a7ed1e2e | 249 | \r |
250 | #define PCI_CLASS_SERIAL 0x0C\r | |
bc14bdb3 | 251 | #define PCI_CLASS_SERIAL_FIREWIRE 0x00\r |
252 | #define PCI_IF_1394 0x00\r | |
253 | #define PCI_IF_1394_OPEN_HCI 0x10\r | |
254 | #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r | |
255 | #define PCI_CLASS_SERIAL_SSA 0x02\r | |
256 | #define PCI_CLASS_SERIAL_USB 0x03\r | |
257 | #define PCI_IF_UHCI 0x00\r | |
258 | #define PCI_IF_OHCI 0x10\r | |
259 | #define PCI_IF_USB_OTHER 0x80\r | |
260 | #define PCI_IF_USB_DEVICE 0xFE\r | |
261 | #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r | |
262 | #define PCI_CLASS_SERIAL_SMB 0x05\r | |
a7ed1e2e | 263 | \r |
264 | #define PCI_CLASS_WIRELESS 0x0D\r | |
bc14bdb3 | 265 | #define PCI_SUBCLASS_IRDA 0x00\r |
266 | #define PCI_SUBCLASS_IR 0x01\r | |
267 | #define PCI_SUBCLASS_RF 0x02\r | |
268 | #define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r | |
a7ed1e2e | 269 | \r |
270 | #define PCI_CLASS_INTELLIGENT_IO 0x0E\r | |
271 | \r | |
272 | #define PCI_CLASS_SATELLITE 0x0F\r | |
bc14bdb3 | 273 | #define PCI_SUBCLASS_TV 0x01\r |
274 | #define PCI_SUBCLASS_AUDIO 0x02\r | |
275 | #define PCI_SUBCLASS_VOICE 0x03\r | |
276 | #define PCI_SUBCLASS_DATA 0x04\r | |
a7ed1e2e | 277 | \r |
bc14bdb3 | 278 | #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r |
279 | #define PCI_SUBCLASS_NET_COMPUT 0x00\r | |
280 | #define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r | |
281 | #define PCI_SUBCLASS_SECURITY_OTHER 0x80\r | |
a7ed1e2e | 282 | \r |
283 | #define PCI_CLASS_DPIO 0x11\r | |
bc14bdb3 | 284 | #define PCI_SUBCLASS_DPIO 0x00\r |
285 | #define PCI_SUBCLASS_DPIO_OTHER 0x80\r | |
a7ed1e2e | 286 | \r |
287 | #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r | |
288 | #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r | |
289 | #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r | |
290 | \r | |
291 | #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r | |
292 | #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)\r | |
293 | #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)\r | |
294 | #define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)\r | |
295 | #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r | |
296 | #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r | |
297 | #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r | |
298 | #define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)\r | |
299 | #define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)\r | |
300 | #define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)\r | |
301 | #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)\r | |
302 | #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)\r | |
303 | #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r | |
304 | #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r | |
305 | \r | |
bc14bdb3 | 306 | //\r |
307 | // the definition of Header Type \r | |
308 | //\r | |
a7ed1e2e | 309 | #define HEADER_TYPE_DEVICE 0x00\r |
310 | #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r | |
311 | #define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r | |
a7ed1e2e | 312 | #define HEADER_TYPE_MULTI_FUNCTION 0x80\r |
bc14bdb3 | 313 | //\r |
314 | // Mask of Header type\r | |
315 | //\r | |
a7ed1e2e | 316 | #define HEADER_LAYOUT_CODE 0x7f\r |
317 | \r | |
318 | #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r | |
319 | #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r | |
320 | #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r | |
321 | \r | |
bc14bdb3 | 322 | ///\r |
323 | /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,\r | |
324 | ///\r | |
a7ed1e2e | 325 | #define PCI_BRIDGE_ROMBAR 0x38\r |
326 | \r | |
327 | #define PCI_MAX_BAR 0x0006\r | |
328 | #define PCI_MAX_CONFIG_OFFSET 0x0100\r | |
329 | \r | |
330 | #define PCI_VENDOR_ID_OFFSET 0x00\r | |
331 | #define PCI_DEVICE_ID_OFFSET 0x02\r | |
332 | #define PCI_COMMAND_OFFSET 0x04\r | |
333 | #define PCI_PRIMARY_STATUS_OFFSET 0x06\r | |
334 | #define PCI_REVISION_ID_OFFSET 0x08\r | |
335 | #define PCI_CLASSCODE_OFFSET 0x09\r | |
336 | #define PCI_CACHELINE_SIZE_OFFSET 0x0C\r | |
337 | #define PCI_LATENCY_TIMER_OFFSET 0x0D\r | |
338 | #define PCI_HEADER_TYPE_OFFSET 0x0E\r | |
339 | #define PCI_BIST_OFFSET 0x0F\r | |
340 | #define PCI_BASE_ADDRESSREG_OFFSET 0x10\r | |
341 | #define PCI_CARDBUS_CIS_OFFSET 0x28\r | |
bc14bdb3 | 342 | #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r |
a7ed1e2e | 343 | #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r |
bc14bdb3 | 344 | #define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r |
a7ed1e2e | 345 | #define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r |
346 | #define PCI_EXPANSION_ROM_BASE 0x30\r | |
347 | #define PCI_CAPBILITY_POINTER_OFFSET 0x34\r | |
bc14bdb3 | 348 | #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r |
349 | #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r | |
350 | #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r | |
351 | #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r | |
a7ed1e2e | 352 | \r |
bc14bdb3 | 353 | ///\r |
354 | /// defined in PCI-to-PCI Bridge Architecture Specification\r | |
355 | ///\r | |
356 | #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r | |
357 | #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r | |
358 | #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r | |
359 | #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E \r | |
360 | #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E \r | |
a7ed1e2e | 361 | \r |
bc14bdb3 | 362 | ///\r |
363 | /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r | |
364 | ///\r | |
a7ed1e2e | 365 | #define PCI_INT_LINE_UNKNOWN 0xFF \r |
366 | \r | |
367 | typedef union {\r | |
368 | struct {\r | |
369 | UINT32 Reg : 8;\r | |
370 | UINT32 Func : 3;\r | |
371 | UINT32 Dev : 5;\r | |
372 | UINT32 Bus : 8;\r | |
373 | UINT32 Reserved : 7;\r | |
374 | UINT32 Enable : 1;\r | |
375 | } Bits;\r | |
376 | UINT32 Uint32;\r | |
377 | } PCI_CONFIG_ACCESS_CF8;\r | |
378 | \r | |
379 | #pragma pack()\r | |
380 | \r | |
bc14bdb3 | 381 | #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r |
382 | #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r | |
383 | #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r | |
384 | #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r | |
385 | #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r | |
386 | #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r | |
387 | #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r | |
388 | #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r | |
389 | #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r | |
390 | #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r | |
a7ed1e2e | 391 | \r |
bc14bdb3 | 392 | ///\r |
393 | /// defined in PCI-to-PCI Bridge Architecture Specification\r | |
394 | ///\r | |
395 | #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\r | |
396 | #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\r | |
397 | #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\r | |
398 | #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008\r | |
399 | #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010\r | |
400 | #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020\r | |
401 | #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040\r | |
402 | #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080\r | |
403 | #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100\r | |
404 | #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200\r | |
405 | #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\r | |
406 | #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\r | |
407 | \r | |
408 | ///\r | |
409 | /// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r | |
410 | ///\r | |
411 | #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r | |
412 | #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r | |
413 | #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r | |
414 | #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r | |
a7ed1e2e | 415 | \r |
416 | //\r | |
417 | // Following are the PCI status control bit\r | |
418 | //\r | |
bc14bdb3 | 419 | #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r |
420 | #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r | |
421 | #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r | |
422 | #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r | |
a7ed1e2e | 423 | \r |
bc14bdb3 | 424 | ///\r |
425 | /// defined in PC Card Standard\r | |
426 | ///\r | |
a7ed1e2e | 427 | #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r |
428 | \r | |
429 | #pragma pack(1)\r | |
a7ed1e2e | 430 | //\r |
431 | // PCI Capability List IDs and records\r | |
432 | //\r | |
433 | #define EFI_PCI_CAPABILITY_ID_PMI 0x01\r | |
434 | #define EFI_PCI_CAPABILITY_ID_AGP 0x02\r | |
435 | #define EFI_PCI_CAPABILITY_ID_VPD 0x03\r | |
436 | #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r | |
437 | #define EFI_PCI_CAPABILITY_ID_MSI 0x05\r | |
438 | #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r | |
a7ed1e2e | 439 | typedef struct {\r |
440 | UINT8 CapabilityID;\r | |
441 | UINT8 NextItemPtr;\r | |
442 | } EFI_PCI_CAPABILITY_HDR;\r | |
443 | \r | |
1bc5d021 | 444 | ///\r |
bc14bdb3 | 445 | /// Capability EFI_PCI_CAPABILITY_ID_PMI, defined in PCI Power Management Interface Specifiction\r |
1bc5d021 | 446 | ///\r |
a7ed1e2e | 447 | typedef struct {\r |
448 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
449 | UINT16 PMC;\r | |
450 | UINT16 PMCSR;\r | |
451 | UINT8 BridgeExtention;\r | |
452 | UINT8 Data;\r | |
453 | } EFI_PCI_CAPABILITY_PMI;\r | |
454 | \r | |
1bc5d021 | 455 | ///\r |
bc14bdb3 | 456 | /// Capability EFI_PCI_CAPABILITY_ID_AGP, defined in Accelerated Graphics Port Interface Specification\r |
1bc5d021 | 457 | ///\r |
a7ed1e2e | 458 | typedef struct {\r |
459 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
460 | UINT8 Rev;\r | |
461 | UINT8 Reserved;\r | |
462 | UINT32 Status;\r | |
463 | UINT32 Command;\r | |
464 | } EFI_PCI_CAPABILITY_AGP;\r | |
465 | \r | |
1bc5d021 | 466 | ///\r |
bc14bdb3 | 467 | /// Capability EFI_PCI_CAPABILITY_ID_VPD, in PCI2.2 Spec.\r |
1bc5d021 | 468 | ///\r |
a7ed1e2e | 469 | typedef struct {\r |
470 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
471 | UINT16 AddrReg;\r | |
472 | UINT32 DataReg;\r | |
473 | } EFI_PCI_CAPABILITY_VPD;\r | |
474 | \r | |
1bc5d021 | 475 | ///\r |
bc14bdb3 | 476 | /// Capability EFI_PCI_CAPABILITY_ID_SLOTID, defined in PCI-to-PCI Bridge Architeture Specification\r |
1bc5d021 | 477 | ///\r |
a7ed1e2e | 478 | typedef struct {\r |
479 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
480 | UINT8 ExpnsSlotReg;\r | |
481 | UINT8 ChassisNo;\r | |
482 | } EFI_PCI_CAPABILITY_SLOTID;\r | |
483 | \r | |
1bc5d021 | 484 | ///\r |
bc14bdb3 | 485 | /// Capability EFI_PCI_CAPABILITY_ID_MSI, defined in PCI2.2\r |
1bc5d021 | 486 | ///\r |
a7ed1e2e | 487 | typedef struct {\r |
488 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
489 | UINT16 MsgCtrlReg;\r | |
490 | UINT32 MsgAddrReg;\r | |
491 | UINT16 MsgDataReg;\r | |
492 | } EFI_PCI_CAPABILITY_MSI32;\r | |
493 | \r | |
494 | typedef struct {\r | |
495 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
496 | UINT16 MsgCtrlReg;\r | |
497 | UINT32 MsgAddrRegLsdw;\r | |
498 | UINT32 MsgAddrRegMsdw;\r | |
499 | UINT16 MsgDataReg;\r | |
500 | } EFI_PCI_CAPABILITY_MSI64;\r | |
501 | \r | |
1bc5d021 | 502 | ///\r |
bc14bdb3 | 503 | /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, defined in CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r |
1bc5d021 | 504 | ///\r |
a7ed1e2e | 505 | typedef struct {\r |
506 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
1bc5d021 | 507 | ///\r |
508 | /// not finished - fields need to go here\r | |
509 | ///\r | |
a7ed1e2e | 510 | } EFI_PCI_CAPABILITY_HOTPLUG;\r |
511 | \r | |
a7ed1e2e | 512 | #define DEVICE_ID_NOCARE 0xFFFF\r |
513 | \r | |
514 | #define PCI_ACPI_UNUSED 0\r | |
515 | #define PCI_BAR_NOCHANGE 0\r | |
516 | #define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL\r | |
517 | #define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL\r | |
518 | #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r | |
519 | #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r | |
520 | \r | |
521 | #define PCI_BAR_IDX0 0x00\r | |
522 | #define PCI_BAR_IDX1 0x01\r | |
523 | #define PCI_BAR_IDX2 0x02\r | |
524 | #define PCI_BAR_IDX3 0x03\r | |
525 | #define PCI_BAR_IDX4 0x04\r | |
526 | #define PCI_BAR_IDX5 0x05\r | |
527 | #define PCI_BAR_ALL 0xFF\r | |
528 | \r | |
bc14bdb3 | 529 | ///\r |
530 | /// EFI PCI Option ROM definitions\r | |
531 | /// \r | |
532 | #define EFI_ROOT_BRIDGE_LIST 'eprb' \r | |
533 | #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r | |
afcf4907 | 534 | \r |
535 | typedef struct {\r | |
536 | UINT8 Register;\r | |
537 | UINT8 Function;\r | |
538 | UINT8 Device;\r | |
539 | UINT8 Bus;\r | |
540 | UINT8 Reserved[4];\r | |
541 | } DEFIO_PCI_ADDR;\r | |
542 | \r | |
bc14bdb3 | 543 | #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r |
544 | #define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')\r | |
545 | #define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r | |
546 | #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///<defined in UEFI spec.\r | |
547 | \r | |
548 | typedef struct {\r | |
549 | UINT16 Signature; ///< 0xaa55\r | |
550 | UINT8 Reserved[0x16];\r | |
551 | UINT16 PcirOffset;\r | |
552 | } PCI_EXPANSION_ROM_HEADER;\r | |
553 | \r | |
554 | typedef struct {\r | |
555 | UINT16 Signature; ///< 0xaa55\r | |
556 | UINT8 Size512;\r | |
557 | UINT8 InitEntryPoint[3];\r | |
558 | UINT8 Reserved[0x12];\r | |
559 | UINT16 PcirOffset;\r | |
560 | } EFI_LEGACY_EXPANSION_ROM_HEADER;\r | |
561 | \r | |
562 | typedef struct {\r | |
563 | UINT32 Signature; ///< "PCIR"\r | |
564 | UINT16 VendorId;\r | |
565 | UINT16 DeviceId;\r | |
566 | UINT16 Reserved0;\r | |
567 | UINT16 Length;\r | |
568 | UINT8 Revision;\r | |
569 | UINT8 ClassCode[3];\r | |
570 | UINT16 ImageLength;\r | |
571 | UINT16 CodeRevision;\r | |
572 | UINT8 CodeType;\r | |
573 | UINT8 Indicator;\r | |
574 | UINT16 Reserved1;\r | |
575 | } PCI_DATA_STRUCTURE;\r | |
576 | \r | |
577 | ///\r | |
578 | /// defined in EFI/UEFI Spec\r | |
579 | ///\r | |
afcf4907 | 580 | typedef struct {\r |
bc14bdb3 | 581 | UINT16 Signature; ///< 0xaa55\r |
afcf4907 | 582 | UINT16 InitializationSize;\r |
bc14bdb3 | 583 | UINT32 EfiSignature; ///< 0x0EF1\r |
afcf4907 | 584 | UINT16 EfiSubsystem;\r |
585 | UINT16 EfiMachineType;\r | |
586 | UINT16 CompressionType;\r | |
587 | UINT8 Reserved[8];\r | |
588 | UINT16 EfiImageHeaderOffset;\r | |
589 | UINT16 PcirOffset;\r | |
590 | } EFI_PCI_EXPANSION_ROM_HEADER;\r | |
591 | \r | |
592 | typedef union {\r | |
593 | UINT8 *Raw;\r | |
594 | PCI_EXPANSION_ROM_HEADER *Generic;\r | |
595 | EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r | |
596 | EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r | |
597 | } EFI_PCI_ROM_HEADER;\r | |
598 | \r | |
373b5cf9 | 599 | #pragma pack()\r |
a7ed1e2e | 600 | \r |
601 | #endif\r |