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a7ed1e2e | 1 | /** @file\r |
2 | Support for PCI 2.3 standard.\r | |
3 | \r | |
9095d37b | 4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a7ed1e2e | 6 | \r |
a7ed1e2e | 7 | **/\r |
8 | \r | |
42eedea9 | 9 | #ifndef _PCI23_H_\r |
10 | #define _PCI23_H_\r | |
a7ed1e2e | 11 | \r |
bc14bdb3 | 12 | #include <IndustryStandard/Pci22.h>\r |
13 | \r | |
14 | ///\r | |
af2dc6a7 | 15 | /// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r |
bc14bdb3 | 16 | ///\r |
179d85c8 | 17 | ///@{\r |
2f88bd3a | 18 | #define PCI_CLASS_MASS_STORAGE_ATA 0x05\r |
179d85c8 | 19 | #define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20\r |
20 | #define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30\r | |
21 | ///@}\r | |
22 | \r | |
826a66d4 RN |
23 | ///\r |
24 | /// PCI_CLASS_NETWORK, Base Class 02h.\r | |
25 | ///\r | |
26 | ///@{\r | |
2f88bd3a MK |
27 | #define PCI_CLASS_NETWORK_WORLDFIP 0x05\r |
28 | #define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06\r | |
826a66d4 RN |
29 | ///@}\r |
30 | \r | |
31 | ///\r | |
32 | /// PCI_CLASS_BRIDGE, Base Class 06h.\r | |
33 | ///\r | |
34 | ///@{\r | |
2f88bd3a MK |
35 | #define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09\r |
36 | #define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40\r | |
37 | #define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80\r | |
38 | #define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A\r | |
826a66d4 RN |
39 | ///@}\r |
40 | \r | |
41 | ///\r | |
42 | /// PCI_CLASS_SCC, Base Class 07h.\r | |
43 | ///\r | |
44 | ///@{\r | |
2f88bd3a MK |
45 | #define PCI_SUBCLASS_GPIB 0x04\r |
46 | #define PCI_SUBCLASS_SMART_CARD 0x05\r | |
826a66d4 RN |
47 | ///@}\r |
48 | \r | |
179d85c8 | 49 | ///\r |
af2dc6a7 | 50 | /// PCI_CLASS_SERIAL, Base Class 0Ch.\r |
179d85c8 | 51 | ///\r |
52 | ///@{\r | |
2f88bd3a MK |
53 | #define PCI_IF_EHCI 0x20\r |
54 | #define PCI_CLASS_SERIAL_IB 0x06\r | |
55 | #define PCI_CLASS_SERIAL_IPMI 0x07\r | |
56 | #define PCI_IF_IPMI_SMIC 0x00\r | |
57 | #define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style\r | |
58 | #define PCI_IF_IPMI_BT 0x02 ///< Block Transfer\r | |
59 | #define PCI_CLASS_SERIAL_SERCOS 0x08\r | |
60 | #define PCI_CLASS_SERIAL_CANBUS 0x09\r | |
826a66d4 RN |
61 | ///@}\r |
62 | \r | |
63 | ///\r | |
64 | /// PCI_CLASS_WIRELESS, Base Class 0Dh.\r | |
65 | ///\r | |
66 | ///@{\r | |
2f88bd3a MK |
67 | #define PCI_SUBCLASS_BLUETOOTH 0x11\r |
68 | #define PCI_SUBCLASS_BROADBAND 0x12\r | |
826a66d4 RN |
69 | ///@}\r |
70 | \r | |
71 | ///\r | |
72 | /// PCI_CLASS_DPIO, Base Class 11h.\r | |
73 | ///\r | |
74 | ///@{\r | |
2f88bd3a MK |
75 | #define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01\r |
76 | #define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10\r | |
77 | #define PCI_SUBCLASS_MANAGEMENT_CARD 0x20\r | |
179d85c8 | 78 | ///@}\r |
a7ed1e2e | 79 | \r |
bc14bdb3 | 80 | ///\r |
81 | /// defined in PCI Express Spec.\r | |
82 | ///\r | |
2f88bd3a | 83 | #define PCI_EXP_MAX_CONFIG_OFFSET 0x1000\r |
a7ed1e2e | 84 | \r |
a2461f6b | 85 | ///\r |
af2dc6a7 | 86 | /// PCI Capability List IDs and records.\r |
a2461f6b | 87 | ///\r |
bc14bdb3 | 88 | #define EFI_PCI_CAPABILITY_ID_PCIX 0x07\r |
8844f15d | 89 | #define EFI_PCI_CAPABILITY_ID_VENDOR 0x09\r |
bc14bdb3 | 90 | \r |
766f4bc1 | 91 | #pragma pack(1)\r |
bc14bdb3 | 92 | ///\r |
9095d37b | 93 | /// PCI-X Capabilities List,\r |
af2dc6a7 | 94 | /// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r |
bc14bdb3 | 95 | ///\r |
96 | typedef struct {\r | |
2f88bd3a MK |
97 | EFI_PCI_CAPABILITY_HDR Hdr;\r |
98 | UINT16 CommandReg;\r | |
99 | UINT32 StatusReg;\r | |
bc14bdb3 | 100 | } EFI_PCI_CAPABILITY_PCIX;\r |
101 | \r | |
427987f5 | 102 | ///\r |
9095d37b | 103 | /// PCI-X Bridge Capabilities List,\r |
af2dc6a7 | 104 | /// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r |
bc14bdb3 | 105 | ///\r |
106 | typedef struct {\r | |
2f88bd3a MK |
107 | EFI_PCI_CAPABILITY_HDR Hdr;\r |
108 | UINT16 SecStatusReg;\r | |
109 | UINT32 StatusReg;\r | |
110 | UINT32 SplitTransCtrlRegUp;\r | |
111 | UINT32 SplitTransCtrlRegDn;\r | |
bc14bdb3 | 112 | } EFI_PCI_CAPABILITY_PCIX_BRDG;\r |
113 | \r | |
8844f15d LE |
114 | ///\r |
115 | /// Vendor Specific Capability Header\r | |
116 | /// Table H-1: Capability IDs, PCI Local Bus Specification, 2.3\r | |
117 | ///\r | |
118 | typedef struct {\r | |
2f88bd3a MK |
119 | EFI_PCI_CAPABILITY_HDR Hdr;\r |
120 | UINT8 Length;\r | |
8844f15d LE |
121 | } EFI_PCI_CAPABILITY_VENDOR_HDR;\r |
122 | \r | |
766f4bc1 | 123 | #pragma pack()\r |
124 | \r | |
2f88bd3a | 125 | #define PCI_CODE_TYPE_EFI_IMAGE 0x03\r |
a7ed1e2e | 126 | \r |
127 | #endif\r |