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a7ed1e2e | 1 | /** @file\r |
2 | Support for PCI 3.0 standard.\r | |
3 | \r | |
9095d37b | 4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a7ed1e2e | 6 | \r |
a7ed1e2e | 7 | **/\r |
8 | \r | |
842f5579 A |
9 | #ifndef __PCI30_H__\r |
10 | #define __PCI30_H__\r | |
a7ed1e2e | 11 | \r |
bc14bdb3 | 12 | #include <IndustryStandard/Pci23.h>\r |
13 | \r | |
14 | ///\r | |
826a66d4 | 15 | /// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r |
bc14bdb3 | 16 | ///\r |
826a66d4 | 17 | ///@{\r |
2f88bd3a MK |
18 | #define PCI_CLASS_MASS_STORAGE_SATADPA 0x06\r |
19 | #define PCI_IF_MASS_STORAGE_SATA 0x00\r | |
20 | #define PCI_IF_MASS_STORAGE_AHCI 0x01\r | |
826a66d4 | 21 | ///@}\r |
bc14bdb3 | 22 | \r |
826a66d4 RN |
23 | ///\r |
24 | /// PCI_CLASS_WIRELESS, Base Class 0Dh.\r | |
25 | ///\r | |
26 | ///@{\r | |
2f88bd3a MK |
27 | #define PCI_SUBCLASS_ETHERNET_80211A 0x20\r |
28 | #define PCI_SUBCLASS_ETHERNET_80211B 0x21\r | |
826a66d4 RN |
29 | ///@}\r |
30 | \r | |
31 | /**\r | |
98642032 | 32 | Macro that checks whether device is a SATA controller.\r |
33 | \r | |
34 | @param _p Specified device.\r | |
35 | \r | |
36 | @retval TRUE Device is a SATA controller.\r | |
37 | @retval FALSE Device is not a SATA controller.\r | |
38 | \r | |
39 | **/\r | |
2f88bd3a | 40 | #define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)\r |
98642032 | 41 | \r |
bc14bdb3 | 42 | ///\r |
43 | /// PCI Capability List IDs and records\r | |
44 | ///\r | |
45 | #define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10\r | |
a7ed1e2e | 46 | \r |
766f4bc1 | 47 | #pragma pack(1)\r |
48 | \r | |
bc14bdb3 | 49 | ///\r |
427987f5 | 50 | /// PCI Data Structure Format\r |
51 | /// Section 5.1.2, PCI Firmware Specification, Revision 3.0\r | |
bc14bdb3 | 52 | ///\r |
a7ed1e2e | 53 | typedef struct {\r |
2f88bd3a MK |
54 | UINT32 Signature; ///< "PCIR"\r |
55 | UINT16 VendorId;\r | |
56 | UINT16 DeviceId;\r | |
57 | UINT16 DeviceListOffset;\r | |
58 | UINT16 Length;\r | |
59 | UINT8 Revision;\r | |
60 | UINT8 ClassCode[3];\r | |
61 | UINT16 ImageLength;\r | |
62 | UINT16 CodeRevision;\r | |
63 | UINT8 CodeType;\r | |
64 | UINT8 Indicator;\r | |
65 | UINT16 MaxRuntimeImageLength;\r | |
66 | UINT16 ConfigUtilityCodeHeaderOffset;\r | |
67 | UINT16 DMTFCLPEntryPointOffset;\r | |
a7ed1e2e | 68 | } PCI_3_0_DATA_STRUCTURE;\r |
69 | \r | |
766f4bc1 | 70 | #pragma pack()\r |
71 | \r | |
a7ed1e2e | 72 | #endif\r |