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a7ed1e2e | 1 | /** @file\r |
2 | Support for PCI 3.0 standard.\r | |
3 | \r | |
9095d37b | 4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a7ed1e2e | 6 | \r |
a7ed1e2e | 7 | **/\r |
8 | \r | |
842f5579 A |
9 | #ifndef __PCI30_H__\r |
10 | #define __PCI30_H__\r | |
a7ed1e2e | 11 | \r |
bc14bdb3 | 12 | \r |
13 | #include <IndustryStandard/Pci23.h>\r | |
14 | \r | |
15 | ///\r | |
826a66d4 | 16 | /// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r |
bc14bdb3 | 17 | ///\r |
826a66d4 | 18 | ///@{\r |
a7ed1e2e | 19 | #define PCI_CLASS_MASS_STORAGE_SATADPA 0x06\r |
bc14bdb3 | 20 | #define PCI_IF_MASS_STORAGE_SATA 0x00\r |
21 | #define PCI_IF_MASS_STORAGE_AHCI 0x01\r | |
826a66d4 | 22 | ///@}\r |
bc14bdb3 | 23 | \r |
826a66d4 RN |
24 | ///\r |
25 | /// PCI_CLASS_WIRELESS, Base Class 0Dh.\r | |
26 | ///\r | |
27 | ///@{\r | |
28 | #define PCI_SUBCLASS_ETHERNET_80211A 0x20\r | |
29 | #define PCI_SUBCLASS_ETHERNET_80211B 0x21\r | |
30 | ///@}\r | |
31 | \r | |
32 | /**\r | |
98642032 | 33 | Macro that checks whether device is a SATA controller.\r |
34 | \r | |
35 | @param _p Specified device.\r | |
36 | \r | |
37 | @retval TRUE Device is a SATA controller.\r | |
38 | @retval FALSE Device is not a SATA controller.\r | |
39 | \r | |
40 | **/\r | |
41 | #define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)\r | |
42 | \r | |
bc14bdb3 | 43 | ///\r |
44 | /// PCI Capability List IDs and records\r | |
45 | ///\r | |
46 | #define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10\r | |
a7ed1e2e | 47 | \r |
766f4bc1 | 48 | #pragma pack(1)\r |
49 | \r | |
bc14bdb3 | 50 | ///\r |
427987f5 | 51 | /// PCI Data Structure Format\r |
52 | /// Section 5.1.2, PCI Firmware Specification, Revision 3.0\r | |
bc14bdb3 | 53 | ///\r |
a7ed1e2e | 54 | typedef struct {\r |
bc14bdb3 | 55 | UINT32 Signature; ///< "PCIR"\r |
a7ed1e2e | 56 | UINT16 VendorId;\r |
57 | UINT16 DeviceId;\r | |
58 | UINT16 DeviceListOffset;\r | |
59 | UINT16 Length;\r | |
60 | UINT8 Revision;\r | |
61 | UINT8 ClassCode[3];\r | |
62 | UINT16 ImageLength;\r | |
63 | UINT16 CodeRevision;\r | |
64 | UINT8 CodeType;\r | |
65 | UINT8 Indicator;\r | |
66 | UINT16 MaxRuntimeImageLength;\r | |
67 | UINT16 ConfigUtilityCodeHeaderOffset;\r | |
68 | UINT16 DMTFCLPEntryPointOffset;\r | |
69 | } PCI_3_0_DATA_STRUCTURE;\r | |
70 | \r | |
766f4bc1 | 71 | #pragma pack()\r |
72 | \r | |
a7ed1e2e | 73 | #endif\r |