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MdePkg/PCI: Add missing PCI/PCIE definitions
[mirror_edk2.git] / MdePkg / Include / IndustryStandard / PciExpress21.h
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533403e6 1/** @file\r
2 Support for the latest PCI standard.\r
3\r
cbedba86 4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
0a38a95a 5 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR> \r
9df063a0 6 This program and the accompanying materials \r
533403e6 7 are licensed and made available under the terms and conditions of the BSD License \r
8 which accompanies this distribution. The full text of the license may be found at \r
9 http://opensource.org/licenses/bsd-license.php \r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
13\r
14**/\r
15\r
16#ifndef _PCIEXPRESS21_H_\r
17#define _PCIEXPRESS21_H_\r
18\r
cbedba86
RN		 19#include <IndustryStandard/Pci30.h>\r
20\r
21#pragma pack(1)\r
22///\r
23/// PCI Express Capability Structure\r
24///\r
25typedef union {\r
26 struct {\r
27 UINT16 Version : 4;\r
28 UINT16 DevicePortType : 4;\r
29 UINT16 SlotImplemented : 1;\r
30 UINT16 InterruptMessageNumber : 5;\r
31 UINT16 Undefined : 1;\r
32 UINT16 Reserved : 1;\r
33 } Bits;\r
34 UINT16 Uint16;\r
35} PCI_REG_PCIE_CAPABILITY;\r
36\r
37#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0\r
38#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1\r
39#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4\r
40#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5\r
41#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6\r
42#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7\r
43#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8\r
44#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9\r
45#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10\r
46\r
47typedef union {\r
48 struct {\r
49 UINT32 MaxPayloadSize : 3;\r
50 UINT32 PhantomFunctions : 2;\r
51 UINT32 ExtendedTagField : 1;\r
52 UINT32 EndpointL0sAcceptableLatency : 3;\r
53 UINT32 EndpointL1AcceptableLatency : 3;\r
54 UINT32 Undefined : 3;\r
55 UINT32 RoleBasedErrorReporting : 1;\r
56 UINT32 Reserved : 2;\r
57 UINT32 CapturedSlotPowerLimitValue : 8;\r
58 UINT32 CapturedSlotPowerLimitScale : 2;\r
59 UINT32 FunctionLevelReset : 1;\r
60 UINT32 Reserved2 : 3;\r
61 } Bits;\r
62 UINT32 Uint32;\r
63} PCI_REG_PCIE_DEVICE_CAPABILITY;\r
64\r
65typedef union {\r
66 struct {\r
67 UINT16 CorrectableError : 1;\r
68 UINT16 NonFatalError : 1;\r
69 UINT16 FatalError : 1;\r
70 UINT16 UnsupportedRequest : 1;\r
71 UINT16 RelaxedOrdering : 1;\r
72 UINT16 MaxPayloadSize : 3;\r
73 UINT16 ExtendedTagField : 1;\r
74 UINT16 PhantomFunctions : 1;\r
75 UINT16 AuxPower : 1;\r
76 UINT16 NoSnoop : 1;\r
77 UINT16 MaxReadRequestSize : 3;\r
78 UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;\r
79 } Bits;\r
80 UINT16 Uint16;\r
81} PCI_REG_PCIE_DEVICE_CONTROL;\r
82\r
83typedef union {\r
84 struct {\r
85 UINT16 CorrectableError : 1;\r
86 UINT16 NonFatalError : 1;\r
87 UINT16 FatalError : 1;\r
88 UINT16 UnsupportedRequest : 1;\r
89 UINT16 AuxPower : 1;\r
90 UINT16 TransactionsPending : 1;\r
91 UINT16 Reserved : 10;\r
92 } Bits;\r
93 UINT16 Uint16;\r
94} PCI_REG_PCIE_DEVICE_STATUS;\r
95\r
96typedef union {\r
97 struct {\r
98 UINT32 MaxLinkSpeed : 4;\r
99 UINT32 MaxLinkWidth : 6;\r
100 UINT32 Aspm : 2;\r
101 UINT32 L0sExitLatency : 3;\r
102 UINT32 L1ExitLatency : 3;\r
103 UINT32 ClockPowerManagement : 1;\r
104 UINT32 SurpriseDownError : 1;\r
105 UINT32 DataLinkLayerLinkActive : 1;\r
106 UINT32 LinkBandwidthNotification : 1;\r
107 UINT32 AspmOptionalityCompliance : 1;\r
108 UINT32 Reserved : 1;\r
109 UINT32 PortNumber : 8;\r
110 } Bits;\r
111 UINT32 Uint32;\r
112} PCI_REG_PCIE_LINK_CAPABILITY;\r
113\r
114#define PCIE_LINK_ASPM_L0S BIT0\r
115#define PCIE_LINK_ASPM_L1 BIT1\r
116\r
117typedef union {\r
118 struct {\r
119 UINT16 AspmControl : 2;\r
120 UINT16 Reserved : 1;\r
121 UINT16 ReadCompletionBoundary : 1;\r
122 UINT16 LinkDisable : 1;\r
123 UINT16 RetrainLink : 1;\r
124 UINT16 CommonClockConfiguration : 1;\r
125 UINT16 ExtendedSynch : 1;\r
126 UINT16 ClockPowerManagement : 1;\r
127 UINT16 HardwareAutonomousWidthDisable : 1;\r
128 UINT16 LinkBandwidthManagementInterrupt : 1;\r
129 UINT16 LinkAutonomousBandwidthInterrupt : 1;\r
130 } Bits;\r
131 UINT16 Uint16;\r
132} PCI_REG_PCIE_LINK_CONTROL;\r
133\r
134typedef union {\r
135 struct {\r
136 UINT16 CurrentLinkSpeed : 4;\r
137 UINT16 NegotiatedLinkWidth : 6;\r
138 UINT16 Undefined : 1;\r
139 UINT16 LinkTraining : 1;\r
140 UINT16 SlotClockConfiguration : 1;\r
141 UINT16 DataLinkLayerLinkActive : 1;\r
142 UINT16 LinkBandwidthManagement : 1;\r
143 UINT16 LinkAutonomousBandwidth : 1;\r
144 } Bits;\r
145 UINT16 Uint16;\r
146} PCI_REG_PCIE_LINK_STATUS;\r
147\r
148typedef union {\r
149 struct {\r
150 UINT32 AttentionButton : 1;\r
151 UINT32 PowerController : 1;\r
152 UINT32 MrlSensor : 1;\r
153 UINT32 AttentionIndicator : 1;\r
154 UINT32 PowerIndicator : 1;\r
155 UINT32 HotPlugSurprise : 1;\r
156 UINT32 HotPlugCapable : 1;\r
157 UINT32 SlotPowerLimitValue : 8;\r
158 UINT32 SlotPowerLimitScale : 2;\r
159 UINT32 ElectromechanicalInterlock : 1;\r
160 UINT32 NoCommandCompleted : 1;\r
161 UINT32 PhysicalSlotNumber : 13;\r
162 } Bits;\r
163 UINT32 Uint32;\r
164} PCI_REG_PCIE_SLOT_CAPABILITY;\r
165\r
166typedef union {\r
167 struct {\r
168 UINT32 AttentionButtonPressed : 1;\r
169 UINT32 PowerFaultDetected : 1;\r
170 UINT32 MrlSensorChanged : 1;\r
171 UINT32 PresenceDetectChanged : 1;\r
172 UINT32 CommandCompletedInterrupt : 1;\r
173 UINT32 HotPlugInterrupt : 1;\r
174 UINT32 AttentionIndicator : 2;\r
175 UINT32 PowerIndicator : 2;\r
176 UINT32 PowerController : 1;\r
177 UINT32 ElectromechanicalInterlock : 1;\r
178 UINT32 DataLinkLayerStateChanged : 1;\r
179 UINT32 Reserved : 3;\r
180 } Bits;\r
181 UINT16 Uint16;\r
182} PCI_REG_PCIE_SLOT_CONTROL;\r
183\r
184typedef union {\r
185 struct {\r
186 UINT16 AttentionButtonPressed : 1;\r
187 UINT16 PowerFaultDetected : 1;\r
188 UINT16 MrlSensorChanged : 1;\r
189 UINT16 PresenceDetectChanged : 1;\r
190 UINT16 CommandCompleted : 1;\r
191 UINT16 MrlSensor : 1;\r
192 UINT16 PresenceDetect : 1;\r
193 UINT16 ElectromechanicalInterlock : 1;\r
194 UINT16 DataLinkLayerStateChanged : 1;\r
195 UINT16 Reserved : 7;\r
196 } Bits;\r
197 UINT16 Uint16;\r
198} PCI_REG_PCIE_SLOT_STATUS;\r
199\r
200typedef union {\r
201 struct {\r
202 UINT16 SystemErrorOnCorrectableError : 1;\r
203 UINT16 SystemErrorOnNonFatalError : 1;\r
204 UINT16 SystemErrorOnFatalError : 1;\r
205 UINT16 PmeInterrupt : 1;\r
206 UINT16 CrsSoftwareVisibility : 1;\r
207 UINT16 Reserved : 11;\r
208 } Bits;\r
209 UINT16 Uint16;\r
210} PCI_REG_PCIE_ROOT_CONTROL;\r
211\r
212typedef union {\r
213 struct {\r
214 UINT16 CrsSoftwareVisibility : 1;\r
215 UINT16 Reserved : 15;\r
216 } Bits;\r
217 UINT16 Uint16;\r
218} PCI_REG_PCIE_ROOT_CAPABILITY;\r
219\r
220typedef union {\r
221 struct {\r
222 UINT32 PmeRequesterId : 16;\r
223 UINT32 PmeStatus : 1;\r
224 UINT32 PmePending : 1;\r
225 UINT32 Reserved : 14;\r
226 } Bits;\r
227 UINT32 Uint32;\r
228} PCI_REG_PCIE_ROOT_STATUS;\r
229\r
230typedef union {\r
231 struct {\r
232 UINT32 CompletionTimeoutRanges : 4;\r
233 UINT32 CompletionTimeoutDisable : 1;\r
234 UINT32 AriForwarding : 1;\r
235 UINT32 AtomicOpRouting : 1;\r
236 UINT32 AtomicOp32Completer : 1;\r
237 UINT32 AtomicOp64Completer : 1;\r
238 UINT32 Cas128Completer : 1;\r
239 UINT32 NoRoEnabledPrPrPassing : 1;\r
240 UINT32 LtrMechanism : 1;\r
241 UINT32 TphCompleter : 2;\r
242 UINT32 Reserved : 4;\r
243 UINT32 Obff : 2;\r
244 UINT32 ExtendedFmtField : 1;\r
245 UINT32 EndEndTlpPrefix : 1;\r
246 UINT32 MaxEndEndTlpPrefixes : 2;\r
247 UINT32 Reserved2 : 8;\r
248 } Bits;\r
249 UINT32 Uint32;\r
250} PCI_REG_PCIE_DEVICE_CAPABILITY2;\r
251\r
252#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r
253#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1\r
254\r
255typedef union {\r
256 struct {\r
257 UINT16 CompletionTimeoutValue : 4;\r
258 UINT16 CompletionTimeoutDisable : 1;\r
259 UINT16 AriForwarding : 1;\r
260 UINT16 AtomicOpRequester : 1;\r
261 UINT16 AtomicOpEgressBlocking : 1;\r
262 UINT16 IdoRequest : 1;\r
263 UINT16 IdoCompletion : 1;\r
264 UINT16 LtrMechanism : 2;\r
265 UINT16 Reserved : 2;\r
266 UINT16 Obff : 2;\r
267 UINT16 EndEndTlpPrefixBlocking : 1;\r
268 } Bits;\r
269 UINT16 Uint16;\r
270} PCI_REG_PCIE_DEVICE_CONTROL2;\r
271\r
272#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0\r
273#define PCIE_COMPLETION_TIMEOUT_50US_100US 1\r
274#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2\r
275#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5\r
276#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6\r
277#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9\r
278#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10\r
279#define PCIE_COMPLETION_TIMEOUT_4S_13S 13\r
280#define PCIE_COMPLETION_TIMEOUT_17S_64S 14\r
281\r
282#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0\r
283#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1\r
284#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2\r
285#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3\r
286\r
287typedef union {\r
288 struct {\r
289 UINT32 Reserved : 1;\r
290 UINT32 LinkSpeedsVector : 7;\r
291 UINT32 Crosslink : 1;\r
292 UINT32 Reserved2 : 23;\r
293 } Bits;\r
294 UINT32 Uint32;\r
295} PCI_REG_PCIE_LINK_CAPABILITY2;\r
296\r
297typedef union {\r
298 struct {\r
299 UINT16 TargetLinkSpeed : 4;\r
300 UINT16 EnterCompliance : 1;\r
301 UINT16 HardwareAutonomousSpeedDisable : 1;\r
302 UINT16 SelectableDeemphasis : 1;\r
303 UINT16 TransmitMargin : 3;\r
304 UINT16 EnterModifiedCompliance : 1;\r
305 UINT16 ComplianceSos : 1;\r
306 UINT16 CompliancePresetDeemphasis : 4;\r
307 } Bits;\r
308 UINT16 Uint16;\r
309} PCI_REG_PCIE_LINK_CONTROL2;\r
310\r
311typedef union {\r
312 struct {\r
313 UINT16 CurrentDeemphasisLevel : 1;\r
314 UINT16 EqualizationComplete : 1;\r
315 UINT16 EqualizationPhase1Successful : 1;\r
316 UINT16 EqualizationPhase2Successful : 1;\r
317 UINT16 EqualizationPhase3Successful : 1;\r
318 UINT16 LinkEqualizationRequest : 1;\r
319 UINT16 Reserved : 10;\r
320 } Bits;\r
321 UINT16 Uint16;\r
322} PCI_REG_PCIE_LINK_STATUS2;\r
323\r
324typedef struct {\r
325 EFI_PCI_CAPABILITY_HDR Hdr;\r
326 PCI_REG_PCIE_CAPABILITY Capability;\r
327 PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;\r
328 PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;\r
329 PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;\r
330 PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;\r
331 PCI_REG_PCIE_LINK_CONTROL LinkControl;\r
332 PCI_REG_PCIE_LINK_STATUS LinkStatus;\r
333 PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;\r
334 PCI_REG_PCIE_SLOT_CONTROL SlotControl;\r
335 PCI_REG_PCIE_SLOT_STATUS SlotStatus;\r
336 PCI_REG_PCIE_ROOT_CONTROL RootControl;\r
337 PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;\r
338 PCI_REG_PCIE_ROOT_STATUS RootStatus;\r
339 PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;\r
340 PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;\r
341 UINT16 DeviceStatus2;\r
342 PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;\r
343 PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;\r
344 PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;\r
345 UINT32 SlotCapability2;\r
346 UINT16 SlotControl2;\r
347 UINT16 SlotStatus2;\r
348} PCI_CAPABILITY_PCIEXP;\r
349\r
533403e6 350#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\r
351#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\r
352#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\r
353#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20\r
354#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28\r
355#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20\r
356\r
357//\r
358// for SR-IOV\r
359//\r
360#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E\r
361#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F\r
362#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10\r
363#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11\r
364\r
365typedef struct {\r
366 UINT32 CapabilityHeader;\r
367 UINT32 Capability;\r
368 UINT16 Control;\r
369 UINT16 Status;\r
370 UINT16 InitialVFs;\r
371 UINT16 TotalVFs;\r
372 UINT16 NumVFs;\r
373 UINT8 FunctionDependencyLink;\r
374 UINT8 Reserved0;\r
375 UINT16 FirstVFOffset;\r
376 UINT16 VFStride;\r
377 UINT16 Reserved1;\r
378 UINT16 VFDeviceID;\r
379 UINT32 SupportedPageSize;\r
380 UINT32 SystemPageSize;\r
381 UINT32 VFBar[6];\r
382 UINT32 VFMigrationStateArrayOffset;\r
383} SR_IOV_CAPABILITY_REGISTER;\r
384\r
385#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04\r
386#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08\r
387#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A\r
388#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C\r
389#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E\r
390#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10\r
391#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12\r
392#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14\r
393#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16\r
394#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A\r
395#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C\r
396#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20\r
397#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24\r
398#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28\r
399#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C\r
400#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30\r
401#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34\r
402#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38\r
403#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C\r
404\r
a1d20250
JC		 405typedef struct {\r
406 UINT32 CapabilityId:16;\r
407 UINT32 CapabilityVersion:4;\r
408 UINT32 NextCapabilityOffset:12;\r
409} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;\r
410\r
411#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER\r
412\r
413#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001\r
414#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\r
415#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\r
416\r
cbedba86
RN		 417typedef union {\r
418 struct {\r
419 UINT32 Undefined : 1;\r
420 UINT32 Reserved : 3;\r
421 UINT32 DataLinkProtocolError : 1;\r
422 UINT32 SurpriseDownError : 1;\r
423 UINT32 Reserved2 : 6;\r
424 UINT32 PoisonedTlp : 1;\r
425 UINT32 FlowControlProtocolError : 1;\r
426 UINT32 CompletionTimeout : 1;\r
427 UINT32 CompleterAbort : 1;\r
428 UINT32 UnexpectedCompletion : 1;\r
429 UINT32 ReceiverOverflow : 1;\r
430 UINT32 MalformedTlp : 1;\r
431 UINT32 EcrcError : 1;\r
432 UINT32 UnsupportedRequestError : 1;\r
433 UINT32 AcsVoilation : 1;\r
434 UINT32 UncorrectableInternalError : 1;\r
435 UINT32 McBlockedTlp : 1;\r
436 UINT32 AtomicOpEgressBlocked : 1;\r
437 UINT32 TlpPrefixBlockedError : 1;\r
438 UINT32 Reserved3 : 6;\r
439 } Bits;\r
440 UINT32 Uint32;\r
441} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;\r
442\r
a1d20250
JC		 443typedef struct {\r
444 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
cbedba86
RN		 445 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;\r
446 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;\r
447 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;\r
a1d20250
JC		 448 UINT32 CorrectableErrorStatus;\r
449 UINT32 CorrectableErrorMask;\r
450 UINT32 AdvancedErrorCapabilitiesAndControl;\r
0a38a95a 451 UINT32 HeaderLog[4];\r
a1d20250
JC		 452 UINT32 RootErrorCommand;\r
453 UINT32 RootErrorStatus;\r
454 UINT16 ErrorSourceIdentification;\r
455 UINT16 CorrectableErrorSourceIdentification;\r
456 UINT32 TlpPrefixLog[4];\r
457} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;\r
458\r
459#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002\r
460#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009\r
461#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1\r
462\r
463typedef struct {\r
464 UINT32 VcResourceCapability:24;\r
465 UINT32 PortArbTableOffset:8;\r
466 UINT32 VcResourceControl;\r
467 UINT16 Reserved1;\r
468 UINT16 VcResourceStatus;\r
469} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;\r
470\r
471typedef struct {\r
472 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
473 UINT32 ExtendedVcCount:3;\r
474 UINT32 PortVcCapability1:29;\r
475 UINT32 PortVcCapability2:24;\r
476 UINT32 VcArbTableOffset:8;\r
477 UINT16 PortVcControl;\r
478 UINT16 PortVcStatus;\r
479 PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];\r
480} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;\r
481\r
482#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003\r
483#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1\r
484\r
485typedef struct {\r
486 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
487 UINT64 SerialNumber;\r
488} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;\r
489\r
490#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005\r
491#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1\r
492\r
493typedef struct {\r
494 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
495 UINT32 ElementSelfDescription;\r
496 UINT32 Reserved;\r
497 UINT32 LinkEntry[1];\r
498} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;\r
499\r
500#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)\r
501\r
502#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006\r
503#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1\r
504\r
505typedef struct {\r
506 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
507 UINT32 RootComplexLinkCapabilities;\r
508 UINT16 RootComplexLinkControl;\r
509 UINT16 RootComplexLinkStatus;\r
510} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;\r
511\r
512#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004\r
513#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1\r
514\r
515typedef struct {\r
516 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
517 UINT32 DataSelect:8;\r
518 UINT32 Reserved:24;\r
519 UINT32 Data;\r
520 UINT32 PowerBudgetCapability:1;\r
521 UINT32 Reserved2:7;\r
522 UINT32 Reserved3:24;\r
523} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;\r
524\r
525#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D\r
526#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1\r
527\r
528typedef struct {\r
529 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
530 UINT16 AcsCapability;\r
531 UINT16 AcsControl;\r
532 UINT8 EgressControlVectorArray[1];\r
533} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;\r
534\r
535#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))\r
536#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))\r
537\r
538#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007\r
539#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1\r
540\r
541typedef struct {\r
542 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
543 UINT32 AssociationBitmap;\r
544} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;\r
545\r
546#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008\r
547#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1\r
548\r
549typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;\r
550\r
551#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B\r
552#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1\r
553\r
554typedef struct {\r
555 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
556 UINT32 VendorSpecificHeader;\r
557 UINT8 VendorSpecific[1];\r
558} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;\r
559\r
560#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)\r
561\r
562#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A\r
563#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1\r
564\r
565typedef struct {\r
566 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
567 UINT16 VendorId;\r
568 UINT16 DeviceId;\r
569 UINT32 RcrbCapabilities;\r
570 UINT32 RcrbControl;\r
571 UINT32 Reserved;\r
572} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;\r
573\r
574#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012\r
575#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1\r
576\r
577typedef struct {\r
578 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
579 UINT16 MultiCastCapability;\r
580 UINT16 MulticastControl;\r
581 UINT64 McBaseAddress;\r
582 UINT64 McReceiveAddress;\r
583 UINT64 McBlockAll;\r
584 UINT64 McBlockUntranslated;\r
585 UINT64 McOverlayBar;\r
586} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;\r
587\r
588#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015\r
589#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1\r
590\r
591typedef struct {\r
592 UINT32 ResizableBarCapability;\r
593 UINT16 ResizableBarControl;\r
594 UINT16 Reserved;\r
595} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;\r
596\r
597typedef struct {\r
598 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
599 PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];\r
600} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;\r
601\r
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JC		 602#define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)\r
603\r
a1d20250
JC		 604#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E\r
605#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1\r
606\r
607typedef struct {\r
608 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
609 UINT16 AriCapability;\r
610 UINT16 AriControl;\r
611} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;\r
612\r
613#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016\r
614#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1\r
615\r
616typedef struct {\r
617 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
618 UINT32 DpaCapability;\r
619 UINT32 DpaLatencyIndicator;\r
620 UINT16 DpaStatus;\r
621 UINT16 DpaControl;\r
622 UINT8 DpaPowerAllocationArray[1];\r
623} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;\r
624\r
625#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))\r
626\r
627\r
628#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018\r
629#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1\r
630\r
631typedef struct {\r
632 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
633 UINT16 MaxSnoopLatency;\r
634 UINT16 MaxNoSnoopLatency;\r
635} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;\r
636\r
637#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017\r
638#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1\r
639\r
640typedef struct {\r
641 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
642 UINT32 TphRequesterCapability;\r
643 UINT32 TphRequesterControl;\r
644 UINT16 TphStTable[1];\r
645} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;\r
646\r
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JC		 647#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\r
648\r
cbedba86
RN		 649#pragma pack()\r
650\r
533403e6 651#endif\r
EFI Development Kit II mirror for PVE