projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| cbedba86 RN |
1 | /** @file\r |
| 2 | Support for the PCI Express 3.1 standard.\r | |
| 3 | \r | |
| 4 | This header file may not define all structures. Please extend as required.\r | |
| 5 | \r | |
| 6 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 9344f092 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| cbedba86 RN |
8 | \r |
| 9 | **/\r | |
| 10 | \r | |
| 11 | #ifndef _PCIEXPRESS31_H_\r | |
| 12 | #define _PCIEXPRESS31_H_\r | |
| 13 | \r | |
| 14 | #include <IndustryStandard/PciExpress30.h>\r | |
| 15 | \r | |
| 16 | #pragma pack(1)\r | |
| 17 | \r | |
| 18 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID 0x001E\r | |
| 19 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1 0x1\r | |
| 20 | \r | |
| 21 | typedef union {\r | |
| 22 | struct {\r | |
| 2f88bd3a MK |
23 | UINT32 PciPmL12 : 1;\r |
| 24 | UINT32 PciPmL11 : 1;\r | |
| 25 | UINT32 AspmL12 : 1;\r | |
| 26 | UINT32 AspmL11 : 1;\r | |
| 27 | UINT32 L1PmSubstates : 1;\r | |
| 28 | UINT32 Reserved : 3;\r | |
| 29 | UINT32 CommonModeRestoreTime : 8;\r | |
| 30 | UINT32 TPowerOnScale : 2;\r | |
| 31 | UINT32 Reserved2 : 1;\r | |
| 32 | UINT32 TPowerOnValue : 5;\r | |
| 33 | UINT32 Reserved3 : 8;\r | |
| cbedba86 | 34 | } Bits;\r |
| 2f88bd3a | 35 | UINT32 Uint32;\r |
| cbedba86 RN |
36 | } PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY;\r |
| 37 | \r | |
| 38 | typedef union {\r | |
| 39 | struct {\r | |
| 2f88bd3a MK |
40 | UINT32 PciPmL12 : 1;\r |
| 41 | UINT32 PciPmL11 : 1;\r | |
| 42 | UINT32 AspmL12 : 1;\r | |
| 43 | UINT32 AspmL11 : 1;\r | |
| 44 | UINT32 Reserved : 4;\r | |
| 45 | UINT32 CommonModeRestoreTime : 8;\r | |
| 46 | UINT32 LtrL12ThresholdValue : 10;\r | |
| 47 | UINT32 Reserved2 : 3;\r | |
| 48 | UINT32 LtrL12ThresholdScale : 3;\r | |
| cbedba86 | 49 | } Bits;\r |
| 2f88bd3a | 50 | UINT32 Uint32;\r |
| cbedba86 RN |
51 | } PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1;\r |
| 52 | \r | |
| 53 | typedef union {\r | |
| 54 | struct {\r | |
| 2f88bd3a MK |
55 | UINT32 TPowerOnScale : 2;\r |
| 56 | UINT32 Reserved : 1;\r | |
| 57 | UINT32 TPowerOnValue : 5;\r | |
| 58 | UINT32 Reserved2 : 24;\r | |
| cbedba86 | 59 | } Bits;\r |
| 2f88bd3a | 60 | UINT32 Uint32;\r |
| cbedba86 RN |
61 | } PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2;\r |
| 62 | \r | |
| 63 | typedef struct {\r | |
| 2f88bd3a MK |
64 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r |
| 65 | PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;\r | |
| 66 | PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1;\r | |
| 67 | PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;\r | |
| cbedba86 RN |
68 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;\r |
| 69 | \r | |
| 70 | #pragma pack()\r | |
| 71 | \r | |
| 72 | #endif\r |