projects / mirror_edk2.git / blame
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|---|---|---|
| 8805bd90 FP |
1 | /** @file\r |
| 2 | Support for the PCI Express 4.0 standard.\r | |
| 3 | \r | |
| 4 | This header file may not define all structures. Please extend as required.\r | |
| 5 | \r | |
| 6 | Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>\r | |
| 7 | This program and the accompanying materials\r | |
| 8 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 9 | which accompanies this distribution. The full text of the license may be found at\r | |
| 10 | http://opensource.org/licenses/bsd-license.php\r | |
| 11 | \r | |
| 12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 14 | \r | |
| 15 | **/\r | |
| 16 | \r | |
| 17 | #ifndef _PCIEXPRESS40_H_\r | |
| 18 | #define _PCIEXPRESS40_H_\r | |
| 19 | \r | |
| 20 | #include <IndustryStandard/PciExpress31.h>\r | |
| 21 | \r | |
| 22 | #pragma pack(1)\r | |
| 23 | \r | |
| 24 | /// The Physical Layer PCI Express Extended Capability definitions.\r | |
| 25 | ///\r | |
| 26 | /// Based on section 7.7.5 of PCI Express Base Specification 4.0.\r | |
| 27 | ///@{\r | |
| 28 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID 0x0026\r | |
| 29 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1\r | |
| 30 | \r | |
| 31 | // Register offsets from Physical Layer PCI-E Ext Cap Header\r | |
| 32 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04\r | |
| 33 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08\r | |
| 34 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C\r | |
| 35 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10\r | |
| 36 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14\r | |
| 37 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18\r | |
| 38 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20\r | |
| 39 | \r | |
| 40 | typedef union {\r | |
| 41 | struct {\r | |
| 42 | UINT32 Reserved : 32; // Reserved bit 0:31\r | |
| 43 | } Bits;\r | |
| 44 | UINT32 Uint32;\r | |
| 45 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;\r | |
| 46 | \r | |
| 47 | typedef union {\r | |
| 48 | struct {\r | |
| 49 | UINT32 Reserved : 32; // Reserved bit 0:31\r | |
| 50 | } Bits;\r | |
| 51 | UINT32 Uint32;\r | |
| 52 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;\r | |
| 53 | \r | |
| 54 | typedef union {\r | |
| 55 | struct {\r | |
| 56 | UINT32 EqualizationComplete : 1; // bit 0\r | |
| 57 | UINT32 EqualizationPhase1Success : 1; // bit 1\r | |
| 58 | UINT32 EqualizationPhase2Success : 1; // bit 2\r | |
| 59 | UINT32 EqualizationPhase3Success : 1; // bit 3\r | |
| 60 | UINT32 LinkEqualizationRequest : 1; // bit 4\r | |
| 61 | UINT32 Reserved : 27; // Reserved bit 5:31\r | |
| 62 | } Bits;\r | |
| 63 | UINT32 Uint32;\r | |
| 64 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;\r | |
| 65 | \r | |
| 66 | typedef union {\r | |
| 67 | struct {\r | |
| 68 | UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3\r | |
| 69 | UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7\r | |
| 70 | } Bits;\r | |
| 71 | UINT8 Uint8;\r | |
| 72 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;\r | |
| 73 | \r | |
| 74 | typedef struct {\r | |
| 75 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
| 76 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;\r | |
| 77 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;\r | |
| 78 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;\r | |
| 79 | UINT32 LocalDataParityMismatchStatus;\r | |
| 80 | UINT32 FirstRetimerDataParityMismatchStatus;\r | |
| 81 | UINT32 SecondRetimerDataParityMismatchStatus;\r | |
| 82 | UINT32 Reserved;\r | |
| 83 | PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\r | |
| 84 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;\r | |
| 85 | ///@}\r | |
| 86 | \r | |
| 87 | #pragma pack()\r | |
| 88 | \r | |
| 89 | #endif\r |