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e465aae0 FP |
1 | /** @file\r |
2 | Support for the PCI Express 5.0 standard.\r | |
3 | \r | |
4 | This header file may not define all structures. Please extend as required.\r | |
5 | \r | |
6 | Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>\r | |
7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
8 | \r | |
9 | **/\r | |
10 | \r | |
11 | #ifndef _PCIEXPRESS50_H_\r | |
12 | #define _PCIEXPRESS50_H_\r | |
13 | \r | |
14 | #include <IndustryStandard/PciExpress40.h>\r | |
15 | \r | |
16 | #pragma pack(1)\r | |
17 | \r | |
18 | /// The Physical Layer PCI Express Extended Capability definitions.\r | |
19 | ///\r | |
20 | /// Based on section 7.7.6 of PCI Express Base Specification 5.0.\r | |
21 | ///@{\r | |
22 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A\r | |
23 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1\r | |
24 | \r | |
25 | // Register offsets from Physical Layer PCI-E Ext Cap Header\r | |
2f88bd3a MK |
26 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04\r |
27 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08\r | |
28 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C\r | |
29 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10\r | |
30 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14\r | |
31 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18\r | |
32 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C\r | |
33 | #define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20\r | |
e465aae0 FP |
34 | \r |
35 | typedef union {\r | |
36 | struct {\r | |
2f88bd3a MK |
37 | UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0\r |
38 | UINT32 NoEqualizationNeededSupport : 1; // bit 1\r | |
39 | UINT32 Reserved1 : 6; // Reserved bit 2:7\r | |
40 | UINT32 ModifiedTSUsageMode0Support : 1; // bit 8\r | |
41 | UINT32 ModifiedTSUsageMode1Support : 1; // bit 9\r | |
42 | UINT32 ModifiedTSUsageMode2Support : 1; // bit 10\r | |
43 | UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15\r | |
44 | UINT32 Reserved2 : 16; // Reserved bit 16:31\r | |
e465aae0 | 45 | } Bits;\r |
2f88bd3a | 46 | UINT32 Uint32;\r |
e465aae0 FP |
47 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;\r |
48 | \r | |
49 | typedef union {\r | |
50 | struct {\r | |
2f88bd3a MK |
51 | UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0\r |
52 | UINT32 NoEqualizationNeededDisable : 1; // bit 1\r | |
53 | UINT32 Reserved1 : 6; // Reserved bit 2:7\r | |
54 | UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10\r | |
55 | UINT32 Reserved2 : 21; // Reserved bit 11:31\r | |
e465aae0 | 56 | } Bits;\r |
2f88bd3a | 57 | UINT32 Uint32;\r |
e465aae0 FP |
58 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;\r |
59 | \r | |
60 | typedef union {\r | |
61 | struct {\r | |
2f88bd3a MK |
62 | UINT32 EqualizationComplete : 1; // bit 0\r |
63 | UINT32 EqualizationPhase1Success : 1; // bit 1\r | |
64 | UINT32 EqualizationPhase2Success : 1; // bit 2\r | |
65 | UINT32 EqualizationPhase3Success : 1; // bit 3\r | |
66 | UINT32 LinkEqualizationRequest : 1; // bit 4\r | |
67 | UINT32 ModifiedTSRcvd : 1; // bit 5\r | |
68 | UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7\r | |
69 | UINT32 TransmitterPrecodingOn : 1; // bit 8\r | |
70 | UINT32 TransmitterPrecodeRequest : 1; // bit 9\r | |
71 | UINT32 NoEqualizationNeededRcvd : 1; // bit 10\r | |
72 | UINT32 Reserved : 21; // Reserved bit 11:31\r | |
e465aae0 | 73 | } Bits;\r |
2f88bd3a | 74 | UINT32 Uint32;\r |
e465aae0 FP |
75 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;\r |
76 | \r | |
77 | typedef union {\r | |
78 | struct {\r | |
2f88bd3a MK |
79 | UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2\r |
80 | UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15\r | |
81 | UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31\r | |
e465aae0 | 82 | } Bits;\r |
2f88bd3a | 83 | UINT32 Uint32;\r |
e465aae0 FP |
84 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;\r |
85 | \r | |
86 | typedef union {\r | |
87 | struct {\r | |
2f88bd3a MK |
88 | UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23\r |
89 | UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25\r | |
90 | UINT32 Reserved : 6; // Reserved bit 26:31\r | |
e465aae0 | 91 | } Bits;\r |
2f88bd3a | 92 | UINT32 Uint32;\r |
e465aae0 FP |
93 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;\r |
94 | \r | |
95 | typedef union {\r | |
96 | struct {\r | |
2f88bd3a MK |
97 | UINT32 TransModifiedTSUsageMode : 3; // bit 0:2\r |
98 | UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15\r | |
99 | UINT32 TransModifiedTSVendorId : 16; // bit 16:31\r | |
e465aae0 | 100 | } Bits;\r |
2f88bd3a | 101 | UINT32 Uint32;\r |
e465aae0 FP |
102 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;\r |
103 | \r | |
104 | typedef union {\r | |
105 | struct {\r | |
2f88bd3a MK |
106 | UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23\r |
107 | UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25\r | |
108 | UINT32 Reserved : 6; // Reserved bit 26:31\r | |
e465aae0 | 109 | } Bits;\r |
2f88bd3a | 110 | UINT32 Uint32;\r |
e465aae0 FP |
111 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;\r |
112 | \r | |
113 | typedef union {\r | |
114 | struct {\r | |
2f88bd3a MK |
115 | UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3\r |
116 | UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7\r | |
e465aae0 | 117 | } Bits;\r |
2f88bd3a | 118 | UINT8 Uint8;\r |
e465aae0 FP |
119 | } PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;\r |
120 | \r | |
121 | typedef struct {\r | |
2f88bd3a MK |
122 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r |
123 | PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;\r | |
124 | PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;\r | |
125 | PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;\r | |
126 | PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;\r | |
127 | PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;\r | |
128 | PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;\r | |
129 | PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;\r | |
130 | PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\r | |
e465aae0 FP |
131 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;\r |
132 | ///@}\r | |
133 | \r | |
134 | #pragma pack()\r | |
135 | \r | |
136 | #endif\r |