MdePkg ACPI: Correct processor struct of PPTT

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / SdramSpd.h

/** @file\r
  This file contains definitions for the SPD fields on an SDRAM.\r
\r
  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
**/\r
\r
#ifndef _SDRAM_SPD_H_\r
#define _SDRAM_SPD_H_\r
\r
#include <IndustryStandard/SdramSpdDdr3.h>\r
#include <IndustryStandard/SdramSpdDdr4.h>\r
#include <IndustryStandard/SdramSpdLpDdr.h>\r
\r
//\r
// SDRAM SPD field definitions\r
//\r
#define SPD_MEMORY_TYPE                 2\r
#define SPD_SDRAM_ROW_ADDR              3\r
#define SPD_SDRAM_COL_ADDR              4\r
#define SPD_SDRAM_MODULE_ROWS           5\r
#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6\r
#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7\r
#define SPD_SDRAM_ECC_SUPPORT           11\r
#define SPD_SDRAM_REFRESH               12\r
#define SPD_SDRAM_WIDTH                 13\r
#define SPD_SDRAM_ERROR_WIDTH           14\r
#define SPD_SDRAM_BURST_LENGTH          16\r
#define SPD_SDRAM_NO_OF_BANKS           17\r
#define SPD_SDRAM_CAS_LATENCY           18\r
#define SPD_SDRAM_MODULE_ATTR           21\r
\r
#define SPD_SDRAM_TCLK1_PULSE           9   ///< cycle time for highest cas latency\r
#define SPD_SDRAM_TAC1_PULSE            10  ///< access time for highest cas latency\r
#define SPD_SDRAM_TCLK2_PULSE           23  ///< cycle time for 2nd highest cas latency\r
#define SPD_SDRAM_TAC2_PULSE            24  ///< access time for 2nd highest cas latency\r
#define SPD_SDRAM_TCLK3_PULSE           25  ///< cycle time for 3rd highest cas latency\r
#define SPD_SDRAM_TAC3_PULSE            26  ///< access time for 3rd highest cas latency\r
#define SPD_SDRAM_MIN_PRECHARGE         27\r
#define SPD_SDRAM_ACTIVE_MIN            28\r
#define SPD_SDRAM_RAS_CAS               29\r
#define SPD_SDRAM_RAS_PULSE             30\r
#define SPD_SDRAM_DENSITY               31\r
\r
//\r
// Memory Type Definitions\r
//\r
#define SPD_VAL_SDR_TYPE  4       ///< SDR SDRAM memory\r
#define SPD_VAL_DDR_TYPE  7       ///< DDR SDRAM memory\r
#define SPD_VAL_DDR2_TYPE 8       ///< DDR2 SDRAM memory\r
#define SPD_VAL_DDR3_TYPE 11      ///< DDR3 SDRAM memory\r
#define SPD_VAL_DDR4_TYPE 12      ///< DDR4 SDRAM memory\r
#define SPD_VAL_LPDDR3_TYPE 15    ///< LPDDR3 SDRAM memory\r
#define SPD_VAL_LPDDR4_TYPE 16    ///< LPDDR4 SDRAM memory\r
\r
//\r
// ECC Type Definitions\r
//\r
#define SPD_ECC_TYPE_NONE   0x00  ///< No error checking\r
#define SPD_ECC_TYPE_PARITY 0x01  ///< No error checking\r
#define SPD_ECC_TYPE_ECC    0x02  ///< Error checking only\r
//\r
// Module Attributes (Bit positions)\r
//\r
#define SPD_BUFFERED    0x01\r
#define SPD_REGISTERED  0x02\r
\r
#endif\r