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LG		 1/** @file\r
2 This file contains definitions for SPD DDR3.\r
3\r
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13 @par Revision Reference:\r
14 - Serial Presence Detect (SPD) for DDR3 SDRAM Modules Document Release 6\r
15 http://www.jedec.org/sites/default/files/docs/4_01_02_11R21A.pdf\r
16**/\r
17\r
18#ifndef _SDRAM_SPD_DDR3_H_\r
19#define _SDRAM_SPD_DDR3_H_\r
20\r
21#pragma pack (push, 1)\r
22\r
23typedef union {\r
24 struct {\r
25 UINT8 BytesUsed : 4; ///< Bits 3:0\r
26 UINT8 BytesTotal : 3; ///< Bits 6:4\r
27 UINT8 CrcCoverage : 1; ///< Bits 7:7\r
28 } Bits;\r
29 UINT8 Data;\r
30} SPD3_DEVICE_DESCRIPTION_STRUCT;\r
31\r
32typedef union {\r
33 struct {\r
34 UINT8 Minor : 4; ///< Bits 3:0\r
35 UINT8 Major : 4; ///< Bits 7:4\r
36 } Bits;\r
37 UINT8 Data;\r
38} SPD3_REVISION_STRUCT;\r
39\r
40typedef union {\r
41 struct {\r
42 UINT8 Type : 8; ///< Bits 7:0\r
43 } Bits;\r
44 UINT8 Data;\r
45} SPD3_DRAM_DEVICE_TYPE_STRUCT;\r
46\r
47typedef union {\r
48 struct {\r
49 UINT8 ModuleType : 4; ///< Bits 3:0\r
50 UINT8 Reserved : 4; ///< Bits 7:4\r
51 } Bits;\r
52 UINT8 Data;\r
53} SPD3_MODULE_TYPE_STRUCT;\r
54\r
55typedef union {\r
56 struct {\r
57 UINT8 Density : 4; ///< Bits 3:0\r
58 UINT8 BankAddress : 3; ///< Bits 6:4\r
59 UINT8 Reserved : 1; ///< Bits 7:7\r
60 } Bits;\r
61 UINT8 Data;\r
62} SPD3_SDRAM_DENSITY_BANKS_STRUCT;\r
63\r
64typedef union {\r
65 struct {\r
66 UINT8 ColumnAddress : 3; ///< Bits 2:0\r
67 UINT8 RowAddress : 3; ///< Bits 5:3\r
68 UINT8 Reserved : 2; ///< Bits 7:6\r
69 } Bits;\r
70 UINT8 Data;\r
71} SPD3_SDRAM_ADDRESSING_STRUCT;\r
72\r
73typedef union {\r
74 struct {\r
75 UINT8 OperationAt1_50 : 1; ///< Bits 0:0\r
76 UINT8 OperationAt1_35 : 1; ///< Bits 1:1\r
77 UINT8 OperationAt1_25 : 1; ///< Bits 2:2\r
78 UINT8 Reserved : 5; ///< Bits 7:3\r
79 } Bits;\r
80 UINT8 Data;\r
81} SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT;\r
82\r
83typedef union {\r
84 struct {\r
85 UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
86 UINT8 RankCount : 3; ///< Bits 5:3\r
87 UINT8 Reserved : 2; ///< Bits 7:6\r
88 } Bits;\r
89 UINT8 Data;\r
90} SPD3_MODULE_ORGANIZATION_STRUCT;\r
91\r
92typedef union {\r
93 struct {\r
94 UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
95 UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
96 UINT8 Reserved : 3; ///< Bits 7:5\r
97 } Bits;\r
98 UINT8 Data;\r
99} SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r
100\r
101typedef union {\r
102 struct {\r
103 UINT8 Divisor : 4; ///< Bits 3:0\r
104 UINT8 Dividend : 4; ///< Bits 7:4\r
105 } Bits;\r
106 UINT8 Data;\r
107} SPD3_FINE_TIMEBASE_STRUCT;\r
108\r
109typedef union {\r
110 struct {\r
111 UINT8 Dividend : 8; ///< Bits 7:0\r
112 } Bits;\r
113 UINT8 Data;\r
114} SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;\r
115\r
116typedef union {\r
117 struct {\r
118 UINT8 Divisor : 8; ///< Bits 7:0\r
119 } Bits;\r
120 UINT8 Data;\r
121} SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT;\r
122\r
123typedef struct {\r
124 SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend\r
125 SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor\r
126} SPD3_MEDIUM_TIMEBASE;\r
127\r
128typedef union {\r
129 struct {\r
130 UINT8 tCKmin : 8; ///< Bits 7:0\r
131 } Bits;\r
132 UINT8 Data;\r
133} SPD3_TCK_MIN_MTB_STRUCT;\r
134\r
135typedef union {\r
136 struct {\r
137 UINT16 Cl4 : 1; ///< Bits 0:0\r
138 UINT16 Cl5 : 1; ///< Bits 1:1\r
139 UINT16 Cl6 : 1; ///< Bits 2:2\r
140 UINT16 Cl7 : 1; ///< Bits 3:3\r
141 UINT16 Cl8 : 1; ///< Bits 4:4\r
142 UINT16 Cl9 : 1; ///< Bits 5:5\r
143 UINT16 Cl10 : 1; ///< Bits 6:6\r
144 UINT16 Cl11 : 1; ///< Bits 7:7\r
145 UINT16 Cl12 : 1; ///< Bits 8:8\r
146 UINT16 Cl13 : 1; ///< Bits 9:9\r
147 UINT16 Cl14 : 1; ///< Bits 10:10\r
148 UINT16 Cl15 : 1; ///< Bits 11:11\r
149 UINT16 Cl16 : 1; ///< Bits 12:12\r
150 UINT16 Cl17 : 1; ///< Bits 13:13\r
151 UINT16 Cl18 : 1; ///< Bits 14:14\r
152 UINT16 Reserved : 1; ///< Bits 15:15\r
153 } Bits;\r
154 UINT16 Data;\r
155 UINT8 Data8[2];\r
156} SPD3_CAS_LATENCIES_SUPPORTED_STRUCT;\r
157\r
158typedef union {\r
159 struct {\r
160 UINT8 tAAmin : 8; ///< Bits 7:0\r
161 } Bits;\r
162 UINT8 Data;\r
163} SPD3_TAA_MIN_MTB_STRUCT;\r
164\r
165typedef union {\r
166 struct {\r
167 UINT8 tWRmin : 8; ///< Bits 7:0\r
168 } Bits;\r
169 UINT8 Data;\r
170} SPD3_TWR_MIN_MTB_STRUCT;\r
171\r
172typedef union {\r
173 struct {\r
174 UINT8 tRCDmin : 8; ///< Bits 7:0\r
175 } Bits;\r
176 UINT8 Data;\r
177} SPD3_TRCD_MIN_MTB_STRUCT;\r
178\r
179typedef union {\r
180 struct {\r
181 UINT8 tRRDmin : 8; ///< Bits 7:0\r
182 } Bits;\r
183 UINT8 Data;\r
184} SPD3_TRRD_MIN_MTB_STRUCT;\r
185\r
186typedef union {\r
187 struct {\r
188 UINT8 tRPmin : 8; ///< Bits 7:0\r
189 } Bits;\r
190 UINT8 Data;\r
191} SPD3_TRP_MIN_MTB_STRUCT;\r
192\r
193typedef union {\r
194 struct {\r
195 UINT8 tRASminUpper : 4; ///< Bits 3:0\r
196 UINT8 tRCminUpper : 4; ///< Bits 7:4\r
197 } Bits;\r
198 UINT8 Data;\r
199} SPD3_TRAS_TRC_MIN_MTB_STRUCT;\r
200\r
201typedef union {\r
202 struct {\r
203 UINT8 tRASmin : 8; ///< Bits 7:0\r
204 } Bits;\r
205 UINT8 Data;\r
206} SPD3_TRAS_MIN_MTB_STRUCT;\r
207\r
208typedef union {\r
209 struct {\r
210 UINT8 tRCmin : 8; ///< Bits 7:0\r
211 } Bits;\r
212 UINT8 Data;\r
213} SPD3_TRC_MIN_MTB_STRUCT;\r
214\r
215typedef union {\r
216 struct {\r
217 UINT16 tRFCmin : 16; ///< Bits 15:0\r
218 } Bits;\r
219 UINT16 Data;\r
220 UINT8 Data8[2];\r
221} SPD3_TRFC_MIN_MTB_STRUCT;\r
222\r
223typedef union {\r
224 struct {\r
225 UINT8 tWTRmin : 8; ///< Bits 7:0\r
226 } Bits;\r
227 UINT8 Data;\r
228} SPD3_TWTR_MIN_MTB_STRUCT;\r
229\r
230typedef union {\r
231 struct {\r
232 UINT8 tRTPmin : 8; ///< Bits 7:0\r
233 } Bits;\r
234 UINT8 Data;\r
235} SPD3_TRTP_MIN_MTB_STRUCT;\r
236\r
237typedef union {\r
238 struct {\r
239 UINT8 tFAWminUpper : 4; ///< Bits 3:0\r
240 UINT8 Reserved : 4; ///< Bits 7:4\r
241 } Bits;\r
242 UINT8 Data;\r
243} SPD3_TFAW_MIN_MTB_UPPER_STRUCT;\r
244\r
245typedef union {\r
246 struct {\r
247 UINT8 tFAWmin : 8; ///< Bits 7:0\r
248 } Bits;\r
249 UINT8 Data;\r
250} SPD3_TFAW_MIN_MTB_STRUCT;\r
251\r
252typedef union {\r
253 struct {\r
254 UINT8 Rzq6 : 1; ///< Bits 0:0\r
255 UINT8 Rzq7 : 1; ///< Bits 1:1\r
256 UINT8 Reserved : 5; ///< Bits 6:2\r
257 UINT8 DllOff : 1; ///< Bits 7:7\r
258 } Bits;\r
259 UINT8 Data;\r
260} SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
261\r
262typedef union {\r
263 struct {\r
264 UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0\r
265 UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1\r
266 UINT8 AutoSelfRefresh : 1; ///< Bits 2:2\r
267 UINT8 OnDieThermalSensor : 1; ///< Bits 3:3\r
268 UINT8 Reserved : 3; ///< Bits 6:4\r
269 UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7\r
270 } Bits;\r
271 UINT8 Data;\r
272} SPD3_SDRAM_THERMAL_REFRESH_STRUCT;\r
273\r
274typedef union {\r
275 struct {\r
276 UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0\r
277 UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
278 } Bits;\r
279 UINT8 Data;\r
280} SPD3_MODULE_THERMAL_SENSOR_STRUCT;\r
281\r
282typedef union {\r
283 struct {\r
284 UINT8 SignalLoading : 2; ///< Bits 1:0\r
285 UINT8 Reserved : 2; ///< Bits 3:2\r
286 UINT8 DieCount : 3; ///< Bits 6:4\r
287 UINT8 SdramDeviceType : 1; ///< Bits 7:7\r
288 } Bits;\r
289 UINT8 Data;\r
290} SPD3_SDRAM_DEVICE_TYPE_STRUCT;\r
291\r
292typedef union {\r
293 struct {\r
294 INT8 tCKminFine : 8; ///< Bits 7:0\r
295 } Bits;\r
296 INT8 Data;\r
297} SPD3_TCK_MIN_FTB_STRUCT;\r
298\r
299typedef union {\r
300 struct {\r
301 INT8 tAAminFine : 8; ///< Bits 7:0\r
302 } Bits;\r
303 INT8 Data;\r
304} SPD3_TAA_MIN_FTB_STRUCT;\r
305\r
306typedef union {\r
307 struct {\r
308 INT8 tRCDminFine : 8; ///< Bits 7:0\r
309 } Bits;\r
310 INT8 Data;\r
311} SPD3_TRCD_MIN_FTB_STRUCT;\r
312\r
313typedef union {\r
314 struct {\r
315 INT8 tRPminFine : 8; ///< Bits 7:0\r
316 } Bits;\r
317 INT8 Data;\r
318} SPD3_TRP_MIN_FTB_STRUCT;\r
319\r
320typedef union {\r
321 struct {\r
322 INT8 tRCminFine : 8; ///< Bits 7:0\r
323 } Bits;\r
324 INT8 Data;\r
325} SPD3_TRC_MIN_FTB_STRUCT;\r
326\r
327typedef union {\r
328 struct {\r
329 UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
330 UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
331 UINT8 VendorSpecific : 2; ///< Bits 7:6\r
332 } Bits;\r
333 UINT8 Data;\r
334} SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT;\r
335\r
336typedef union {\r
337 struct {\r
338 UINT8 Height : 5; ///< Bits 4:0\r
339 UINT8 RawCardExtension : 3; ///< Bits 7:5\r
340 } Bits;\r
341 UINT8 Data;\r
342} SPD3_UNBUF_MODULE_NOMINAL_HEIGHT;\r
343\r
344typedef union {\r
345 struct {\r
346 UINT8 FrontThickness : 4; ///< Bits 3:0\r
347 UINT8 BackThickness : 4; ///< Bits 7:4\r
348 } Bits;\r
349 UINT8 Data;\r
350} SPD3_UNBUF_MODULE_NOMINAL_THICKNESS;\r
351\r
352typedef union {\r
353 struct {\r
354 UINT8 Card : 5; ///< Bits 4:0\r
355 UINT8 Revision : 2; ///< Bits 6:5\r
356 UINT8 Extension : 1; ///< Bits 7:7\r
357 } Bits;\r
358 UINT8 Data;\r
359} SPD3_UNBUF_REFERENCE_RAW_CARD;\r
360\r
361typedef union {\r
362 struct {\r
363 UINT8 MappingRank1 : 1; ///< Bits 0:0\r
364 UINT8 Reserved : 7; ///< Bits 7:1\r
365 } Bits;\r
366 UINT8 Data;\r
367} SPD3_UNBUF_ADDRESS_MAPPING;\r
368\r
369typedef union {\r
370 struct {\r
371 UINT8 Height : 5; ///< Bits 4:0\r
372 UINT8 Reserved : 3; ///< Bits 7:5\r
373 } Bits;\r
374 UINT8 Data;\r
375} SPD3_RDIMM_MODULE_NOMINAL_HEIGHT;\r
376\r
377typedef union {\r
378 struct {\r
379 UINT8 FrontThickness : 4; ///< Bits 3:0\r
380 UINT8 BackThickness : 4; ///< Bits 7:4\r
381 } Bits;\r
382 UINT8 Data;\r
383} SPD3_RDIMM_MODULE_NOMINAL_THICKNESS;\r
384\r
385typedef union {\r
386 struct {\r
387 UINT8 Card : 5; ///< Bits 4:0\r
388 UINT8 Revision : 2; ///< Bits 6:5\r
389 UINT8 Extension : 1; ///< Bits 7:7\r
390 } Bits;\r
391 UINT8 Data;\r
392} SPD3_RDIMM_REFERENCE_RAW_CARD;\r
393\r
394typedef union {\r
395 struct {\r
396 UINT8 RegisterCount : 2; ///< Bits 1:0\r
397 UINT8 DramRowCount : 2; ///< Bits 3:2\r
398 UINT8 RegisterType : 4; ///< Bits 7:4\r
399 } Bits;\r
400 UINT8 Data;\r
401} SPD3_RDIMM_MODULE_ATTRIBUTES;\r
402\r
403typedef union {\r
404 struct {\r
405 UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
406 UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
407 } Bits;\r
408 UINT8 Data;\r
409} SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r
410\r
411typedef union {\r
412 struct {\r
413 UINT16 ContinuationCount : 7; ///< Bits 6:0\r
414 UINT16 ContinuationParity : 1; ///< Bits 7:7\r
415 UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
416 } Bits;\r
417 UINT16 Data;\r
418 UINT8 Data8[2];\r
419} SPD3_MANUFACTURER_ID_CODE;\r
420\r
421typedef union {\r
422 struct {\r
423 UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
424 } Bits;\r
425 UINT8 Data;\r
426} SPD3_RDIMM_REGISTER_REVISION_NUMBER;\r
427\r
428typedef union {\r
429 struct {\r
430 UINT8 Bit0 : 1; ///< Bits 0:0\r
431 UINT8 Bit1 : 1; ///< Bits 1:1\r
432 UINT8 Bit2 : 1; ///< Bits 2:2\r
433 UINT8 Reserved : 5; ///< Bits 7:3\r
434 } Bits;\r
435 UINT8 Data;\r
436} SPD3_RDIMM_REGISTER_TYPE;\r
437\r
438typedef union {\r
439 struct {\r
440 UINT8 Reserved : 4; ///< Bits 0:3\r
441 UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4\r
442 UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6\r
443 } Bits;\r
444 UINT8 Data;\r
445} SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS;\r
446\r
447typedef union {\r
448 struct {\r
449 UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1\r
450 UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2\r
451 UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
452 UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
453 } Bits;\r
454 UINT8 Data;\r
455} SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK;\r
456\r
457typedef union {\r
458 struct {\r
459 UINT8 Reserved0 : 4; ///< Bits 0:3\r
460 UINT8 Reserved1 : 4; ///< Bits 7:4\r
461 } Bits;\r
462 UINT8 Data;\r
463} SPD3_RDIMM_REGISTER_CONTROL_RESERVED;\r
464\r
465typedef union {\r
466 struct {\r
467 UINT8 Height : 5; ///< Bits 4:0\r
468 UINT8 Reserved : 3; ///< Bits 7:5\r
469 } Bits;\r
470 UINT8 Data;\r
471} SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT;\r
472\r
473typedef union {\r
474 struct {\r
475 UINT8 FrontThickness : 4; ///< Bits 3:0\r
476 UINT8 BackThickness : 4; ///< Bits 7:4\r
477 } Bits;\r
478 UINT8 Data;\r
479} SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS;\r
480\r
481typedef union {\r
482 struct {\r
483 UINT8 Card : 5; ///< Bits 4:0\r
484 UINT8 Revision : 2; ///< Bits 6:5\r
485 UINT8 Extension : 1; ///< Bits 7:7\r
486 } Bits;\r
487 UINT8 Data;\r
488} SPD3_LRDIMM_REFERENCE_RAW_CARD;\r
489\r
490typedef union {\r
491 struct {\r
492 UINT8 RegisterCount : 2; ///< Bits 1:0\r
493 UINT8 DramRowCount : 2; ///< Bits 3:2\r
494 UINT8 RegisterType : 4; ///< Bits 7:4\r
495 } Bits;\r
496 UINT8 Data;\r
497} SPD3_LRDIMM_MODULE_ATTRIBUTES;\r
498\r
499typedef union {\r
500 struct {\r
501 UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0\r
502 UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1\r
503 UINT8 Reserved0 : 1; ///< Bits 2:2\r
504 UINT8 Reserved1 : 1; ///< Bits 3:3\r
505 UINT8 AddressCommandOutputs : 2; ///< Bits 5:4\r
506 UINT8 QxCS_nOutputs : 2; ///< Bits 7:6\r
507 } Bits;\r
508 UINT8 Data;\r
509} SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH;\r
510\r
511typedef union {\r
512 struct {\r
513 UINT8 QxOdtOutputs : 2; ///< Bits 1:0\r
514 UINT8 QxCkeOutputs : 2; ///< Bits 3:2\r
515 UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
516 UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
517 } Bits;\r
518 UINT8 Data;\r
519} SPD3_LRDIMM_TIMING_DRIVE_STRENGTH;\r
520\r
521typedef union {\r
522 struct {\r
523 UINT8 YExtendedDelay : 2; ///< Bits 1:0\r
524 UINT8 QxCS_n : 2; ///< Bits 3:2\r
525 UINT8 QxOdt : 2; ///< Bits 5:4\r
526 UINT8 QxCke : 2; ///< Bits 7:6\r
527 } Bits;\r
528 UINT8 Data;\r
529} SPD3_LRDIMM_EXTENDED_DELAY;\r
530\r
531typedef union {\r
532 struct {\r
533 UINT8 DelayY : 3; ///< Bits 2:0\r
534 UINT8 Reserved : 1; ///< Bits 3:3\r
535 UINT8 QxCS_n : 4; ///< Bits 7:4\r
536 } Bits;\r
537 UINT8 Data;\r
538} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA;\r
539\r
540typedef union {\r
541 struct {\r
542 UINT8 QxCS_n : 4; ///< Bits 3:0\r
543 UINT8 QxOdt : 4; ///< Bits 7:4\r
544 } Bits;\r
545 UINT8 Data;\r
546} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE;\r
547\r
548typedef union {\r
549 struct {\r
550 UINT8 RC8MdqOdtStrength : 3; ///< Bits 2:0\r
551 UINT8 RC8Reserved : 1; ///< Bits 3:3\r
552 UINT8 RC9MdqOdtStrength : 3; ///< Bits 6:4\r
553 UINT8 RC9Reserved : 1; ///< Bits 7:7\r
554 } Bits;\r
555 UINT8 Data;\r
556} SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH;\r
557\r
558typedef union {\r
559 struct {\r
560 UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0\r
561 UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1\r
562 UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2\r
563 UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3\r
564 UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4\r
565 UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5\r
566 UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6\r
567 UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7\r
568 } Bits;\r
569 UINT8 Data;\r
570} SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL;\r
571\r
572typedef union {\r
573 struct {\r
574 UINT8 Driver_Impedance : 2; ///< Bits 1:0\r
575 UINT8 Rtt_Nom : 3; ///< Bits 4:2\r
576 UINT8 Reserved : 1; ///< Bits 5:5\r
577 UINT8 Rtt_WR : 2; ///< Bits 7:6\r
578 } Bits;\r
579 UINT8 Data;\r
580} SPD3_LRDIMM_MR_1_2;\r
581\r
582typedef union {\r
583 struct {\r
584 UINT8 MinimumDelayTime : 7; ///< Bits 0:6\r
585 UINT8 Reserved : 1; ///< Bits 7:7\r
586 } Bits;\r
587 UINT8 Data;\r
588} SPD3_LRDIMM_MODULE_DELAY_TIME;\r
589\r
590typedef struct {\r
591 UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
592 UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
593} SPD3_MANUFACTURING_DATE;\r
594\r
595typedef union {\r
596 UINT32 Data;\r
597 UINT16 SerialNumber16[2];\r
598 UINT8 SerialNumber8[4];\r
599} SPD3_MANUFACTURER_SERIAL_NUMBER;\r
600\r
601typedef struct {\r
602 UINT8 Location; ///< Module Manufacturing Location\r
603} SPD3_MANUFACTURING_LOCATION;\r
604\r
605typedef struct {\r
606 SPD3_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
607 SPD3_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
608 SPD3_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
609 SPD3_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
610} SPD3_UNIQUE_MODULE_ID;\r
611\r
612typedef union {\r
613 UINT16 Crc[1];\r
614 UINT8 Data8[2];\r
615} SPD3_CYCLIC_REDUNDANCY_CODE;\r
616\r
617typedef struct {\r
618 SPD3_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
619 SPD3_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
620 SPD3_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
621 SPD3_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
622 SPD3_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
623 SPD3_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
624 SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD\r
625 SPD3_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization\r
626 SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width\r
627 SPD3_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor\r
628 SPD3_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend\r
629 SPD3_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin)\r
630 UINT8 Reserved0; ///< 13 Reserved\r
631 SPD3_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported\r
632 SPD3_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin)\r
633 SPD3_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin)\r
634 SPD3_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
635 SPD3_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)\r
636 SPD3_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin)\r
637 SPD3_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC\r
638 SPD3_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r
639 SPD3_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r
640 SPD3_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin)\r
641 SPD3_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)\r
642 SPD3_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)\r
643 SPD3_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW\r
644 SPD3_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)\r
645 SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features\r
646 SPD3_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options\r
647 SPD3_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor\r
648 SPD3_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type\r
649 SPD3_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r
650 SPD3_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
651 SPD3_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
652 SPD3_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin)\r
653 SPD3_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r
654 UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved\r
655 SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT MacValue; ///< 41 SDRAM Maximum Active Count (MAC) Value\r
656 UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved\r
657} SPD3_BASE_SECTION;\r
658\r
659typedef struct {\r
660 SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
661 SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
662 SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
663 SPD3_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM\r
664 UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved\r
665} SPD3_MODULE_UNBUFFERED;\r
666\r
667typedef struct {\r
668 SPD3_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
669 SPD3_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
670 SPD3_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
671 SPD3_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes\r
672 SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution\r
673 SPD3_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 65-66 Register Manufacturer ID Code\r
674 SPD3_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number\r
675 SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type\r
676 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved\r
677 SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address\r
678 SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock\r
679 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor\r
680 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved\r
681 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved\r
682 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved\r
683 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved\r
684 UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved\r
685} SPD3_MODULE_REGISTERED;\r
686\r
687typedef struct {\r
688 SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
689 SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
690 SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
691 UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved\r
692} SPD3_MODULE_CLOCKED;\r
693\r
694typedef struct {\r
695 SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
696 SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
697 SPD3_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
698 SPD3_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes\r
699 UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number\r
700 SPD3_MANUFACTURER_ID_CODE ManufacturerIdCode; ///< 65-66 Memory Buffer Manufacturer ID Code\r
701 SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCaCs; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS\r
702 SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y\r
703 SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE\r
704 SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCsCa; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA\r
705 SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForOdtCke; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
706 SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
707 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
708 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
709 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
710 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
711 SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066\r
712 SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1333_1600; ///< 78 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
713 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
714 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
715 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
716 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
717 SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066\r
718 SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1866_2133; ///< 84 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
719 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
720 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
721 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
722 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
723 SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066\r
724 SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V\r
725 SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V\r
726 SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V\r
727 SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V\r
728 SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V\r
729 SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V\r
730 UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved\r
731 UINT8 PersonalityByte[116 - 102 + 1]; ///< 102-116 Memory Buffer Personality Bytes\r
732} SPD3_MODULE_LOADREDUCED;\r
733\r
734typedef union {\r
735 SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r
736 SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r
737 SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types\r
738 SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r
739} SPD3_MODULE_SPECIFIC;\r
740\r
741typedef struct {\r
742 UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number\r
743} SPD3_MODULE_PART_NUMBER;\r
744\r
745typedef struct {\r
746 UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code\r
747} SPD3_MODULE_REVISION_CODE;\r
748\r
749typedef struct {\r
750 UINT8 ManufacturerSpecificData[175 - 150 + 1];///< 150-175 Manufacturer's Specific Data\r
751} SPD3_MANUFACTURER_SPECIFIC;\r
752\r
753///\r
754/// DDR3 Serial Presence Detect structure\r
755///\r
756typedef struct {\r
757 SPD3_BASE_SECTION General; ///< 0-59 General Section\r
758 SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section\r
759 SPD3_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID\r
760 SPD3_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
761 SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number\r
762 SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code\r
763 SPD3_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code\r
764 SPD3_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 150-175 Manufacturer's Specific Data\r
765 UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use\r
766} SPD_DDR3;\r
767\r
768#pragma pack (pop)\r
769#endif\r
EFI Development Kit II mirror for PVE