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LG		 1/** @file\r
2 This file contains definitions for SPD DDR4.\r
3\r
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13 @par Revision Reference:\r
14 - Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4\r
15 http://www.jedec.org/standards-documents/docs/spd412l-4\r
16**/\r
17\r
18#ifndef _SDRAM_SPD_DDR4_H_\r
19#define _SDRAM_SPD_DDR4_H_\r
20\r
21#pragma pack (push, 1)\r
22\r
23typedef union {\r
24 struct {\r
25 UINT8 BytesUsed : 4; ///< Bits 3:0\r
26 UINT8 BytesTotal : 3; ///< Bits 6:4\r
27 UINT8 CrcCoverage : 1; ///< Bits 7:7\r
28 } Bits;\r
29 UINT8 Data;\r
30} SPD4_DEVICE_DESCRIPTION_STRUCT;\r
31\r
32typedef union {\r
33 struct {\r
34 UINT8 Minor : 4; ///< Bits 3:0\r
35 UINT8 Major : 4; ///< Bits 7:4\r
36 } Bits;\r
37 UINT8 Data;\r
38} SPD4_REVISION_STRUCT;\r
39\r
40typedef union {\r
41 struct {\r
42 UINT8 Type : 8; ///< Bits 7:0\r
43 } Bits;\r
44 UINT8 Data;\r
45} SPD4_DRAM_DEVICE_TYPE_STRUCT;\r
46\r
47typedef union {\r
48 struct {\r
49 UINT8 ModuleType : 4; ///< Bits 3:0\r
50 UINT8 HybridMedia : 3; ///< Bits 6:4\r
51 UINT8 Hybrid : 1; ///< Bits 7:7\r
52 } Bits;\r
53 UINT8 Data;\r
54} SPD4_MODULE_TYPE_STRUCT;\r
55\r
56typedef union {\r
57 struct {\r
58 UINT8 Density : 4; ///< Bits 3:0\r
59 UINT8 BankAddress : 2; ///< Bits 5:4\r
60 UINT8 BankGroup : 2; ///< Bits 7:6\r
61 } Bits;\r
62 UINT8 Data;\r
63} SPD4_SDRAM_DENSITY_BANKS_STRUCT;\r
64\r
65typedef union {\r
66 struct {\r
67 UINT8 ColumnAddress : 3; ///< Bits 2:0\r
68 UINT8 RowAddress : 3; ///< Bits 5:3\r
69 UINT8 Reserved : 2; ///< Bits 7:6\r
70 } Bits;\r
71 UINT8 Data;\r
72} SPD4_SDRAM_ADDRESSING_STRUCT;\r
73\r
74typedef union {\r
75 struct {\r
76 UINT8 SignalLoading : 2; ///< Bits 1:0\r
77 UINT8 Reserved : 2; ///< Bits 3:2\r
78 UINT8 DieCount : 3; ///< Bits 6:4\r
79 UINT8 SdramPackageType : 1; ///< Bits 7:7\r
80 } Bits;\r
81 UINT8 Data;\r
82} SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT;\r
83\r
84typedef union {\r
85 struct {\r
86 UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
87 UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
88 UINT8 Reserved : 2; ///< Bits 7:6\r
89 } Bits;\r
90 UINT8 Data;\r
91} SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
92\r
93typedef union {\r
94 struct {\r
95 UINT8 Reserved : 8; ///< Bits 7:0\r
96 } Bits;\r
97 UINT8 Data;\r
98} SPD4_SDRAM_THERMAL_REFRESH_STRUCT;\r
99\r
100typedef union {\r
101 struct {\r
102 UINT8 Reserved : 5; ///< Bits 4:0\r
103 UINT8 SoftPPR : 1; ///< Bits 5:5\r
104 UINT8 PostPackageRepair : 2; ///< Bits 7:6\r
105 } Bits;\r
106 UINT8 Data;\r
107} SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
108\r
109typedef union {\r
110 struct {\r
111 UINT8 SignalLoading : 2; ///< Bits 1:0\r
112 UINT8 DRAMDensityRatio : 2; ///< Bits 3:2\r
113 UINT8 DieCount : 3; ///< Bits 6:4\r
114 UINT8 SdramPackageType : 1; ///< Bits 7:7\r
115 } Bits;\r
116 UINT8 Data;\r
117} SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT;\r
118\r
119typedef union {\r
120 struct {\r
121 UINT8 OperationAt1_20 : 1; ///< Bits 0:0\r
122 UINT8 EndurantAt1_20 : 1; ///< Bits 1:1\r
123 UINT8 Reserved : 6; ///< Bits 7:2\r
124 } Bits;\r
125 UINT8 Data;\r
126} SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT;\r
127\r
128typedef union {\r
129 struct {\r
130 UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
131 UINT8 RankCount : 3; ///< Bits 5:3\r
132 UINT8 RankMix : 1; ///< Bits 6:6\r
133 UINT8 Reserved : 1; ///< Bits 7:7\r
134 } Bits;\r
135 UINT8 Data;\r
136} SPD4_MODULE_ORGANIZATION_STRUCT;\r
137\r
138typedef union {\r
139 struct {\r
140 UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
141 UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
142 UINT8 Reserved : 3; ///< Bits 7:5\r
143 } Bits;\r
144 UINT8 Data;\r
145} SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r
146\r
147typedef union {\r
148 struct {\r
149 UINT8 Reserved : 7; ///< Bits 6:0\r
150 UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
151 } Bits;\r
152 UINT8 Data;\r
153} SPD4_MODULE_THERMAL_SENSOR_STRUCT;\r
154\r
155typedef union {\r
156 struct {\r
157 UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0\r
158 UINT8 Reserved : 4; ///< Bits 7:4\r
159 } Bits;\r
160 UINT8 Data;\r
161} SPD4_EXTENDED_MODULE_TYPE_STRUCT;\r
162\r
163typedef union {\r
164 struct {\r
165 UINT8 Fine : 2; ///< Bits 1:0\r
166 UINT8 Medium : 2; ///< Bits 3:2\r
167 UINT8 Reserved : 4; ///< Bits 7:4\r
168 } Bits;\r
169 UINT8 Data;\r
170} SPD4_TIMEBASE_STRUCT;\r
171\r
172typedef union {\r
173 struct {\r
174 UINT8 tCKmin : 8; ///< Bits 7:0\r
175 } Bits;\r
176 UINT8 Data;\r
177} SPD4_TCK_MIN_MTB_STRUCT;\r
178\r
179typedef union {\r
180 struct {\r
181 UINT8 tCKmax : 8; ///< Bits 7:0\r
182 } Bits;\r
183 UINT8 Data;\r
184} SPD4_TCK_MAX_MTB_STRUCT;\r
185\r
186typedef union {\r
187 struct {\r
188 UINT32 Cl7 : 1; ///< Bits 0:0\r
189 UINT32 Cl8 : 1; ///< Bits 1:1\r
190 UINT32 Cl9 : 1; ///< Bits 2:2\r
191 UINT32 Cl10 : 1; ///< Bits 3:3\r
192 UINT32 Cl11 : 1; ///< Bits 4:4\r
193 UINT32 Cl12 : 1; ///< Bits 5:5\r
194 UINT32 Cl13 : 1; ///< Bits 6:6\r
195 UINT32 Cl14 : 1; ///< Bits 7:7\r
196 UINT32 Cl15 : 1; ///< Bits 8:8\r
197 UINT32 Cl16 : 1; ///< Bits 9:9\r
198 UINT32 Cl17 : 1; ///< Bits 10:10\r
199 UINT32 Cl18 : 1; ///< Bits 11:11\r
200 UINT32 Cl19 : 1; ///< Bits 12:12\r
201 UINT32 Cl20 : 1; ///< Bits 13:13\r
202 UINT32 Cl21 : 1; ///< Bits 14:14\r
203 UINT32 Cl22 : 1; ///< Bits 15:15\r
204 UINT32 Cl23 : 1; ///< Bits 16:16\r
205 UINT32 Cl24 : 1; ///< Bits 17:17\r
206 UINT32 Cl25 : 1; ///< Bits 18:18\r
207 UINT32 Cl26 : 1; ///< Bits 19:19\r
208 UINT32 Cl27 : 1; ///< Bits 20:20\r
209 UINT32 Cl28 : 1; ///< Bits 21:21\r
210 UINT32 Cl29 : 1; ///< Bits 22:22\r
211 UINT32 Cl30 : 1; ///< Bits 23:23\r
212 UINT32 Cl31 : 1; ///< Bits 24:24\r
213 UINT32 Cl32 : 1; ///< Bits 25:25\r
214 UINT32 Cl33 : 1; ///< Bits 26:26\r
215 UINT32 Cl34 : 1; ///< Bits 27:27\r
216 UINT32 Cl35 : 1; ///< Bits 28:28\r
217 UINT32 Cl36 : 1; ///< Bits 29:29\r
218 UINT32 Reserved : 1; ///< Bits 30:30\r
219 UINT32 ClRange : 1; ///< Bits 31:31\r
220 } Bits;\r
221 struct {\r
222 UINT32 Cl23 : 1; ///< Bits 0:0\r
223 UINT32 Cl24 : 1; ///< Bits 1:1\r
224 UINT32 Cl25 : 1; ///< Bits 2:2\r
225 UINT32 Cl26 : 1; ///< Bits 3:3\r
226 UINT32 Cl27 : 1; ///< Bits 4:4\r
227 UINT32 Cl28 : 1; ///< Bits 5:5\r
228 UINT32 Cl29 : 1; ///< Bits 6:6\r
229 UINT32 Cl30 : 1; ///< Bits 7:7\r
230 UINT32 Cl31 : 1; ///< Bits 8:8\r
231 UINT32 Cl32 : 1; ///< Bits 9:9\r
232 UINT32 Cl33 : 1; ///< Bits 10:10\r
233 UINT32 Cl34 : 1; ///< Bits 11:11\r
234 UINT32 Cl35 : 1; ///< Bits 12:12\r
235 UINT32 Cl36 : 1; ///< Bits 13:13\r
236 UINT32 Cl37 : 1; ///< Bits 14:14\r
237 UINT32 Cl38 : 1; ///< Bits 15:15\r
238 UINT32 Cl39 : 1; ///< Bits 16:16\r
239 UINT32 Cl40 : 1; ///< Bits 17:17\r
240 UINT32 Cl41 : 1; ///< Bits 18:18\r
241 UINT32 Cl42 : 1; ///< Bits 19:19\r
242 UINT32 Cl43 : 1; ///< Bits 20:20\r
243 UINT32 Cl44 : 1; ///< Bits 21:21\r
244 UINT32 Cl45 : 1; ///< Bits 22:22\r
245 UINT32 Cl46 : 1; ///< Bits 23:23\r
246 UINT32 Cl47 : 1; ///< Bits 24:24\r
247 UINT32 Cl48 : 1; ///< Bits 25:25\r
248 UINT32 Cl49 : 1; ///< Bits 26:26\r
249 UINT32 Cl50 : 1; ///< Bits 27:27\r
250 UINT32 Cl51 : 1; ///< Bits 28:28\r
251 UINT32 Cl52 : 1; ///< Bits 29:29\r
252 UINT32 Reserved : 1; ///< Bits 30:30\r
253 UINT32 ClRange : 1; ///< Bits 31:31\r
254 } HighRangeBits;\r
255 UINT32 Data;\r
256 UINT16 Data16[2];\r
257 UINT8 Data8[4];\r
258} SPD4_CAS_LATENCIES_SUPPORTED_STRUCT;\r
259\r
260typedef union {\r
261 struct {\r
262 UINT8 tAAmin : 8; ///< Bits 7:0\r
263 } Bits;\r
264 UINT8 Data;\r
265} SPD4_TAA_MIN_MTB_STRUCT;\r
266\r
267typedef union {\r
268 struct {\r
269 UINT8 tRCDmin : 8; ///< Bits 7:0\r
270 } Bits;\r
271 UINT8 Data;\r
272} SPD4_TRCD_MIN_MTB_STRUCT;\r
273\r
274typedef union {\r
275 struct {\r
276 UINT8 tRPmin : 8; ///< Bits 7:0\r
277 } Bits;\r
278 UINT8 Data;\r
279} SPD4_TRP_MIN_MTB_STRUCT;\r
280\r
281typedef union {\r
282 struct {\r
283 UINT8 tRASminUpper : 4; ///< Bits 3:0\r
284 UINT8 tRCminUpper : 4; ///< Bits 7:4\r
285 } Bits;\r
286 UINT8 Data;\r
287} SPD4_TRAS_TRC_MIN_MTB_STRUCT;\r
288\r
289typedef union {\r
290 struct {\r
291 UINT8 tRASmin : 8; ///< Bits 7:0\r
292 } Bits;\r
293 UINT8 Data;\r
294} SPD4_TRAS_MIN_MTB_STRUCT;\r
295\r
296typedef union {\r
297 struct {\r
298 UINT8 tRCmin : 8; ///< Bits 7:0\r
299 } Bits;\r
300 UINT8 Data;\r
301} SPD4_TRC_MIN_MTB_STRUCT;\r
302\r
303typedef union {\r
304 struct {\r
305 UINT16 tRFCmin : 16; ///< Bits 15:0\r
306 } Bits;\r
307 UINT16 Data;\r
308 UINT8 Data8[2];\r
309} SPD4_TRFC_MIN_MTB_STRUCT;\r
310\r
311typedef union {\r
312 struct {\r
313 UINT8 tFAWminUpper : 4; ///< Bits 3:0\r
314 UINT8 Reserved : 4; ///< Bits 7:4\r
315 } Bits;\r
316 UINT8 Data;\r
317} SPD4_TFAW_MIN_MTB_UPPER_STRUCT;\r
318\r
319typedef union {\r
320 struct {\r
321 UINT8 tFAWmin : 8; ///< Bits 7:0\r
322 } Bits;\r
323 UINT8 Data;\r
324} SPD4_TFAW_MIN_MTB_STRUCT;\r
325\r
326typedef union {\r
327 struct {\r
328 UINT8 tRRDmin : 8; ///< Bits 7:0\r
329 } Bits;\r
330 UINT8 Data;\r
331} SPD4_TRRD_MIN_MTB_STRUCT;\r
332\r
333typedef union {\r
334 struct {\r
335 UINT8 tCCDmin : 8; ///< Bits 7:0\r
336 } Bits;\r
337 UINT8 Data;\r
338} SPD4_TCCD_MIN_MTB_STRUCT;\r
339\r
340typedef union {\r
341 struct {\r
342 UINT8 tWRminMostSignificantNibble : 4; ///< Bits 3:0\r
343 UINT8 Reserved : 4; ///< Bits 7:4\r
344 } Bits;\r
345 UINT8 Data;\r
346} SPD4_TWR_UPPER_NIBBLE_STRUCT;\r
347\r
348typedef union {\r
349 struct {\r
350 UINT8 tWRmin : 8; ///< Bits 7:0\r
351 } Bits;\r
352 UINT8 Data;\r
353} SPD4_TWR_MIN_MTB_STRUCT;\r
354\r
355typedef union {\r
356 struct {\r
357 UINT8 tWTR_SminMostSignificantNibble : 4; ///< Bits 3:0\r
358 UINT8 tWTR_LminMostSignificantNibble : 4; ///< Bits 7:4\r
359 } Bits;\r
360 UINT8 Data;\r
361} SPD4_TWTR_UPPER_NIBBLE_STRUCT;\r
362\r
363typedef union {\r
364 struct {\r
365 UINT8 tWTRmin : 8; ///< Bits 7:0\r
366 } Bits;\r
367 UINT8 Data;\r
368} SPD4_TWTR_MIN_MTB_STRUCT;\r
369\r
370typedef union {\r
371 struct {\r
372 UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0\r
373 UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5\r
374 UINT8 PackageRankMap : 2; ///< Bits 7:6\r
375 } Bits;\r
376 UINT8 Data;\r
377} SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;\r
378\r
379typedef union {\r
380 struct {\r
381 INT8 tCCDminFine : 8; ///< Bits 7:0\r
382 } Bits;\r
383 INT8 Data;\r
384} SPD4_TCCD_MIN_FTB_STRUCT;\r
385\r
386typedef union {\r
387 struct {\r
388 INT8 tRRDminFine : 8; ///< Bits 7:0\r
389 } Bits;\r
390 INT8 Data;\r
391} SPD4_TRRD_MIN_FTB_STRUCT;\r
392\r
393typedef union {\r
394 struct {\r
395 INT8 tRCminFine : 8; ///< Bits 7:0\r
396 } Bits;\r
397 INT8 Data;\r
398} SPD4_TRC_MIN_FTB_STRUCT;\r
399\r
400typedef union {\r
401 struct {\r
402 INT8 tRPminFine : 8; ///< Bits 7:0\r
403 } Bits;\r
404 INT8 Data;\r
405} SPD4_TRP_MIN_FTB_STRUCT;\r
406\r
407typedef union {\r
408 struct {\r
409 INT8 tRCDminFine : 8; ///< Bits 7:0\r
410 } Bits;\r
411 INT8 Data;\r
412} SPD4_TRCD_MIN_FTB_STRUCT;\r
413\r
414typedef union {\r
415 struct {\r
416 INT8 tAAminFine : 8; ///< Bits 7:0\r
417 } Bits;\r
418 INT8 Data;\r
419} SPD4_TAA_MIN_FTB_STRUCT;\r
420\r
421typedef union {\r
422 struct {\r
423 INT8 tCKmaxFine : 8; ///< Bits 7:0\r
424 } Bits;\r
425 INT8 Data;\r
426} SPD4_TCK_MAX_FTB_STRUCT;\r
427\r
428typedef union {\r
429 struct {\r
430 INT8 tCKminFine : 8; ///< Bits 7:0\r
431 } Bits;\r
432 INT8 Data;\r
433} SPD4_TCK_MIN_FTB_STRUCT;\r
434\r
435typedef union {\r
436 struct {\r
437 UINT8 Height : 5; ///< Bits 4:0\r
438 UINT8 RawCardExtension : 3; ///< Bits 7:5\r
439 } Bits;\r
440 UINT8 Data;\r
441} SPD4_UNBUF_MODULE_NOMINAL_HEIGHT;\r
442\r
443typedef union {\r
444 struct {\r
445 UINT8 FrontThickness : 4; ///< Bits 3:0\r
446 UINT8 BackThickness : 4; ///< Bits 7:4\r
447 } Bits;\r
448 UINT8 Data;\r
449} SPD4_UNBUF_MODULE_NOMINAL_THICKNESS;\r
450\r
451typedef union {\r
452 struct {\r
453 UINT8 Card : 5; ///< Bits 4:0\r
454 UINT8 Revision : 2; ///< Bits 6:5\r
455 UINT8 Extension : 1; ///< Bits 7:7\r
456 } Bits;\r
457 UINT8 Data;\r
458} SPD4_UNBUF_REFERENCE_RAW_CARD;\r
459\r
460typedef union {\r
461 struct {\r
462 UINT8 MappingRank1 : 1; ///< Bits 0:0\r
463 UINT8 Reserved : 7; ///< Bits 7:1\r
464 } Bits;\r
465 UINT8 Data;\r
466} SPD4_UNBUF_ADDRESS_MAPPING;\r
467\r
468typedef union {\r
469 struct {\r
470 UINT8 Height : 5; ///< Bits 4:0\r
471 UINT8 Reserved : 3; ///< Bits 7:5\r
472 } Bits;\r
473 UINT8 Data;\r
474} SPD4_RDIMM_MODULE_NOMINAL_HEIGHT;\r
475\r
476typedef union {\r
477 struct {\r
478 UINT8 FrontThickness : 4; ///< Bits 3:0\r
479 UINT8 BackThickness : 4; ///< Bits 7:4\r
480 } Bits;\r
481 UINT8 Data;\r
482} SPD4_RDIMM_MODULE_NOMINAL_THICKNESS;\r
483\r
484typedef union {\r
485 struct {\r
486 UINT8 Card : 5; ///< Bits 4:0\r
487 UINT8 Revision : 2; ///< Bits 6:5\r
488 UINT8 Extension : 1; ///< Bits 7:7\r
489 } Bits;\r
490 UINT8 Data;\r
491} SPD4_RDIMM_REFERENCE_RAW_CARD;\r
492\r
493typedef union {\r
494 struct {\r
495 UINT8 RegisterCount : 2; ///< Bits 1:0\r
496 UINT8 DramRowCount : 2; ///< Bits 3:2\r
497 UINT8 RegisterType : 4; ///< Bits 7:4\r
498 } Bits;\r
499 UINT8 Data;\r
500} SPD4_RDIMM_MODULE_ATTRIBUTES;\r
501\r
502typedef union {\r
503 struct {\r
504 UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
505 UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
506 } Bits;\r
507 UINT8 Data;\r
508} SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r
509\r
510typedef union {\r
511 struct {\r
512 UINT16 ContinuationCount : 7; ///< Bits 6:0\r
513 UINT16 ContinuationParity : 1; ///< Bits 7:7\r
514 UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
515 } Bits;\r
516 UINT16 Data;\r
517 UINT8 Data8[2];\r
518} SPD4_MANUFACTURER_ID_CODE;\r
519\r
520typedef union {\r
521 struct {\r
522 UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
523 } Bits;\r
524 UINT8 Data;\r
525} SPD4_RDIMM_REGISTER_REVISION_NUMBER;\r
526\r
527typedef union {\r
528 struct {\r
529 UINT8 Rank1Mapping : 1; ///< Bits 0:0\r
530 UINT8 Reserved : 7; ///< Bits 7:1\r
531 } Bits;\r
532 UINT8 Data;\r
533} SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;\r
534\r
535typedef union {\r
536 struct {\r
537 UINT8 Cke : 2; ///< Bits 1:0\r
538 UINT8 Odt : 2; ///< Bits 3:2\r
539 UINT8 CommandAddress : 2; ///< Bits 5:4\r
540 UINT8 ChipSelect : 2; ///< Bits 7:6\r
541 } Bits;\r
542 UINT8 Data;\r
543} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;\r
544\r
545typedef union {\r
546 struct {\r
547 UINT8 Y0Y2 : 2; ///< Bits 1:0\r
548 UINT8 Y1Y3 : 2; ///< Bits 3:2\r
549 UINT8 Reserved0 : 2; ///< Bits 5:4\r
550 UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6\r
551 UINT8 Reserved1 : 1; ///< Bits 7:7\r
552 } Bits;\r
553 UINT8 Data;\r
554} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;\r
555\r
556typedef union {\r
557 struct {\r
558 UINT8 Height : 5; ///< Bits 4:0\r
559 UINT8 Reserved : 3; ///< Bits 7:5\r
560 } Bits;\r
561 UINT8 Data;\r
562} SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT;\r
563\r
564typedef union {\r
565 struct {\r
566 UINT8 FrontThickness : 4; ///< Bits 3:0\r
567 UINT8 BackThickness : 4; ///< Bits 7:4\r
568 } Bits;\r
569 UINT8 Data;\r
570} SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS;\r
571\r
572typedef union {\r
573 struct {\r
574 UINT8 Card : 5; ///< Bits 4:0\r
575 UINT8 Revision : 2; ///< Bits 6:5\r
576 UINT8 Extension : 1; ///< Bits 7:7\r
577 } Bits;\r
578 UINT8 Data;\r
579} SPD4_LRDIMM_REFERENCE_RAW_CARD;\r
580\r
581typedef union {\r
582 struct {\r
583 UINT8 RegisterCount : 2; ///< Bits 1:0\r
584 UINT8 DramRowCount : 2; ///< Bits 3:2\r
585 UINT8 RegisterType : 4; ///< Bits 7:4\r
586 } Bits;\r
587 UINT8 Data;\r
588} SPD4_LRDIMM_MODULE_ATTRIBUTES;\r
589\r
590typedef union {\r
591 struct {\r
592 UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
593 UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
594 } Bits;\r
595 UINT8 Data;\r
596} SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r
597\r
598typedef union {\r
599 struct {\r
600 UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
601 } Bits;\r
602 UINT8 Data;\r
603} SPD4_LRDIMM_REGISTER_REVISION_NUMBER;\r
604\r
605typedef union {\r
606 struct {\r
607 UINT8 Rank1Mapping : 1; ///< Bits 0:0\r
608 UINT8 Reserved : 7; ///< Bits 7:1\r
609 } Bits;\r
610 UINT8 Data;\r
611} SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;\r
612\r
613typedef union {\r
614 struct {\r
615 UINT8 Cke : 2; ///< Bits 1:0\r
616 UINT8 Odt : 2; ///< Bits 3:2\r
617 UINT8 CommandAddress : 2; ///< Bits 5:4\r
618 UINT8 ChipSelect : 2; ///< Bits 7:6\r
619 } Bits;\r
620 UINT8 Data;\r
621} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;\r
622\r
623typedef union {\r
624 struct {\r
625 UINT8 Y0Y2 : 2; ///< Bits 1:0\r
626 UINT8 Y1Y3 : 2; ///< Bits 3:2\r
627 UINT8 Reserved0 : 2; ///< Bits 5:4\r
628 UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6\r
629 UINT8 Reserved1 : 1; ///< Bits 7:7\r
630 } Bits;\r
631 UINT8 Data;\r
632} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;\r
633\r
634typedef struct {\r
635 UINT8 DataBufferRevisionNumber;\r
636} SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER;\r
637\r
638typedef union {\r
639 struct {\r
640 UINT8 DramVrefDQForPackageRank0 : 6; ///< Bits 5:0\r
641 UINT8 Reserved : 2; ///< Bits 7:6\r
642 } Bits;\r
643 UINT8 Data;\r
644} SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK;\r
645\r
646typedef struct {\r
647 UINT8 DataBufferVrefDQforDramInterface;\r
648} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE;\r
649\r
650typedef union {\r
651 struct {\r
652 UINT8 DramInterfaceMdqDriveStrength : 4; ///< Bits 3:0\r
653 UINT8 DramInterfaceMdqReadTerminationStrength : 4; ///< Bits 7:4\r
654 } Bits;\r
655 UINT8 Data;\r
656} SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE;\r
657\r
658typedef union {\r
659 struct {\r
660 UINT8 DataRateLe1866 : 2; ///< Bits 1:0\r
661 UINT8 DataRateLe2400 : 2; ///< Bits 3:2\r
662 UINT8 DataRateLe3200 : 2; ///< Bits 5:4\r
663 UINT8 Reserved : 2; ///< Bits 7:6\r
664 } Bits;\r
665 UINT8 Data;\r
666} SPD4_LRDIMM_DRAM_DRIVE_STRENGTH;\r
667\r
668typedef union {\r
669 struct {\r
670 UINT8 Rtt_Nom : 3; ///< Bits 2:0\r
671 UINT8 Rtt_WR : 3; ///< Bits 5:3\r
672 UINT8 Reserved : 2; ///< Bits 7:6\r
673 } Bits;\r
674 UINT8 Data;\r
675} SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE;\r
676\r
677typedef union {\r
678 struct {\r
679 UINT8 PackageRanks0_1 : 3; ///< Bits 2:0\r
680 UINT8 PackageRanks2_3 : 3; ///< Bits 5:3\r
681 UINT8 Reserved : 2; ///< Bits 7:6\r
682 } Bits;\r
683 UINT8 Data;\r
684} SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE;\r
685\r
686typedef union {\r
687 struct {\r
688 UINT8 Rank0 : 1; ///< Bits 0:0\r
689 UINT8 Rank1 : 1; ///< Bits 1:1\r
690 UINT8 Rank2 : 1; ///< Bits 2:2\r
691 UINT8 Rank3 : 1; ///< Bits 3:3\r
692 UINT8 DataBuffer : 1; ///< Bits 4:4\r
693 UINT8 Reserved : 3; ///< Bits 7:5\r
694 } Bits;\r
695 UINT8 Data;\r
696} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE;\r
697\r
698typedef union {\r
699 struct {\r
700 UINT8 DataBufferGainAdjustment : 1; ///< Bits 0:0\r
701 UINT8 DataBufferDfe : 1; ///< Bits 1:1\r
702 UINT8 Reserved : 6; ///< Bits 7:2\r
703 } Bits;\r
704 UINT8 Data;\r
705} SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION;\r
706\r
707typedef UINT16 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER;\r
708\r
709typedef union {\r
710 struct {\r
711 UINT16 ContinuationCount : 7; ///< Bits 6:0\r
712 UINT16 ContinuationParity : 1; ///< Bits 7:7\r
713 UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
714 } Bits;\r
715 UINT16 Data;\r
716 UINT8 Data8[2];\r
717} SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE;\r
718\r
719typedef UINT16 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER;\r
720\r
721typedef UINT8 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE;\r
722\r
723typedef union {\r
724 struct {\r
725 UINT8 Card : 5; ///< Bits 4:0\r
726 UINT8 Revision : 2; ///< Bits 6:5\r
727 UINT8 Extension : 1; ///< Bits 7:7\r
728 } Bits;\r
729 UINT8 Data;\r
730} SPD4_NVDIMM_REFERENCE_RAW_CARD;\r
731\r
732typedef union {\r
733 struct {\r
734 UINT8 Reserved : 4; ///< Bits 3:0\r
735 UINT8 Extension : 4; ///< Bits 7:4\r
736 } Bits;\r
737 UINT8 Data;\r
738} SPD4_NVDIMM_MODULE_CHARACTERISTICS;\r
739\r
740typedef struct {\r
741 UINT8 Reserved;\r
742 UINT8 MediaType;\r
743} SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES;\r
744\r
745typedef UINT8 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME;\r
746\r
747typedef union {\r
748 struct {\r
749 UINT16 FunctionInterface : 5; ///< Bits 4:0\r
750 UINT16 FunctionClass : 5; ///< Bits 9:5\r
751 UINT16 BlockOffset : 4; ///< Bits 13:10\r
752 UINT16 Reserved : 1; ///< Bits 14:14\r
753 UINT16 Implemented : 1; ///< Bits 15:15\r
754 } Bits;\r
755 UINT16 Data;\r
756 UINT8 Data8[2];\r
757} SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR;\r
758\r
759typedef struct {\r
760 UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
761 UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
762} SPD4_MANUFACTURING_DATE;\r
763\r
764typedef union {\r
765 UINT32 Data;\r
766 UINT16 SerialNumber16[2];\r
767 UINT8 SerialNumber8[4];\r
768} SPD4_MANUFACTURER_SERIAL_NUMBER;\r
769\r
770typedef struct {\r
771 UINT8 Location; ///< Module Manufacturing Location\r
772} SPD4_MANUFACTURING_LOCATION;\r
773\r
774typedef struct {\r
775 SPD4_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
776 SPD4_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
777 SPD4_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
778 SPD4_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
779} SPD4_UNIQUE_MODULE_ID;\r
780\r
781typedef union {\r
782 UINT16 Crc[1];\r
783 UINT8 Data8[2];\r
784} SPD4_CYCLIC_REDUNDANCY_CODE;\r
785\r
786typedef struct {\r
787 SPD4_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
788 SPD4_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
789 SPD4_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
790 SPD4_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
791 SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
792 SPD4_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
793 SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT PrimarySdramPackageType; ///< 6 Primary SDRAM Package Type\r
794 SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features\r
795 SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options\r
796 SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features\r
797 SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramPackageType;///< 10 Secondary SDRAM Package Type\r
798 SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD\r
799 SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization\r
800 SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width\r
801 SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor\r
802 SPD4_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type\r
803 UINT8 Reserved0; ///< 16 Reserved\r
804 SPD4_TIMEBASE_STRUCT Timebase; ///< 17 Timebases\r
805 SPD4_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)\r
806 SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)\r
807 SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported\r
808 SPD4_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)\r
809 SPD4_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
810 SPD4_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin)\r
811 SPD4_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC\r
812 SPD4_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r
813 SPD4_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r
814 SPD4_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min)\r
815 SPD4_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min)\r
816 SPD4_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min)\r
817 SPD4_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW\r
818 SPD4_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin)\r
819 SPD4_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group\r
820 SPD4_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group\r
821 SPD4_TCCD_MIN_MTB_STRUCT tCCD_Lmin; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group\r
822 SPD4_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble; ///< 41 Upper Nibble for tWRmin\r
823 SPD4_TWR_MIN_MTB_STRUCT tWRmin; ///< 42 Minimum Write Recovery Time (tWRmin)\r
824 SPD4_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble; ///< 43 Upper Nibbles for tWTRmin\r
825 SPD4_TWTR_MIN_MTB_STRUCT tWTR_Smin; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group\r
826 SPD4_TWTR_MIN_MTB_STRUCT tWTR_Lmin; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group\r
827 UINT8 Reserved1[59 - 46 + 1]; ///< 46-59 Reserved\r
828 SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping\r
829 UINT8 Reserved2[116 - 78 + 1]; ///< 78-116 Reserved\r
830 SPD4_TCCD_MIN_FTB_STRUCT tCCD_LminFine; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group\r
831 SPD4_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group\r
832 SPD4_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group\r
833 SPD4_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r
834 SPD4_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin)\r
835 SPD4_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
836 SPD4_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
837 SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)\r
838 SPD4_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin)\r
839 SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
840} SPD4_BASE_SECTION;\r
841\r
842typedef struct {\r
843 SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
844 SPD4_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
845 SPD4_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
846 SPD4_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM\r
847 UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved\r
848 SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
849} SPD4_MODULE_UNBUFFERED;\r
850\r
851typedef struct {\r
852 SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
853 SPD4_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
854 SPD4_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
855 SPD4_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes\r
856 SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution\r
857 SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code\r
858 SPD4_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number\r
859 SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM; ///< 136 Address Mapping from Register to DRAM\r
860 SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address\r
861 SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock\r
862 UINT8 Reserved[253 - 139 + 1]; ///< 253-139 Reserved\r
863 SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
864} SPD4_MODULE_REGISTERED;\r
865\r
866typedef struct {\r
867 SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
868 SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
869 SPD4_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
870 SPD4_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes\r
871 SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution\r
872 SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code\r
873 SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number\r
874 SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDram; ///< 136 Address Mapping from Register to DRAM\r
875 SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address\r
876 SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock\r
877 SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber; ///< 139 Data Buffer Revision Number\r
878 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank0; ///< 140 DRAM VrefDQ for Package Rank 0\r
879 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank1; ///< 141 DRAM VrefDQ for Package Rank 1\r
880 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank2; ///< 142 DRAM VrefDQ for Package Rank 2\r
881 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank3; ///< 143 DRAM VrefDQ for Package Rank 3\r
882 SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQForDramInterface; ///< 144 Data Buffer VrefDQ for DRAM Interface\r
883 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe1866; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866\r
884 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe2400; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400\r
885 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe3200; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200\r
886 SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DramDriveStrength; ///< 148 DRAM Drive Strength\r
887 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe1866; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866\r
888 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe2400; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400\r
889 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe3200; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200\r
890 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe1866; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866\r
891 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe2400; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400\r
892 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe3200; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200\r
893 SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQForDramInterfaceRange; ///< 155 Data Buffer VrefDQ for DRAM Interface Range\r
894 SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDqDecisionFeedbackEqualization; ///< 156 Data Buffer DQ Decision Feedback Equalization\r
895 UINT8 Reserved[253 - 157 + 1]; ///< 253-132 Reserved\r
896 SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
897} SPD4_MODULE_LOADREDUCED;\r
898\r
899typedef struct {\r
900 UINT8 Reserved0[191 - 128 + 1]; ///< 128-191 Reserved\r
901 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier; ///< 192-193 Module Product Identifier\r
902 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIdCode; ///< 194-195 Subsystem Controller Manufacturer's ID Code\r
903 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier; ///< 196-197 Subsystem Controller Identifier\r
904 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode; ///< 198 Subsystem Controller Revision Code\r
905 SPD4_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 199 Reference Raw Card Used\r
906 SPD4_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics; ///< 200 Module Characteristics\r
907 SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes; ///< 201-202 Hybrid Module Media Types\r
908 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime; ///< 203 Maximum Non-Volatile Memory Initialization Time\r
909 SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors[8]; ///< 204-219 Function Interface Descriptors\r
910 UINT8 Reserved[253 - 220 + 1]; ///< 220-253 Reserved\r
911 SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
912} SPD4_MODULE_NVDIMM;\r
913\r
914typedef union {\r
915 SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r
916 SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r
917 SPD4_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r
918 SPD4_MODULE_NVDIMM NonVolatile; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters\r
919} SPD4_MODULE_SPECIFIC;\r
920\r
921typedef struct {\r
922 UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number\r
923} SPD4_MODULE_PART_NUMBER;\r
924\r
925typedef struct {\r
926 UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data\r
927} SPD4_MANUFACTURER_SPECIFIC;\r
928\r
929typedef UINT8 SPD4_MODULE_REVISION_CODE;///< 349 Module Revision Code\r
930typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping\r
931\r
932typedef struct {\r
933 SPD4_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID\r
934 SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number\r
935 SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code\r
936 SPD4_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code\r
937 SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping\r
938 SPD4_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data\r
939 UINT8 Reserved[2]; ///< 382-383 Reserved\r
940} SPD4_MANUFACTURING_DATA;\r
941\r
942typedef struct {\r
943 UINT8 Reserved[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types\r
944} SPD4_END_USER_SECTION;\r
945\r
946///\r
947/// DDR4 Serial Presence Detect structure\r
948///\r
949typedef struct {\r
950 SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters\r
951 SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section\r
952 UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Reserved\r
953 SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information\r
954 SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable\r
955} SPD_DDR4;\r
956\r
957#pragma pack (pop)\r
958#endif\r
EFI Development Kit II mirror for PVE