Commit | Line | Data |
---|---|---|
6a82ceb6 LG |
1 | /** @file\r |
2 | This file contains definitions for SPD DDR4.\r | |
3 | \r | |
4 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
9344f092 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
6a82ceb6 LG |
6 | \r |
7 | @par Revision Reference:\r | |
8 | - Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4\r | |
9 | http://www.jedec.org/standards-documents/docs/spd412l-4\r | |
10 | **/\r | |
11 | \r | |
12 | #ifndef _SDRAM_SPD_DDR4_H_\r | |
13 | #define _SDRAM_SPD_DDR4_H_\r | |
14 | \r | |
15 | #pragma pack (push, 1)\r | |
16 | \r | |
17 | typedef union {\r | |
18 | struct {\r | |
19 | UINT8 BytesUsed : 4; ///< Bits 3:0\r | |
20 | UINT8 BytesTotal : 3; ///< Bits 6:4\r | |
21 | UINT8 CrcCoverage : 1; ///< Bits 7:7\r | |
22 | } Bits;\r | |
23 | UINT8 Data;\r | |
24 | } SPD4_DEVICE_DESCRIPTION_STRUCT;\r | |
25 | \r | |
26 | typedef union {\r | |
27 | struct {\r | |
28 | UINT8 Minor : 4; ///< Bits 3:0\r | |
29 | UINT8 Major : 4; ///< Bits 7:4\r | |
30 | } Bits;\r | |
31 | UINT8 Data;\r | |
32 | } SPD4_REVISION_STRUCT;\r | |
33 | \r | |
34 | typedef union {\r | |
35 | struct {\r | |
36 | UINT8 Type : 8; ///< Bits 7:0\r | |
37 | } Bits;\r | |
38 | UINT8 Data;\r | |
39 | } SPD4_DRAM_DEVICE_TYPE_STRUCT;\r | |
40 | \r | |
41 | typedef union {\r | |
42 | struct {\r | |
43 | UINT8 ModuleType : 4; ///< Bits 3:0\r | |
44 | UINT8 HybridMedia : 3; ///< Bits 6:4\r | |
45 | UINT8 Hybrid : 1; ///< Bits 7:7\r | |
46 | } Bits;\r | |
47 | UINT8 Data;\r | |
48 | } SPD4_MODULE_TYPE_STRUCT;\r | |
49 | \r | |
50 | typedef union {\r | |
51 | struct {\r | |
52 | UINT8 Density : 4; ///< Bits 3:0\r | |
53 | UINT8 BankAddress : 2; ///< Bits 5:4\r | |
54 | UINT8 BankGroup : 2; ///< Bits 7:6\r | |
55 | } Bits;\r | |
56 | UINT8 Data;\r | |
57 | } SPD4_SDRAM_DENSITY_BANKS_STRUCT;\r | |
58 | \r | |
59 | typedef union {\r | |
60 | struct {\r | |
61 | UINT8 ColumnAddress : 3; ///< Bits 2:0\r | |
62 | UINT8 RowAddress : 3; ///< Bits 5:3\r | |
63 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
64 | } Bits;\r | |
65 | UINT8 Data;\r | |
66 | } SPD4_SDRAM_ADDRESSING_STRUCT;\r | |
67 | \r | |
68 | typedef union {\r | |
69 | struct {\r | |
70 | UINT8 SignalLoading : 2; ///< Bits 1:0\r | |
71 | UINT8 Reserved : 2; ///< Bits 3:2\r | |
72 | UINT8 DieCount : 3; ///< Bits 6:4\r | |
73 | UINT8 SdramPackageType : 1; ///< Bits 7:7\r | |
74 | } Bits;\r | |
75 | UINT8 Data;\r | |
76 | } SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT;\r | |
77 | \r | |
78 | typedef union {\r | |
79 | struct {\r | |
80 | UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r | |
81 | UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r | |
82 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
83 | } Bits;\r | |
84 | UINT8 Data;\r | |
85 | } SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT;\r | |
86 | \r | |
87 | typedef union {\r | |
88 | struct {\r | |
89 | UINT8 Reserved : 8; ///< Bits 7:0\r | |
90 | } Bits;\r | |
91 | UINT8 Data;\r | |
92 | } SPD4_SDRAM_THERMAL_REFRESH_STRUCT;\r | |
93 | \r | |
94 | typedef union {\r | |
95 | struct {\r | |
96 | UINT8 Reserved : 5; ///< Bits 4:0\r | |
97 | UINT8 SoftPPR : 1; ///< Bits 5:5\r | |
98 | UINT8 PostPackageRepair : 2; ///< Bits 7:6\r | |
99 | } Bits;\r | |
100 | UINT8 Data;\r | |
101 | } SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;\r | |
102 | \r | |
103 | typedef union {\r | |
104 | struct {\r | |
105 | UINT8 SignalLoading : 2; ///< Bits 1:0\r | |
106 | UINT8 DRAMDensityRatio : 2; ///< Bits 3:2\r | |
107 | UINT8 DieCount : 3; ///< Bits 6:4\r | |
108 | UINT8 SdramPackageType : 1; ///< Bits 7:7\r | |
109 | } Bits;\r | |
110 | UINT8 Data;\r | |
111 | } SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT;\r | |
112 | \r | |
113 | typedef union {\r | |
114 | struct {\r | |
115 | UINT8 OperationAt1_20 : 1; ///< Bits 0:0\r | |
116 | UINT8 EndurantAt1_20 : 1; ///< Bits 1:1\r | |
117 | UINT8 Reserved : 6; ///< Bits 7:2\r | |
118 | } Bits;\r | |
119 | UINT8 Data;\r | |
120 | } SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT;\r | |
121 | \r | |
122 | typedef union {\r | |
123 | struct {\r | |
124 | UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r | |
125 | UINT8 RankCount : 3; ///< Bits 5:3\r | |
126 | UINT8 RankMix : 1; ///< Bits 6:6\r | |
127 | UINT8 Reserved : 1; ///< Bits 7:7\r | |
128 | } Bits;\r | |
129 | UINT8 Data;\r | |
130 | } SPD4_MODULE_ORGANIZATION_STRUCT;\r | |
131 | \r | |
132 | typedef union {\r | |
133 | struct {\r | |
134 | UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r | |
135 | UINT8 BusWidthExtension : 2; ///< Bits 4:3\r | |
136 | UINT8 Reserved : 3; ///< Bits 7:5\r | |
137 | } Bits;\r | |
138 | UINT8 Data;\r | |
139 | } SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r | |
140 | \r | |
141 | typedef union {\r | |
142 | struct {\r | |
143 | UINT8 Reserved : 7; ///< Bits 6:0\r | |
144 | UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r | |
145 | } Bits;\r | |
146 | UINT8 Data;\r | |
147 | } SPD4_MODULE_THERMAL_SENSOR_STRUCT;\r | |
148 | \r | |
149 | typedef union {\r | |
150 | struct {\r | |
151 | UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0\r | |
152 | UINT8 Reserved : 4; ///< Bits 7:4\r | |
153 | } Bits;\r | |
154 | UINT8 Data;\r | |
155 | } SPD4_EXTENDED_MODULE_TYPE_STRUCT;\r | |
156 | \r | |
157 | typedef union {\r | |
158 | struct {\r | |
159 | UINT8 Fine : 2; ///< Bits 1:0\r | |
160 | UINT8 Medium : 2; ///< Bits 3:2\r | |
161 | UINT8 Reserved : 4; ///< Bits 7:4\r | |
162 | } Bits;\r | |
163 | UINT8 Data;\r | |
164 | } SPD4_TIMEBASE_STRUCT;\r | |
165 | \r | |
166 | typedef union {\r | |
167 | struct {\r | |
168 | UINT8 tCKmin : 8; ///< Bits 7:0\r | |
169 | } Bits;\r | |
170 | UINT8 Data;\r | |
171 | } SPD4_TCK_MIN_MTB_STRUCT;\r | |
172 | \r | |
173 | typedef union {\r | |
174 | struct {\r | |
175 | UINT8 tCKmax : 8; ///< Bits 7:0\r | |
176 | } Bits;\r | |
177 | UINT8 Data;\r | |
178 | } SPD4_TCK_MAX_MTB_STRUCT;\r | |
179 | \r | |
180 | typedef union {\r | |
181 | struct {\r | |
182 | UINT32 Cl7 : 1; ///< Bits 0:0\r | |
183 | UINT32 Cl8 : 1; ///< Bits 1:1\r | |
184 | UINT32 Cl9 : 1; ///< Bits 2:2\r | |
185 | UINT32 Cl10 : 1; ///< Bits 3:3\r | |
186 | UINT32 Cl11 : 1; ///< Bits 4:4\r | |
187 | UINT32 Cl12 : 1; ///< Bits 5:5\r | |
188 | UINT32 Cl13 : 1; ///< Bits 6:6\r | |
189 | UINT32 Cl14 : 1; ///< Bits 7:7\r | |
190 | UINT32 Cl15 : 1; ///< Bits 8:8\r | |
191 | UINT32 Cl16 : 1; ///< Bits 9:9\r | |
192 | UINT32 Cl17 : 1; ///< Bits 10:10\r | |
193 | UINT32 Cl18 : 1; ///< Bits 11:11\r | |
194 | UINT32 Cl19 : 1; ///< Bits 12:12\r | |
195 | UINT32 Cl20 : 1; ///< Bits 13:13\r | |
196 | UINT32 Cl21 : 1; ///< Bits 14:14\r | |
197 | UINT32 Cl22 : 1; ///< Bits 15:15\r | |
198 | UINT32 Cl23 : 1; ///< Bits 16:16\r | |
199 | UINT32 Cl24 : 1; ///< Bits 17:17\r | |
200 | UINT32 Cl25 : 1; ///< Bits 18:18\r | |
201 | UINT32 Cl26 : 1; ///< Bits 19:19\r | |
202 | UINT32 Cl27 : 1; ///< Bits 20:20\r | |
203 | UINT32 Cl28 : 1; ///< Bits 21:21\r | |
204 | UINT32 Cl29 : 1; ///< Bits 22:22\r | |
205 | UINT32 Cl30 : 1; ///< Bits 23:23\r | |
206 | UINT32 Cl31 : 1; ///< Bits 24:24\r | |
207 | UINT32 Cl32 : 1; ///< Bits 25:25\r | |
208 | UINT32 Cl33 : 1; ///< Bits 26:26\r | |
209 | UINT32 Cl34 : 1; ///< Bits 27:27\r | |
210 | UINT32 Cl35 : 1; ///< Bits 28:28\r | |
211 | UINT32 Cl36 : 1; ///< Bits 29:29\r | |
212 | UINT32 Reserved : 1; ///< Bits 30:30\r | |
213 | UINT32 ClRange : 1; ///< Bits 31:31\r | |
214 | } Bits;\r | |
215 | struct {\r | |
216 | UINT32 Cl23 : 1; ///< Bits 0:0\r | |
217 | UINT32 Cl24 : 1; ///< Bits 1:1\r | |
218 | UINT32 Cl25 : 1; ///< Bits 2:2\r | |
219 | UINT32 Cl26 : 1; ///< Bits 3:3\r | |
220 | UINT32 Cl27 : 1; ///< Bits 4:4\r | |
221 | UINT32 Cl28 : 1; ///< Bits 5:5\r | |
222 | UINT32 Cl29 : 1; ///< Bits 6:6\r | |
223 | UINT32 Cl30 : 1; ///< Bits 7:7\r | |
224 | UINT32 Cl31 : 1; ///< Bits 8:8\r | |
225 | UINT32 Cl32 : 1; ///< Bits 9:9\r | |
226 | UINT32 Cl33 : 1; ///< Bits 10:10\r | |
227 | UINT32 Cl34 : 1; ///< Bits 11:11\r | |
228 | UINT32 Cl35 : 1; ///< Bits 12:12\r | |
229 | UINT32 Cl36 : 1; ///< Bits 13:13\r | |
230 | UINT32 Cl37 : 1; ///< Bits 14:14\r | |
231 | UINT32 Cl38 : 1; ///< Bits 15:15\r | |
232 | UINT32 Cl39 : 1; ///< Bits 16:16\r | |
233 | UINT32 Cl40 : 1; ///< Bits 17:17\r | |
234 | UINT32 Cl41 : 1; ///< Bits 18:18\r | |
235 | UINT32 Cl42 : 1; ///< Bits 19:19\r | |
236 | UINT32 Cl43 : 1; ///< Bits 20:20\r | |
237 | UINT32 Cl44 : 1; ///< Bits 21:21\r | |
238 | UINT32 Cl45 : 1; ///< Bits 22:22\r | |
239 | UINT32 Cl46 : 1; ///< Bits 23:23\r | |
240 | UINT32 Cl47 : 1; ///< Bits 24:24\r | |
241 | UINT32 Cl48 : 1; ///< Bits 25:25\r | |
242 | UINT32 Cl49 : 1; ///< Bits 26:26\r | |
243 | UINT32 Cl50 : 1; ///< Bits 27:27\r | |
244 | UINT32 Cl51 : 1; ///< Bits 28:28\r | |
245 | UINT32 Cl52 : 1; ///< Bits 29:29\r | |
246 | UINT32 Reserved : 1; ///< Bits 30:30\r | |
247 | UINT32 ClRange : 1; ///< Bits 31:31\r | |
248 | } HighRangeBits;\r | |
249 | UINT32 Data;\r | |
250 | UINT16 Data16[2];\r | |
251 | UINT8 Data8[4];\r | |
252 | } SPD4_CAS_LATENCIES_SUPPORTED_STRUCT;\r | |
253 | \r | |
254 | typedef union {\r | |
255 | struct {\r | |
256 | UINT8 tAAmin : 8; ///< Bits 7:0\r | |
257 | } Bits;\r | |
258 | UINT8 Data;\r | |
259 | } SPD4_TAA_MIN_MTB_STRUCT;\r | |
260 | \r | |
261 | typedef union {\r | |
262 | struct {\r | |
263 | UINT8 tRCDmin : 8; ///< Bits 7:0\r | |
264 | } Bits;\r | |
265 | UINT8 Data;\r | |
266 | } SPD4_TRCD_MIN_MTB_STRUCT;\r | |
267 | \r | |
268 | typedef union {\r | |
269 | struct {\r | |
270 | UINT8 tRPmin : 8; ///< Bits 7:0\r | |
271 | } Bits;\r | |
272 | UINT8 Data;\r | |
273 | } SPD4_TRP_MIN_MTB_STRUCT;\r | |
274 | \r | |
275 | typedef union {\r | |
276 | struct {\r | |
277 | UINT8 tRASminUpper : 4; ///< Bits 3:0\r | |
278 | UINT8 tRCminUpper : 4; ///< Bits 7:4\r | |
279 | } Bits;\r | |
280 | UINT8 Data;\r | |
281 | } SPD4_TRAS_TRC_MIN_MTB_STRUCT;\r | |
282 | \r | |
283 | typedef union {\r | |
284 | struct {\r | |
285 | UINT8 tRASmin : 8; ///< Bits 7:0\r | |
286 | } Bits;\r | |
287 | UINT8 Data;\r | |
288 | } SPD4_TRAS_MIN_MTB_STRUCT;\r | |
289 | \r | |
290 | typedef union {\r | |
291 | struct {\r | |
292 | UINT8 tRCmin : 8; ///< Bits 7:0\r | |
293 | } Bits;\r | |
294 | UINT8 Data;\r | |
295 | } SPD4_TRC_MIN_MTB_STRUCT;\r | |
296 | \r | |
297 | typedef union {\r | |
298 | struct {\r | |
299 | UINT16 tRFCmin : 16; ///< Bits 15:0\r | |
300 | } Bits;\r | |
301 | UINT16 Data;\r | |
302 | UINT8 Data8[2];\r | |
303 | } SPD4_TRFC_MIN_MTB_STRUCT;\r | |
304 | \r | |
305 | typedef union {\r | |
306 | struct {\r | |
307 | UINT8 tFAWminUpper : 4; ///< Bits 3:0\r | |
308 | UINT8 Reserved : 4; ///< Bits 7:4\r | |
309 | } Bits;\r | |
310 | UINT8 Data;\r | |
311 | } SPD4_TFAW_MIN_MTB_UPPER_STRUCT;\r | |
312 | \r | |
313 | typedef union {\r | |
314 | struct {\r | |
315 | UINT8 tFAWmin : 8; ///< Bits 7:0\r | |
316 | } Bits;\r | |
317 | UINT8 Data;\r | |
318 | } SPD4_TFAW_MIN_MTB_STRUCT;\r | |
319 | \r | |
320 | typedef union {\r | |
321 | struct {\r | |
322 | UINT8 tRRDmin : 8; ///< Bits 7:0\r | |
323 | } Bits;\r | |
324 | UINT8 Data;\r | |
325 | } SPD4_TRRD_MIN_MTB_STRUCT;\r | |
326 | \r | |
327 | typedef union {\r | |
328 | struct {\r | |
329 | UINT8 tCCDmin : 8; ///< Bits 7:0\r | |
330 | } Bits;\r | |
331 | UINT8 Data;\r | |
332 | } SPD4_TCCD_MIN_MTB_STRUCT;\r | |
333 | \r | |
334 | typedef union {\r | |
335 | struct {\r | |
336 | UINT8 tWRminMostSignificantNibble : 4; ///< Bits 3:0\r | |
337 | UINT8 Reserved : 4; ///< Bits 7:4\r | |
338 | } Bits;\r | |
339 | UINT8 Data;\r | |
340 | } SPD4_TWR_UPPER_NIBBLE_STRUCT;\r | |
341 | \r | |
342 | typedef union {\r | |
343 | struct {\r | |
344 | UINT8 tWRmin : 8; ///< Bits 7:0\r | |
345 | } Bits;\r | |
346 | UINT8 Data;\r | |
347 | } SPD4_TWR_MIN_MTB_STRUCT;\r | |
348 | \r | |
349 | typedef union {\r | |
350 | struct {\r | |
351 | UINT8 tWTR_SminMostSignificantNibble : 4; ///< Bits 3:0\r | |
352 | UINT8 tWTR_LminMostSignificantNibble : 4; ///< Bits 7:4\r | |
353 | } Bits;\r | |
354 | UINT8 Data;\r | |
355 | } SPD4_TWTR_UPPER_NIBBLE_STRUCT;\r | |
356 | \r | |
357 | typedef union {\r | |
358 | struct {\r | |
359 | UINT8 tWTRmin : 8; ///< Bits 7:0\r | |
360 | } Bits;\r | |
361 | UINT8 Data;\r | |
362 | } SPD4_TWTR_MIN_MTB_STRUCT;\r | |
363 | \r | |
364 | typedef union {\r | |
365 | struct {\r | |
366 | UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0\r | |
367 | UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5\r | |
368 | UINT8 PackageRankMap : 2; ///< Bits 7:6\r | |
369 | } Bits;\r | |
370 | UINT8 Data;\r | |
371 | } SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;\r | |
372 | \r | |
373 | typedef union {\r | |
374 | struct {\r | |
375 | INT8 tCCDminFine : 8; ///< Bits 7:0\r | |
376 | } Bits;\r | |
377 | INT8 Data;\r | |
378 | } SPD4_TCCD_MIN_FTB_STRUCT;\r | |
379 | \r | |
380 | typedef union {\r | |
381 | struct {\r | |
382 | INT8 tRRDminFine : 8; ///< Bits 7:0\r | |
383 | } Bits;\r | |
384 | INT8 Data;\r | |
385 | } SPD4_TRRD_MIN_FTB_STRUCT;\r | |
386 | \r | |
387 | typedef union {\r | |
388 | struct {\r | |
389 | INT8 tRCminFine : 8; ///< Bits 7:0\r | |
390 | } Bits;\r | |
391 | INT8 Data;\r | |
392 | } SPD4_TRC_MIN_FTB_STRUCT;\r | |
393 | \r | |
394 | typedef union {\r | |
395 | struct {\r | |
396 | INT8 tRPminFine : 8; ///< Bits 7:0\r | |
397 | } Bits;\r | |
398 | INT8 Data;\r | |
399 | } SPD4_TRP_MIN_FTB_STRUCT;\r | |
400 | \r | |
401 | typedef union {\r | |
402 | struct {\r | |
403 | INT8 tRCDminFine : 8; ///< Bits 7:0\r | |
404 | } Bits;\r | |
405 | INT8 Data;\r | |
406 | } SPD4_TRCD_MIN_FTB_STRUCT;\r | |
407 | \r | |
408 | typedef union {\r | |
409 | struct {\r | |
410 | INT8 tAAminFine : 8; ///< Bits 7:0\r | |
411 | } Bits;\r | |
412 | INT8 Data;\r | |
413 | } SPD4_TAA_MIN_FTB_STRUCT;\r | |
414 | \r | |
415 | typedef union {\r | |
416 | struct {\r | |
417 | INT8 tCKmaxFine : 8; ///< Bits 7:0\r | |
418 | } Bits;\r | |
419 | INT8 Data;\r | |
420 | } SPD4_TCK_MAX_FTB_STRUCT;\r | |
421 | \r | |
422 | typedef union {\r | |
423 | struct {\r | |
424 | INT8 tCKminFine : 8; ///< Bits 7:0\r | |
425 | } Bits;\r | |
426 | INT8 Data;\r | |
427 | } SPD4_TCK_MIN_FTB_STRUCT;\r | |
428 | \r | |
429 | typedef union {\r | |
430 | struct {\r | |
431 | UINT8 Height : 5; ///< Bits 4:0\r | |
432 | UINT8 RawCardExtension : 3; ///< Bits 7:5\r | |
433 | } Bits;\r | |
434 | UINT8 Data;\r | |
435 | } SPD4_UNBUF_MODULE_NOMINAL_HEIGHT;\r | |
436 | \r | |
437 | typedef union {\r | |
438 | struct {\r | |
439 | UINT8 FrontThickness : 4; ///< Bits 3:0\r | |
440 | UINT8 BackThickness : 4; ///< Bits 7:4\r | |
441 | } Bits;\r | |
442 | UINT8 Data;\r | |
443 | } SPD4_UNBUF_MODULE_NOMINAL_THICKNESS;\r | |
444 | \r | |
445 | typedef union {\r | |
446 | struct {\r | |
447 | UINT8 Card : 5; ///< Bits 4:0\r | |
448 | UINT8 Revision : 2; ///< Bits 6:5\r | |
449 | UINT8 Extension : 1; ///< Bits 7:7\r | |
450 | } Bits;\r | |
451 | UINT8 Data;\r | |
452 | } SPD4_UNBUF_REFERENCE_RAW_CARD;\r | |
453 | \r | |
454 | typedef union {\r | |
455 | struct {\r | |
456 | UINT8 MappingRank1 : 1; ///< Bits 0:0\r | |
457 | UINT8 Reserved : 7; ///< Bits 7:1\r | |
458 | } Bits;\r | |
459 | UINT8 Data;\r | |
460 | } SPD4_UNBUF_ADDRESS_MAPPING;\r | |
461 | \r | |
462 | typedef union {\r | |
463 | struct {\r | |
464 | UINT8 Height : 5; ///< Bits 4:0\r | |
465 | UINT8 Reserved : 3; ///< Bits 7:5\r | |
466 | } Bits;\r | |
467 | UINT8 Data;\r | |
468 | } SPD4_RDIMM_MODULE_NOMINAL_HEIGHT;\r | |
469 | \r | |
470 | typedef union {\r | |
471 | struct {\r | |
472 | UINT8 FrontThickness : 4; ///< Bits 3:0\r | |
473 | UINT8 BackThickness : 4; ///< Bits 7:4\r | |
474 | } Bits;\r | |
475 | UINT8 Data;\r | |
476 | } SPD4_RDIMM_MODULE_NOMINAL_THICKNESS;\r | |
477 | \r | |
478 | typedef union {\r | |
479 | struct {\r | |
480 | UINT8 Card : 5; ///< Bits 4:0\r | |
481 | UINT8 Revision : 2; ///< Bits 6:5\r | |
482 | UINT8 Extension : 1; ///< Bits 7:7\r | |
483 | } Bits;\r | |
484 | UINT8 Data;\r | |
485 | } SPD4_RDIMM_REFERENCE_RAW_CARD;\r | |
486 | \r | |
487 | typedef union {\r | |
488 | struct {\r | |
489 | UINT8 RegisterCount : 2; ///< Bits 1:0\r | |
490 | UINT8 DramRowCount : 2; ///< Bits 3:2\r | |
491 | UINT8 RegisterType : 4; ///< Bits 7:4\r | |
492 | } Bits;\r | |
493 | UINT8 Data;\r | |
494 | } SPD4_RDIMM_MODULE_ATTRIBUTES;\r | |
495 | \r | |
496 | typedef union {\r | |
497 | struct {\r | |
498 | UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r | |
499 | UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r | |
500 | } Bits;\r | |
501 | UINT8 Data;\r | |
502 | } SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r | |
503 | \r | |
504 | typedef union {\r | |
505 | struct {\r | |
506 | UINT16 ContinuationCount : 7; ///< Bits 6:0\r | |
507 | UINT16 ContinuationParity : 1; ///< Bits 7:7\r | |
508 | UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r | |
509 | } Bits;\r | |
510 | UINT16 Data;\r | |
511 | UINT8 Data8[2];\r | |
512 | } SPD4_MANUFACTURER_ID_CODE;\r | |
513 | \r | |
514 | typedef union {\r | |
515 | struct {\r | |
516 | UINT8 RegisterRevisionNumber; ///< Bits 7:0\r | |
517 | } Bits;\r | |
518 | UINT8 Data;\r | |
519 | } SPD4_RDIMM_REGISTER_REVISION_NUMBER;\r | |
520 | \r | |
521 | typedef union {\r | |
522 | struct {\r | |
523 | UINT8 Rank1Mapping : 1; ///< Bits 0:0\r | |
524 | UINT8 Reserved : 7; ///< Bits 7:1\r | |
525 | } Bits;\r | |
526 | UINT8 Data;\r | |
527 | } SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;\r | |
528 | \r | |
529 | typedef union {\r | |
530 | struct {\r | |
531 | UINT8 Cke : 2; ///< Bits 1:0\r | |
532 | UINT8 Odt : 2; ///< Bits 3:2\r | |
533 | UINT8 CommandAddress : 2; ///< Bits 5:4\r | |
534 | UINT8 ChipSelect : 2; ///< Bits 7:6\r | |
535 | } Bits;\r | |
536 | UINT8 Data;\r | |
537 | } SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;\r | |
538 | \r | |
539 | typedef union {\r | |
540 | struct {\r | |
541 | UINT8 Y0Y2 : 2; ///< Bits 1:0\r | |
542 | UINT8 Y1Y3 : 2; ///< Bits 3:2\r | |
543 | UINT8 Reserved0 : 2; ///< Bits 5:4\r | |
544 | UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6\r | |
545 | UINT8 Reserved1 : 1; ///< Bits 7:7\r | |
546 | } Bits;\r | |
547 | UINT8 Data;\r | |
548 | } SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;\r | |
549 | \r | |
550 | typedef union {\r | |
551 | struct {\r | |
552 | UINT8 Height : 5; ///< Bits 4:0\r | |
553 | UINT8 Reserved : 3; ///< Bits 7:5\r | |
554 | } Bits;\r | |
555 | UINT8 Data;\r | |
556 | } SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT;\r | |
557 | \r | |
558 | typedef union {\r | |
559 | struct {\r | |
560 | UINT8 FrontThickness : 4; ///< Bits 3:0\r | |
561 | UINT8 BackThickness : 4; ///< Bits 7:4\r | |
562 | } Bits;\r | |
563 | UINT8 Data;\r | |
564 | } SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS;\r | |
565 | \r | |
566 | typedef union {\r | |
567 | struct {\r | |
568 | UINT8 Card : 5; ///< Bits 4:0\r | |
569 | UINT8 Revision : 2; ///< Bits 6:5\r | |
570 | UINT8 Extension : 1; ///< Bits 7:7\r | |
571 | } Bits;\r | |
572 | UINT8 Data;\r | |
573 | } SPD4_LRDIMM_REFERENCE_RAW_CARD;\r | |
574 | \r | |
575 | typedef union {\r | |
576 | struct {\r | |
577 | UINT8 RegisterCount : 2; ///< Bits 1:0\r | |
578 | UINT8 DramRowCount : 2; ///< Bits 3:2\r | |
579 | UINT8 RegisterType : 4; ///< Bits 7:4\r | |
580 | } Bits;\r | |
581 | UINT8 Data;\r | |
582 | } SPD4_LRDIMM_MODULE_ATTRIBUTES;\r | |
583 | \r | |
584 | typedef union {\r | |
585 | struct {\r | |
586 | UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r | |
587 | UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r | |
588 | } Bits;\r | |
589 | UINT8 Data;\r | |
590 | } SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r | |
591 | \r | |
592 | typedef union {\r | |
593 | struct {\r | |
594 | UINT8 RegisterRevisionNumber; ///< Bits 7:0\r | |
595 | } Bits;\r | |
596 | UINT8 Data;\r | |
597 | } SPD4_LRDIMM_REGISTER_REVISION_NUMBER;\r | |
598 | \r | |
599 | typedef union {\r | |
600 | struct {\r | |
601 | UINT8 Rank1Mapping : 1; ///< Bits 0:0\r | |
602 | UINT8 Reserved : 7; ///< Bits 7:1\r | |
603 | } Bits;\r | |
604 | UINT8 Data;\r | |
605 | } SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;\r | |
606 | \r | |
607 | typedef union {\r | |
608 | struct {\r | |
609 | UINT8 Cke : 2; ///< Bits 1:0\r | |
610 | UINT8 Odt : 2; ///< Bits 3:2\r | |
611 | UINT8 CommandAddress : 2; ///< Bits 5:4\r | |
612 | UINT8 ChipSelect : 2; ///< Bits 7:6\r | |
613 | } Bits;\r | |
614 | UINT8 Data;\r | |
615 | } SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;\r | |
616 | \r | |
617 | typedef union {\r | |
618 | struct {\r | |
619 | UINT8 Y0Y2 : 2; ///< Bits 1:0\r | |
620 | UINT8 Y1Y3 : 2; ///< Bits 3:2\r | |
621 | UINT8 Reserved0 : 2; ///< Bits 5:4\r | |
622 | UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6\r | |
623 | UINT8 Reserved1 : 1; ///< Bits 7:7\r | |
624 | } Bits;\r | |
625 | UINT8 Data;\r | |
626 | } SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;\r | |
627 | \r | |
628 | typedef struct {\r | |
629 | UINT8 DataBufferRevisionNumber;\r | |
630 | } SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER;\r | |
631 | \r | |
632 | typedef union {\r | |
633 | struct {\r | |
634 | UINT8 DramVrefDQForPackageRank0 : 6; ///< Bits 5:0\r | |
635 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
636 | } Bits;\r | |
637 | UINT8 Data;\r | |
638 | } SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK;\r | |
639 | \r | |
640 | typedef struct {\r | |
641 | UINT8 DataBufferVrefDQforDramInterface;\r | |
642 | } SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE;\r | |
643 | \r | |
644 | typedef union {\r | |
645 | struct {\r | |
646 | UINT8 DramInterfaceMdqDriveStrength : 4; ///< Bits 3:0\r | |
647 | UINT8 DramInterfaceMdqReadTerminationStrength : 4; ///< Bits 7:4\r | |
648 | } Bits;\r | |
649 | UINT8 Data;\r | |
650 | } SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE;\r | |
651 | \r | |
652 | typedef union {\r | |
653 | struct {\r | |
654 | UINT8 DataRateLe1866 : 2; ///< Bits 1:0\r | |
655 | UINT8 DataRateLe2400 : 2; ///< Bits 3:2\r | |
656 | UINT8 DataRateLe3200 : 2; ///< Bits 5:4\r | |
657 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
658 | } Bits;\r | |
659 | UINT8 Data;\r | |
660 | } SPD4_LRDIMM_DRAM_DRIVE_STRENGTH;\r | |
661 | \r | |
662 | typedef union {\r | |
663 | struct {\r | |
664 | UINT8 Rtt_Nom : 3; ///< Bits 2:0\r | |
665 | UINT8 Rtt_WR : 3; ///< Bits 5:3\r | |
666 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
667 | } Bits;\r | |
668 | UINT8 Data;\r | |
669 | } SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE;\r | |
670 | \r | |
671 | typedef union {\r | |
672 | struct {\r | |
673 | UINT8 PackageRanks0_1 : 3; ///< Bits 2:0\r | |
674 | UINT8 PackageRanks2_3 : 3; ///< Bits 5:3\r | |
675 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
676 | } Bits;\r | |
677 | UINT8 Data;\r | |
678 | } SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE;\r | |
679 | \r | |
680 | typedef union {\r | |
681 | struct {\r | |
682 | UINT8 Rank0 : 1; ///< Bits 0:0\r | |
683 | UINT8 Rank1 : 1; ///< Bits 1:1\r | |
684 | UINT8 Rank2 : 1; ///< Bits 2:2\r | |
685 | UINT8 Rank3 : 1; ///< Bits 3:3\r | |
686 | UINT8 DataBuffer : 1; ///< Bits 4:4\r | |
687 | UINT8 Reserved : 3; ///< Bits 7:5\r | |
688 | } Bits;\r | |
689 | UINT8 Data;\r | |
690 | } SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE;\r | |
691 | \r | |
692 | typedef union {\r | |
693 | struct {\r | |
694 | UINT8 DataBufferGainAdjustment : 1; ///< Bits 0:0\r | |
695 | UINT8 DataBufferDfe : 1; ///< Bits 1:1\r | |
696 | UINT8 Reserved : 6; ///< Bits 7:2\r | |
697 | } Bits;\r | |
698 | UINT8 Data;\r | |
699 | } SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION;\r | |
700 | \r | |
701 | typedef UINT16 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER;\r | |
702 | \r | |
703 | typedef union {\r | |
704 | struct {\r | |
705 | UINT16 ContinuationCount : 7; ///< Bits 6:0\r | |
706 | UINT16 ContinuationParity : 1; ///< Bits 7:7\r | |
707 | UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r | |
708 | } Bits;\r | |
709 | UINT16 Data;\r | |
710 | UINT8 Data8[2];\r | |
711 | } SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE;\r | |
712 | \r | |
713 | typedef UINT16 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER;\r | |
714 | \r | |
715 | typedef UINT8 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE;\r | |
716 | \r | |
717 | typedef union {\r | |
718 | struct {\r | |
719 | UINT8 Card : 5; ///< Bits 4:0\r | |
720 | UINT8 Revision : 2; ///< Bits 6:5\r | |
721 | UINT8 Extension : 1; ///< Bits 7:7\r | |
722 | } Bits;\r | |
723 | UINT8 Data;\r | |
724 | } SPD4_NVDIMM_REFERENCE_RAW_CARD;\r | |
725 | \r | |
726 | typedef union {\r | |
727 | struct {\r | |
728 | UINT8 Reserved : 4; ///< Bits 3:0\r | |
729 | UINT8 Extension : 4; ///< Bits 7:4\r | |
730 | } Bits;\r | |
731 | UINT8 Data;\r | |
732 | } SPD4_NVDIMM_MODULE_CHARACTERISTICS;\r | |
733 | \r | |
734 | typedef struct {\r | |
735 | UINT8 Reserved;\r | |
736 | UINT8 MediaType;\r | |
737 | } SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES;\r | |
738 | \r | |
739 | typedef UINT8 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME;\r | |
740 | \r | |
741 | typedef union {\r | |
742 | struct {\r | |
743 | UINT16 FunctionInterface : 5; ///< Bits 4:0\r | |
744 | UINT16 FunctionClass : 5; ///< Bits 9:5\r | |
745 | UINT16 BlockOffset : 4; ///< Bits 13:10\r | |
746 | UINT16 Reserved : 1; ///< Bits 14:14\r | |
747 | UINT16 Implemented : 1; ///< Bits 15:15\r | |
748 | } Bits;\r | |
749 | UINT16 Data;\r | |
750 | UINT8 Data8[2];\r | |
751 | } SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR;\r | |
752 | \r | |
753 | typedef struct {\r | |
754 | UINT8 Year; ///< Year represented in BCD (00h = 2000)\r | |
755 | UINT8 Week; ///< Year represented in BCD (47h = week 47)\r | |
756 | } SPD4_MANUFACTURING_DATE;\r | |
757 | \r | |
758 | typedef union {\r | |
759 | UINT32 Data;\r | |
760 | UINT16 SerialNumber16[2];\r | |
761 | UINT8 SerialNumber8[4];\r | |
762 | } SPD4_MANUFACTURER_SERIAL_NUMBER;\r | |
763 | \r | |
764 | typedef struct {\r | |
765 | UINT8 Location; ///< Module Manufacturing Location\r | |
766 | } SPD4_MANUFACTURING_LOCATION;\r | |
767 | \r | |
768 | typedef struct {\r | |
769 | SPD4_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r | |
770 | SPD4_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r | |
771 | SPD4_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r | |
772 | SPD4_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r | |
773 | } SPD4_UNIQUE_MODULE_ID;\r | |
774 | \r | |
775 | typedef union {\r | |
776 | UINT16 Crc[1];\r | |
777 | UINT8 Data8[2];\r | |
778 | } SPD4_CYCLIC_REDUNDANCY_CODE;\r | |
779 | \r | |
780 | typedef struct {\r | |
781 | SPD4_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r | |
782 | SPD4_REVISION_STRUCT Revision; ///< 1 SPD Revision\r | |
783 | SPD4_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r | |
784 | SPD4_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r | |
785 | SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r | |
786 | SPD4_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r | |
787 | SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT PrimarySdramPackageType; ///< 6 Primary SDRAM Package Type\r | |
788 | SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features\r | |
789 | SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options\r | |
790 | SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features\r | |
791 | SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramPackageType;///< 10 Secondary SDRAM Package Type\r | |
792 | SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD\r | |
793 | SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization\r | |
794 | SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width\r | |
795 | SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor\r | |
796 | SPD4_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type\r | |
797 | UINT8 Reserved0; ///< 16 Reserved\r | |
798 | SPD4_TIMEBASE_STRUCT Timebase; ///< 17 Timebases\r | |
799 | SPD4_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)\r | |
800 | SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)\r | |
801 | SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported\r | |
802 | SPD4_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)\r | |
803 | SPD4_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin)\r | |
804 | SPD4_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin)\r | |
805 | SPD4_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC\r | |
806 | SPD4_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r | |
807 | SPD4_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r | |
808 | SPD4_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min)\r | |
809 | SPD4_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min)\r | |
810 | SPD4_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min)\r | |
811 | SPD4_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW\r | |
812 | SPD4_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin)\r | |
813 | SPD4_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group\r | |
814 | SPD4_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group\r | |
815 | SPD4_TCCD_MIN_MTB_STRUCT tCCD_Lmin; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group\r | |
816 | SPD4_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble; ///< 41 Upper Nibble for tWRmin\r | |
817 | SPD4_TWR_MIN_MTB_STRUCT tWRmin; ///< 42 Minimum Write Recovery Time (tWRmin)\r | |
818 | SPD4_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble; ///< 43 Upper Nibbles for tWTRmin\r | |
819 | SPD4_TWTR_MIN_MTB_STRUCT tWTR_Smin; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group\r | |
820 | SPD4_TWTR_MIN_MTB_STRUCT tWTR_Lmin; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group\r | |
821 | UINT8 Reserved1[59 - 46 + 1]; ///< 46-59 Reserved\r | |
822 | SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping\r | |
823 | UINT8 Reserved2[116 - 78 + 1]; ///< 78-116 Reserved\r | |
824 | SPD4_TCCD_MIN_FTB_STRUCT tCCD_LminFine; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group\r | |
825 | SPD4_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group\r | |
826 | SPD4_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group\r | |
827 | SPD4_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r | |
828 | SPD4_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin)\r | |
829 | SPD4_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r | |
830 | SPD4_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)\r | |
831 | SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)\r | |
832 | SPD4_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin)\r | |
833 | SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r | |
834 | } SPD4_BASE_SECTION;\r | |
835 | \r | |
836 | typedef struct {\r | |
837 | SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r | |
838 | SPD4_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r | |
839 | SPD4_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r | |
840 | SPD4_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM\r | |
841 | UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved\r | |
842 | SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r | |
843 | } SPD4_MODULE_UNBUFFERED;\r | |
844 | \r | |
845 | typedef struct {\r | |
846 | SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r | |
847 | SPD4_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r | |
848 | SPD4_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r | |
849 | SPD4_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes\r | |
850 | SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution\r | |
851 | SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code\r | |
852 | SPD4_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number\r | |
853 | SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM; ///< 136 Address Mapping from Register to DRAM\r | |
854 | SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address\r | |
855 | SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock\r | |
856 | UINT8 Reserved[253 - 139 + 1]; ///< 253-139 Reserved\r | |
857 | SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r | |
858 | } SPD4_MODULE_REGISTERED;\r | |
859 | \r | |
860 | typedef struct {\r | |
861 | SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r | |
862 | SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r | |
863 | SPD4_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r | |
864 | SPD4_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes\r | |
865 | SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution\r | |
866 | SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code\r | |
867 | SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number\r | |
868 | SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDram; ///< 136 Address Mapping from Register to DRAM\r | |
869 | SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address\r | |
870 | SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock\r | |
871 | SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber; ///< 139 Data Buffer Revision Number\r | |
872 | SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank0; ///< 140 DRAM VrefDQ for Package Rank 0\r | |
873 | SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank1; ///< 141 DRAM VrefDQ for Package Rank 1\r | |
874 | SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank2; ///< 142 DRAM VrefDQ for Package Rank 2\r | |
875 | SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank3; ///< 143 DRAM VrefDQ for Package Rank 3\r | |
876 | SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQForDramInterface; ///< 144 Data Buffer VrefDQ for DRAM Interface\r | |
877 | SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe1866; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866\r | |
878 | SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe2400; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400\r | |
879 | SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe3200; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200\r | |
880 | SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DramDriveStrength; ///< 148 DRAM Drive Strength\r | |
881 | SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe1866; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866\r | |
882 | SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe2400; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400\r | |
883 | SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe3200; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200\r | |
884 | SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe1866; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866\r | |
885 | SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe2400; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400\r | |
886 | SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe3200; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200\r | |
887 | SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQForDramInterfaceRange; ///< 155 Data Buffer VrefDQ for DRAM Interface Range\r | |
888 | SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDqDecisionFeedbackEqualization; ///< 156 Data Buffer DQ Decision Feedback Equalization\r | |
889 | UINT8 Reserved[253 - 157 + 1]; ///< 253-132 Reserved\r | |
890 | SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r | |
891 | } SPD4_MODULE_LOADREDUCED;\r | |
892 | \r | |
893 | typedef struct {\r | |
894 | UINT8 Reserved0[191 - 128 + 1]; ///< 128-191 Reserved\r | |
895 | SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier; ///< 192-193 Module Product Identifier\r | |
896 | SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIdCode; ///< 194-195 Subsystem Controller Manufacturer's ID Code\r | |
897 | SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier; ///< 196-197 Subsystem Controller Identifier\r | |
898 | SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode; ///< 198 Subsystem Controller Revision Code\r | |
899 | SPD4_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 199 Reference Raw Card Used\r | |
900 | SPD4_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics; ///< 200 Module Characteristics\r | |
901 | SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes; ///< 201-202 Hybrid Module Media Types\r | |
902 | SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime; ///< 203 Maximum Non-Volatile Memory Initialization Time\r | |
903 | SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors[8]; ///< 204-219 Function Interface Descriptors\r | |
904 | UINT8 Reserved[253 - 220 + 1]; ///< 220-253 Reserved\r | |
905 | SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r | |
906 | } SPD4_MODULE_NVDIMM;\r | |
907 | \r | |
908 | typedef union {\r | |
909 | SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r | |
910 | SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r | |
911 | SPD4_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r | |
912 | SPD4_MODULE_NVDIMM NonVolatile; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters\r | |
913 | } SPD4_MODULE_SPECIFIC;\r | |
914 | \r | |
915 | typedef struct {\r | |
916 | UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number\r | |
917 | } SPD4_MODULE_PART_NUMBER;\r | |
918 | \r | |
919 | typedef struct {\r | |
920 | UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data\r | |
921 | } SPD4_MANUFACTURER_SPECIFIC;\r | |
922 | \r | |
923 | typedef UINT8 SPD4_MODULE_REVISION_CODE;///< 349 Module Revision Code\r | |
924 | typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping\r | |
925 | \r | |
926 | typedef struct {\r | |
927 | SPD4_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID\r | |
928 | SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number\r | |
929 | SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code\r | |
930 | SPD4_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code\r | |
931 | SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping\r | |
932 | SPD4_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data\r | |
933 | UINT8 Reserved[2]; ///< 382-383 Reserved\r | |
934 | } SPD4_MANUFACTURING_DATA;\r | |
935 | \r | |
936 | typedef struct {\r | |
937 | UINT8 Reserved[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types\r | |
938 | } SPD4_END_USER_SECTION;\r | |
939 | \r | |
940 | ///\r | |
941 | /// DDR4 Serial Presence Detect structure\r | |
942 | ///\r | |
943 | typedef struct {\r | |
944 | SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters\r | |
945 | SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section\r | |
946 | UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Reserved\r | |
947 | SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information\r | |
948 | SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable\r | |
949 | } SPD_DDR4;\r | |
950 | \r | |
951 | #pragma pack (pop)\r | |
952 | #endif\r |