[mirror_edk2.git] / MdePkg / Include / IndustryStandard / TpmPtp.h

/** @file\r
  Platform TPM Profile Specification definition for TPM2.0.\r
  It covers both FIFO and CRB interface.\r
\r
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _TPM_PTP_H_\r
#define _TPM_PTP_H_\r
\r
//\r
// PTP FIFO definition\r
//\r
\r
//\r
// Set structure alignment to 1-byte\r
//\r
#pragma pack (1)\r
\r
//\r
// Register set map as specified in PTP specification Chapter 5\r
//\r
typedef struct {\r
  ///\r
  /// Used to gain ownership for this particular port.\r
  ///\r
  UINT8     Access;                                     // 0\r
  UINT8     Reserved1[7];                               // 1\r
  ///\r
  /// Controls interrupts.\r
  ///\r
  UINT32    IntEnable;                                  // 8\r
  ///\r
  /// SIRQ vector to be used by the TPM.\r
  ///\r
  UINT8     IntVector;                                  // 0ch\r
  UINT8     Reserved2[3];                               // 0dh\r
  ///\r
  /// What caused interrupt.\r
  ///\r
  UINT32    IntSts;                                     // 10h\r
  ///\r
  /// Shows which interrupts are supported by that particular TPM.\r
  ///\r
  UINT32    InterfaceCapability;                        // 14h\r
  ///\r
  /// Status Register. Provides status of the TPM.\r
  ///\r
  UINT8     Status;                                     // 18h\r
  ///\r
  /// Number of consecutive writes that can be done to the TPM.\r
  ///\r
  UINT16    BurstCount;                                 // 19h\r
  ///\r
  /// Additional Status Register.\r
  ///\r
  UINT8     StatusEx;                                   // 1Bh\r
  UINT8     Reserved3[8];\r
  ///\r
  /// Read or write FIFO, depending on transaction.\r
  ///\r
  UINT32    DataFifo;                                   // 24h\r
  UINT8     Reserved4[8];                               // 28h\r
  ///\r
  /// Used to identify the Interface types supported by the TPM.\r
  ///\r
  UINT32    InterfaceId;                                // 30h\r
  UINT8     Reserved5[0x4c];                            // 34h\r
  ///\r
  /// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)\r
  ///\r
  UINT32    XDataFifo;                                  // 80h\r
  UINT8     Reserved6[0xe7c];                           // 84h\r
  ///\r
  /// Vendor ID\r
  ///\r
  UINT16    Vid;                                        // 0f00h\r
  ///\r
  /// Device ID\r
  ///\r
  UINT16    Did;                                        // 0f02h\r
  ///\r
  /// Revision ID\r
  ///\r
  UINT8     Rid;                                        // 0f04h\r
  UINT8     Reserved[0xfb];                             // 0f05h\r
} PTP_FIFO_REGISTERS;\r
\r
//\r
// Restore original structure alignment\r
//\r
#pragma pack ()\r
\r
//\r
// Define pointer types used to access TIS registers on PC\r
//\r
typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;\r
\r
//\r
// Define bits of FIFO Interface Identifier Register\r
//\r
typedef union {\r
  struct {\r
    UINT32    InterfaceType          : 4;\r
    UINT32    InterfaceVersion       : 4;\r
    UINT32    CapLocality            : 1;\r
    UINT32    Reserved1              : 2;\r
    UINT32    CapDataXferSizeSupport : 2;\r
    UINT32    CapFIFO                : 1;\r
    UINT32    CapCRB                 : 1;\r
    UINT32    CapIFRes               : 2;\r
    UINT32    InterfaceSelector      : 2;\r
    UINT32    IntfSelLock            : 1;\r
    UINT32    Reserved2              : 4;\r
    UINT32    Reserved3              : 8;\r
  } Bits;\r
  UINT32    Uint32;\r
} PTP_FIFO_INTERFACE_IDENTIFIER;\r
\r
//\r
// Define bits of FIFO Interface Capability Register\r
//\r
typedef union {\r
  struct {\r
    UINT32    DataAvailIntSupport      : 1;\r
    UINT32    StsValidIntSupport       : 1;\r
    UINT32    LocalityChangeIntSupport : 1;\r
    UINT32    InterruptLevelHigh       : 1;\r
    UINT32    InterruptLevelLow        : 1;\r
    UINT32    InterruptEdgeRising      : 1;\r
    UINT32    InterruptEdgeFalling     : 1;\r
    UINT32    CommandReadyIntSupport   : 1;\r
    UINT32    BurstCountStatic         : 1;\r
    UINT32    DataTransferSizeSupport  : 2;\r
    UINT32    Reserved                 : 17;\r
    UINT32    InterfaceVersion         : 3;\r
    UINT32    Reserved2                : 1;\r
  } Bits;\r
  UINT32    Uint32;\r
} PTP_FIFO_INTERFACE_CAPABILITY;\r
\r
///\r
/// InterfaceVersion\r
///\r
#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12  0x0\r
#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13  0x2\r
#define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP     0x3\r
\r
//\r
// Define bits of ACCESS and STATUS registers\r
//\r
\r
///\r
/// This bit is a 1 to indicate that the other bits in this register are valid.\r
///\r
#define PTP_FIFO_VALID  BIT7\r
///\r
/// Indicate that this locality is active.\r
///\r
#define PTP_FIFO_ACC_ACTIVE  BIT5\r
///\r
/// Set to 1 to indicate that this locality had the TPM taken away while\r
/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
///\r
#define PTP_FIFO_ACC_SEIZED  BIT4\r
///\r
/// Set to 1 to indicate that TPM MUST reset the\r
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
/// locality that is writing this bit.\r
///\r
#define PTP_FIFO_ACC_SEIZE  BIT3\r
///\r
/// When this bit is 1, another locality is requesting usage of the TPM.\r
///\r
#define PTP_FIFO_ACC_PENDIND  BIT2\r
///\r
/// Set to 1 to indicate that this locality is requesting to use TPM.\r
///\r
#define PTP_FIFO_ACC_RQUUSE  BIT1\r
///\r
/// A value of 1 indicates that a T/OS has not been established on the platform\r
///\r
#define PTP_FIFO_ACC_ESTABLISH  BIT0\r
\r
///\r
/// This field indicates that STS_DATA and STS_EXPECT are valid\r
///\r
#define PTP_FIFO_STS_VALID  BIT7\r
///\r
/// When this bit is 1, TPM is in the Ready state,\r
/// indicating it is ready to receive a new command.\r
///\r
#define PTP_FIFO_STS_READY  BIT6\r
///\r
/// Write a 1 to this bit to cause the TPM to execute that command.\r
///\r
#define PTP_FIFO_STS_GO  BIT5\r
///\r
/// This bit indicates that the TPM has data available as a response.\r
///\r
#define PTP_FIFO_STS_DATA  BIT4\r
///\r
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
///\r
#define PTP_FIFO_STS_EXPECT  BIT3\r
///\r
/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
///\r
#define PTP_FIFO_STS_SELFTEST_DONE  BIT2\r
///\r
/// Writes a 1 to this bit to force the TPM to re-send the response.\r
///\r
#define PTP_FIFO_STS_RETRY  BIT1\r
\r
///\r
/// TPM Family Identifier.\r
/// 00: TPM 1.2 Family\r
/// 01: TPM 2.0 Family\r
///\r
#define PTP_FIFO_STS_EX_TPM_FAMILY         (BIT2 | BIT3)\r
#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET  (2)\r
#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12   (0)\r
#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20   (BIT2)\r
///\r
/// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.\r
/// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.\r
///\r
#define PTP_FIFO_STS_EX_CANCEL  BIT0\r
\r
//\r
// PTP CRB definition\r
//\r
\r
//\r
// Set structure alignment to 1-byte\r
//\r
#pragma pack (1)\r
\r
//\r
// Register set map as specified in PTP specification Chapter 5\r
//\r
typedef struct {\r
  ///\r
  /// Used to determine current state of Locality of the TPM.\r
  ///\r
  UINT32    LocalityState;                                     // 0\r
  UINT8     Reserved1[4];                                      // 4\r
  ///\r
  /// Used to gain control of the TPM by this Locality.\r
  ///\r
  UINT32    LocalityControl;                                   // 8\r
  ///\r
  /// Used to determine whether Locality has been granted or Seized.\r
  ///\r
  UINT32    LocalityStatus;                                    // 0ch\r
  UINT8     Reserved2[0x20];                                   // 10h\r
  ///\r
  /// Used to identify the Interface types supported by the TPM.\r
  ///\r
  UINT32    InterfaceId;                                       // 30h\r
  ///\r
  /// Vendor ID\r
  ///\r
  UINT16    Vid;                                               // 34h\r
  ///\r
  /// Device ID\r
  ///\r
  UINT16    Did;                                               // 36h\r
  ///\r
  /// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.\r
  ///\r
  UINT64    CrbControlExtension;                               // 38h\r
  ///\r
  /// Register used to initiate transactions for the CRB interface.\r
  ///\r
  UINT32    CrbControlRequest;                                 // 40h\r
  ///\r
  /// Register used by the TPM to provide status of the CRB interface.\r
  ///\r
  UINT32    CrbControlStatus;                                  // 44h\r
  ///\r
  /// Register used by software to cancel command processing.\r
  ///\r
  UINT32    CrbControlCancel;                                  // 48h\r
  ///\r
  /// Register used to indicate presence of command or response data in the CRB buffer.\r
  ///\r
  UINT32    CrbControlStart;                                   // 4Ch\r
  ///\r
  /// Register used to configure and respond to interrupts.\r
  ///\r
  UINT32    CrbInterruptEnable;                                // 50h\r
  UINT32    CrbInterruptStatus;                                // 54h\r
  ///\r
  /// Size of the Command buffer.\r
  ///\r
  UINT32    CrbControlCommandSize;                             // 58h\r
  ///\r
  /// Command buffer start address\r
  ///\r
  UINT32    CrbControlCommandAddressLow;                           // 5Ch\r
  UINT32    CrbControlCommandAddressHigh;                          // 60h\r
  ///\r
  /// Size of the Response buffer\r
  ///\r
  UINT32    CrbControlResponseSize;                            // 64h\r
  ///\r
  /// Address of the start of the Response buffer\r
  ///\r
  UINT64    CrbControlResponseAddrss;                          // 68h\r
  UINT8     Reserved4[0x10];                                   // 70h\r
  ///\r
  /// Command/Response Data may be defined as large as 3968 (0xF80).\r
  ///\r
  UINT8     CrbDataBuffer[0xF80];                              // 80h\r
} PTP_CRB_REGISTERS;\r
\r
//\r
// Define pointer types used to access CRB registers on PTP\r
//\r
typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;\r
\r
//\r
// Define bits of CRB Interface Identifier Register\r
//\r
typedef union {\r
  struct {\r
    UINT32    InterfaceType          : 4;\r
    UINT32    InterfaceVersion       : 4;\r
    UINT32    CapLocality            : 1;\r
    UINT32    CapCRBIdleBypass       : 1;\r
    UINT32    Reserved1              : 1;\r
    UINT32    CapDataXferSizeSupport : 2;\r
    UINT32    CapFIFO                : 1;\r
    UINT32    CapCRB                 : 1;\r
    UINT32    CapIFRes               : 2;\r
    UINT32    InterfaceSelector      : 2;\r
    UINT32    IntfSelLock            : 1;\r
    UINT32    Reserved2              : 4;\r
    UINT32    Rid                    : 8;\r
  } Bits;\r
  UINT32    Uint32;\r
} PTP_CRB_INTERFACE_IDENTIFIER;\r
\r
///\r
/// InterfaceType\r
///\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO  0x0\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB   0x1\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS   0xF\r
\r
///\r
/// InterfaceVersion\r
///\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO  0x0\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB   0x1\r
\r
///\r
/// InterfaceSelector\r
///\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO  0x0\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB   0x1\r
\r
//\r
// Define bits of Locality State Register\r
//\r
\r
///\r
/// This bit indicates whether all other bits of this register contain valid values, if it is a 1.\r
///\r
#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS  BIT7\r
\r
///\r
/// 000 - Locality 0\r
/// 001 - Locality 1\r
/// 010 - Locality 2\r
/// 011 - Locality 3\r
/// 100 - Locality 4\r
///\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK  (BIT2 | BIT3 | BIT4)\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0     (0)\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1     (BIT2)\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2     (BIT3)\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3     (BIT2 | BIT3)\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4     (BIT4)\r
\r
///\r
/// A 0 indicates to the host that no locality is assigned.\r
/// A 1 indicates a locality has been assigned.\r
///\r
#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED  BIT1\r
\r
///\r
/// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End\r
/// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.\r
///\r
#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED  BIT0\r
\r
//\r
// Define bits of Locality Control Register\r
//\r
\r
///\r
/// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4.\r
///\r
#define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT  BIT3\r
\r
///\r
/// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.\r
///\r
#define PTP_CRB_LOCALITY_CONTROL_SEIZE  BIT2\r
\r
///\r
/// Writes (1): The active Locality is done with the TPM.\r
///\r
#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH  BIT1\r
\r
///\r
/// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.\r
///\r
#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS  BIT0\r
\r
//\r
// Define bits of Locality Status Register\r
//\r
\r
///\r
/// 0: A higher locality has not initiated a Seize arbitration process.\r
/// 1: A higher locality has Seized the TPM from this locality.\r
///\r
#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED  BIT1\r
\r
///\r
/// 0: Locality has not been granted to the TPM.\r
/// 1: Locality has been granted access to the TPM\r
///\r
#define PTP_CRB_LOCALITY_STATUS_GRANTED  BIT0\r
\r
//\r
// Define bits of CRB Control Area Request Register\r
//\r
\r
///\r
/// Used by Software to indicate transition the TPM to and from the Idle state\r
/// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle\r
/// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.\r
/// TPM SHALL complete this transition within TIMEOUT_C.\r
///\r
#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE  BIT1\r
\r
///\r
/// Used by Software to request the TPM transition to the Ready State.\r
/// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command.\r
/// 0: Cleared to 0 by TPM to acknowledge the request.\r
/// TPM SHALL complete this transition within TIMEOUT_C.\r
///\r
#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY  BIT0\r
\r
//\r
// Define bits of CRB Control Area Status Register\r
//\r
\r
///\r
/// Used by TPM to indicate it is in the Idle State\r
/// 1: Set by TPM when in the Idle State\r
/// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.\r
/// SHALL be cleared by TIMEOUT_C.\r
///\r
#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE  BIT1\r
\r
///\r
/// Used by the TPM to indicate current status.\r
/// 1: Set by TPM to indicate a FATAL Error\r
/// 0: Indicates TPM is operational\r
///\r
#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS  BIT0\r
\r
//\r
// Define bits of CRB Control Cancel Register\r
//\r
\r
///\r
/// Used by software to cancel command processing Reads return correct value\r
/// Writes (0000 0001h): Cancel a command\r
/// Writes (0000 0000h): Clears field when command has been cancelled\r
///\r
#define PTP_CRB_CONTROL_CANCEL  BIT0\r
\r
//\r
// Define bits of CRB Control Start Register\r
//\r
\r
///\r
/// When set by software, indicates a command is ready for processing.\r
/// Writes (0000 0001h): TPM transitions to Command Execution\r
/// Writes (0000 0000h): TPM clears this field and transitions to Command Completion\r
///\r
#define PTP_CRB_CONTROL_START  BIT0\r
\r
//\r
// Restore original structure alignment\r
//\r
#pragma pack ()\r
\r
//\r
// Default TimeOut value\r
//\r
#define PTP_TIMEOUT_A  (750 * 1000)                // 750ms\r
#define PTP_TIMEOUT_B  (2000 * 1000)               // 2s\r
#define PTP_TIMEOUT_C  (200 * 1000)                // 200ms\r
#define PTP_TIMEOUT_D  (30 * 1000)                 // 30ms\r
\r
#endif\r
Commit	Line	Data
fb7abaca JY	1	/** @file\r
	2	Platform TPM Profile Specification definition for TPM2.0.\r
	3	It covers both FIFO and CRB interface.\r
	4	\r
714eedc5	5	Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
9344f092	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
fb7abaca JY	7	\r
	8	**/\r
	9	\r
	10	#ifndef _TPM_PTP_H_\r
	11	#define _TPM_PTP_H_\r
	12	\r
	13	//\r
	14	// PTP FIFO definition\r
	15	//\r
	16	\r
	17	//\r
	18	// Set structure alignment to 1-byte\r
	19	//\r
	20	#pragma pack (1)\r
	21	\r
	22	//\r
	23	// Register set map as specified in PTP specification Chapter 5\r
	24	//\r
	25	typedef struct {\r
	26	///\r
	27	/// Used to gain ownership for this particular port.\r
	28	///\r
2f88bd3a MK	29	UINT8 Access; // 0\r
2f88bd3a MK	30	UINT8 Reserved1[7]; // 1\r
fb7abaca JY	31	///\r
	32	/// Controls interrupts.\r
	33	///\r
2f88bd3a	34	UINT32 IntEnable; // 8\r
fb7abaca JY	35	///\r
	36	/// SIRQ vector to be used by the TPM.\r
	37	///\r
2f88bd3a MK	38	UINT8 IntVector; // 0ch\r
2f88bd3a MK	39	UINT8 Reserved2[3]; // 0dh\r
fb7abaca JY	40	///\r
	41	/// What caused interrupt.\r
	42	///\r
2f88bd3a	43	UINT32 IntSts; // 10h\r
fb7abaca JY	44	///\r
	45	/// Shows which interrupts are supported by that particular TPM.\r
	46	///\r
2f88bd3a	47	UINT32 InterfaceCapability; // 14h\r
fb7abaca JY	48	///\r
	49	/// Status Register. Provides status of the TPM.\r
	50	///\r
2f88bd3a	51	UINT8 Status; // 18h\r
fb7abaca JY	52	///\r
	53	/// Number of consecutive writes that can be done to the TPM.\r
	54	///\r
2f88bd3a	55	UINT16 BurstCount; // 19h\r
fb7abaca JY	56	///\r
	57	/// Additional Status Register.\r
	58	///\r
2f88bd3a MK	59	UINT8 StatusEx; // 1Bh\r
2f88bd3a MK	60	UINT8 Reserved3[8];\r
fb7abaca JY	61	///\r
	62	/// Read or write FIFO, depending on transaction.\r
	63	///\r
2f88bd3a MK	64	UINT32 DataFifo; // 24h\r
2f88bd3a MK	65	UINT8 Reserved4[8]; // 28h\r
fb7abaca JY	66	///\r
	67	/// Used to identify the Interface types supported by the TPM.\r
	68	///\r
2f88bd3a MK	69	UINT32 InterfaceId; // 30h\r
2f88bd3a MK	70	UINT8 Reserved5[0x4c]; // 34h\r
fb7abaca JY	71	///\r
	72	/// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)\r
	73	///\r
2f88bd3a MK	74	UINT32 XDataFifo; // 80h\r
2f88bd3a MK	75	UINT8 Reserved6[0xe7c]; // 84h\r
fb7abaca JY	76	///\r
	77	/// Vendor ID\r
	78	///\r
2f88bd3a	79	UINT16 Vid; // 0f00h\r
fb7abaca JY	80	///\r
	81	/// Device ID\r
	82	///\r
2f88bd3a	83	UINT16 Did; // 0f02h\r
fb7abaca JY	84	///\r
	85	/// Revision ID\r
	86	///\r
2f88bd3a MK	87	UINT8 Rid; // 0f04h\r
2f88bd3a MK	88	UINT8 Reserved[0xfb]; // 0f05h\r
fb7abaca JY	89	} PTP_FIFO_REGISTERS;\r
	90	\r
	91	//\r
	92	// Restore original structure alignment\r
	93	//\r
	94	#pragma pack ()\r
	95	\r
	96	//\r
	97	// Define pointer types used to access TIS registers on PC\r
	98	//\r
2f88bd3a	99	typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;\r
fb7abaca JY	100	\r
	101	//\r
	102	// Define bits of FIFO Interface Identifier Register\r
	103	//\r
	104	typedef union {\r
	105	struct {\r
2f88bd3a MK	106	UINT32 InterfaceType : 4;\r
	107	UINT32 InterfaceVersion : 4;\r
	108	UINT32 CapLocality : 1;\r
	109	UINT32 Reserved1 : 2;\r
	110	UINT32 CapDataXferSizeSupport : 2;\r
	111	UINT32 CapFIFO : 1;\r
	112	UINT32 CapCRB : 1;\r
	113	UINT32 CapIFRes : 2;\r
	114	UINT32 InterfaceSelector : 2;\r
	115	UINT32 IntfSelLock : 1;\r
	116	UINT32 Reserved2 : 4;\r
	117	UINT32 Reserved3 : 8;\r
fb7abaca	118	} Bits;\r
2f88bd3a	119	UINT32 Uint32;\r
fb7abaca JY	120	} PTP_FIFO_INTERFACE_IDENTIFIER;\r
	121	\r
	122	//\r
	123	// Define bits of FIFO Interface Capability Register\r
	124	//\r
	125	typedef union {\r
	126	struct {\r
2f88bd3a MK	127	UINT32 DataAvailIntSupport : 1;\r
	128	UINT32 StsValidIntSupport : 1;\r
	129	UINT32 LocalityChangeIntSupport : 1;\r
	130	UINT32 InterruptLevelHigh : 1;\r
	131	UINT32 InterruptLevelLow : 1;\r
	132	UINT32 InterruptEdgeRising : 1;\r
	133	UINT32 InterruptEdgeFalling : 1;\r
	134	UINT32 CommandReadyIntSupport : 1;\r
	135	UINT32 BurstCountStatic : 1;\r
	136	UINT32 DataTransferSizeSupport : 2;\r
	137	UINT32 Reserved : 17;\r
	138	UINT32 InterfaceVersion : 3;\r
	139	UINT32 Reserved2 : 1;\r
fb7abaca	140	} Bits;\r
2f88bd3a	141	UINT32 Uint32;\r
fb7abaca JY	142	} PTP_FIFO_INTERFACE_CAPABILITY;\r
	143	\r
	144	///\r
	145	/// InterfaceVersion\r
	146	///\r
	147	#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0\r
	148	#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2\r
	149	#define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3\r
	150	\r
fb7abaca JY	151	//\r
	152	// Define bits of ACCESS and STATUS registers\r
	153	//\r
	154	\r
	155	///\r
	156	/// This bit is a 1 to indicate that the other bits in this register are valid.\r
	157	///\r
2f88bd3a	158	#define PTP_FIFO_VALID BIT7\r
fb7abaca JY	159	///\r
	160	/// Indicate that this locality is active.\r
	161	///\r
2f88bd3a	162	#define PTP_FIFO_ACC_ACTIVE BIT5\r
fb7abaca JY	163	///\r
	164	/// Set to 1 to indicate that this locality had the TPM taken away while\r
	165	/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
	166	///\r
2f88bd3a	167	#define PTP_FIFO_ACC_SEIZED BIT4\r
fb7abaca JY	168	///\r
	169	/// Set to 1 to indicate that TPM MUST reset the\r
	170	/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
	171	/// locality that is writing this bit.\r
	172	///\r
2f88bd3a	173	#define PTP_FIFO_ACC_SEIZE BIT3\r
fb7abaca JY	174	///\r
	175	/// When this bit is 1, another locality is requesting usage of the TPM.\r
	176	///\r
2f88bd3a	177	#define PTP_FIFO_ACC_PENDIND BIT2\r
fb7abaca JY	178	///\r
	179	/// Set to 1 to indicate that this locality is requesting to use TPM.\r
	180	///\r
2f88bd3a	181	#define PTP_FIFO_ACC_RQUUSE BIT1\r
fb7abaca JY	182	///\r
	183	/// A value of 1 indicates that a T/OS has not been established on the platform\r
	184	///\r
2f88bd3a	185	#define PTP_FIFO_ACC_ESTABLISH BIT0\r
fb7abaca JY	186	\r
	187	///\r
	188	/// This field indicates that STS_DATA and STS_EXPECT are valid\r
	189	///\r
2f88bd3a	190	#define PTP_FIFO_STS_VALID BIT7\r
fb7abaca JY	191	///\r
	192	/// When this bit is 1, TPM is in the Ready state,\r
	193	/// indicating it is ready to receive a new command.\r
	194	///\r
2f88bd3a	195	#define PTP_FIFO_STS_READY BIT6\r
fb7abaca JY	196	///\r
	197	/// Write a 1 to this bit to cause the TPM to execute that command.\r
	198	///\r
2f88bd3a	199	#define PTP_FIFO_STS_GO BIT5\r
fb7abaca JY	200	///\r
	201	/// This bit indicates that the TPM has data available as a response.\r
	202	///\r
2f88bd3a	203	#define PTP_FIFO_STS_DATA BIT4\r
fb7abaca JY	204	///\r
	205	/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
	206	///\r
2f88bd3a	207	#define PTP_FIFO_STS_EXPECT BIT3\r
fb7abaca JY	208	///\r
	209	/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
	210	///\r
2f88bd3a	211	#define PTP_FIFO_STS_SELFTEST_DONE BIT2\r
fb7abaca JY	212	///\r
	213	/// Writes a 1 to this bit to force the TPM to re-send the response.\r
	214	///\r
2f88bd3a	215	#define PTP_FIFO_STS_RETRY BIT1\r
fb7abaca JY	216	\r
	217	///\r
	218	/// TPM Family Identifier.\r
	219	/// 00: TPM 1.2 Family\r
	220	/// 01: TPM 2.0 Family\r
	221	///\r
2f88bd3a MK	222	#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 \| BIT3)\r
	223	#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)\r
	224	#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)\r
	225	#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)\r
fb7abaca JY	226	///\r
	227	/// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.\r
	228	/// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.\r
	229	///\r
2f88bd3a	230	#define PTP_FIFO_STS_EX_CANCEL BIT0\r
fb7abaca JY	231	\r
	232	//\r
	233	// PTP CRB definition\r
	234	//\r
	235	\r
	236	//\r
	237	// Set structure alignment to 1-byte\r
	238	//\r
	239	#pragma pack (1)\r
	240	\r
	241	//\r
	242	// Register set map as specified in PTP specification Chapter 5\r
	243	//\r
	244	typedef struct {\r
	245	///\r
	246	/// Used to determine current state of Locality of the TPM.\r
	247	///\r
2f88bd3a MK	248	UINT32 LocalityState; // 0\r
2f88bd3a MK	249	UINT8 Reserved1[4]; // 4\r
fb7abaca JY	250	///\r
	251	/// Used to gain control of the TPM by this Locality.\r
	252	///\r
2f88bd3a	253	UINT32 LocalityControl; // 8\r
fb7abaca JY	254	///\r
	255	/// Used to determine whether Locality has been granted or Seized.\r
	256	///\r
2f88bd3a MK	257	UINT32 LocalityStatus; // 0ch\r
2f88bd3a MK	258	UINT8 Reserved2[0x20]; // 10h\r
fb7abaca JY	259	///\r
	260	/// Used to identify the Interface types supported by the TPM.\r
	261	///\r
2f88bd3a	262	UINT32 InterfaceId; // 30h\r
fb7abaca JY	263	///\r
	264	/// Vendor ID\r
	265	///\r
2f88bd3a	266	UINT16 Vid; // 34h\r
fb7abaca JY	267	///\r
	268	/// Device ID\r
	269	///\r
2f88bd3a	270	UINT16 Did; // 36h\r
fb7abaca JY	271	///\r
	272	/// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.\r
	273	///\r
2f88bd3a	274	UINT64 CrbControlExtension; // 38h\r
fb7abaca JY	275	///\r
	276	/// Register used to initiate transactions for the CRB interface.\r
	277	///\r
2f88bd3a	278	UINT32 CrbControlRequest; // 40h\r
fb7abaca JY	279	///\r
	280	/// Register used by the TPM to provide status of the CRB interface.\r
	281	///\r
2f88bd3a	282	UINT32 CrbControlStatus; // 44h\r
fb7abaca JY	283	///\r
	284	/// Register used by software to cancel command processing.\r
	285	///\r
2f88bd3a	286	UINT32 CrbControlCancel; // 48h\r
fb7abaca JY	287	///\r
	288	/// Register used to indicate presence of command or response data in the CRB buffer.\r
	289	///\r
2f88bd3a	290	UINT32 CrbControlStart; // 4Ch\r
fb7abaca JY	291	///\r
	292	/// Register used to configure and respond to interrupts.\r
	293	///\r
2f88bd3a MK	294	UINT32 CrbInterruptEnable; // 50h\r
2f88bd3a MK	295	UINT32 CrbInterruptStatus; // 54h\r
fb7abaca JY	296	///\r
	297	/// Size of the Command buffer.\r
	298	///\r
2f88bd3a	299	UINT32 CrbControlCommandSize; // 58h\r
fb7abaca JY	300	///\r
	301	/// Command buffer start address\r
	302	///\r
2f88bd3a MK	303	UINT32 CrbControlCommandAddressLow; // 5Ch\r
2f88bd3a MK	304	UINT32 CrbControlCommandAddressHigh; // 60h\r
fb7abaca JY	305	///\r
	306	/// Size of the Response buffer\r
	307	///\r
2f88bd3a	308	UINT32 CrbControlResponseSize; // 64h\r
fb7abaca JY	309	///\r
	310	/// Address of the start of the Response buffer\r
	311	///\r
2f88bd3a MK	312	UINT64 CrbControlResponseAddrss; // 68h\r
2f88bd3a MK	313	UINT8 Reserved4[0x10]; // 70h\r
fb7abaca JY	314	///\r
	315	/// Command/Response Data may be defined as large as 3968 (0xF80).\r
	316	///\r
2f88bd3a	317	UINT8 CrbDataBuffer[0xF80]; // 80h\r
fb7abaca JY	318	} PTP_CRB_REGISTERS;\r
	319	\r
	320	//\r
	321	// Define pointer types used to access CRB registers on PTP\r
	322	//\r
2f88bd3a	323	typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;\r
fb7abaca JY	324	\r
	325	//\r
	326	// Define bits of CRB Interface Identifier Register\r
	327	//\r
	328	typedef union {\r
	329	struct {\r
2f88bd3a MK	330	UINT32 InterfaceType : 4;\r
	331	UINT32 InterfaceVersion : 4;\r
	332	UINT32 CapLocality : 1;\r
	333	UINT32 CapCRBIdleBypass : 1;\r
	334	UINT32 Reserved1 : 1;\r
	335	UINT32 CapDataXferSizeSupport : 2;\r
	336	UINT32 CapFIFO : 1;\r
	337	UINT32 CapCRB : 1;\r
	338	UINT32 CapIFRes : 2;\r
	339	UINT32 InterfaceSelector : 2;\r
	340	UINT32 IntfSelLock : 1;\r
	341	UINT32 Reserved2 : 4;\r
	342	UINT32 Rid : 8;\r
fb7abaca	343	} Bits;\r
2f88bd3a	344	UINT32 Uint32;\r
fb7abaca JY	345	} PTP_CRB_INTERFACE_IDENTIFIER;\r
	346	\r
	347	///\r
	348	/// InterfaceType\r
	349	///\r
	350	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0\r
	351	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB 0x1\r
	352	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS 0xF\r
	353	\r
	354	///\r
	355	/// InterfaceVersion\r
	356	///\r
	357	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0\r
	358	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB 0x1\r
	359	\r
	360	///\r
	361	/// InterfaceSelector\r
	362	///\r
	363	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0\r
	364	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1\r
	365	\r
	366	//\r
	367	// Define bits of Locality State Register\r
	368	//\r
	369	\r
	370	///\r
	371	/// This bit indicates whether all other bits of this register contain valid values, if it is a 1.\r
	372	///\r
2f88bd3a	373	#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7\r
fb7abaca JY	374	\r
	375	///\r
	376	/// 000 - Locality 0\r
	377	/// 001 - Locality 1\r
	378	/// 010 - Locality 2\r
	379	/// 011 - Locality 3\r
	380	/// 100 - Locality 4\r
	381	///\r
2f88bd3a MK	382	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 \| BIT3 \| BIT4)\r
	383	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)\r
	384	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)\r
	385	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)\r
	386	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 \| BIT3)\r
	387	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)\r
fb7abaca JY	388	\r
	389	///\r
	390	/// A 0 indicates to the host that no locality is assigned.\r
	391	/// A 1 indicates a locality has been assigned.\r
	392	///\r
2f88bd3a	393	#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1\r
fb7abaca JY	394	\r
	395	///\r
	396	/// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End\r
	397	/// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.\r
	398	///\r
2f88bd3a	399	#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0\r
fb7abaca JY	400	\r
	401	//\r
	402	// Define bits of Locality Control Register\r
	403	//\r
	404	\r
	405	///\r
	406	/// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4.\r
	407	///\r
	408	#define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3\r
	409	\r
	410	///\r
	411	/// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.\r
	412	///\r
2f88bd3a	413	#define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2\r
fb7abaca JY	414	\r
	415	///\r
	416	/// Writes (1): The active Locality is done with the TPM.\r
	417	///\r
2f88bd3a	418	#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1\r
fb7abaca JY	419	\r
	420	///\r
	421	/// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.\r
	422	///\r
2f88bd3a	423	#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0\r
fb7abaca JY	424	\r
	425	//\r
	426	// Define bits of Locality Status Register\r
	427	//\r
	428	\r
	429	///\r
	430	/// 0: A higher locality has not initiated a Seize arbitration process.\r
	431	/// 1: A higher locality has Seized the TPM from this locality.\r
	432	///\r
2f88bd3a	433	#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1\r
fb7abaca JY	434	\r
	435	///\r
	436	/// 0: Locality has not been granted to the TPM.\r
	437	/// 1: Locality has been granted access to the TPM\r
	438	///\r
2f88bd3a	439	#define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0\r
fb7abaca JY	440	\r
	441	//\r
	442	// Define bits of CRB Control Area Request Register\r
	443	//\r
	444	\r
	445	///\r
	446	/// Used by Software to indicate transition the TPM to and from the Idle state\r
	447	/// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle\r
	448	/// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.\r
	449	/// TPM SHALL complete this transition within TIMEOUT_C.\r
	450	///\r
2f88bd3a	451	#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1\r
fb7abaca JY	452	\r
	453	///\r
	454	/// Used by Software to request the TPM transition to the Ready State.\r
	455	/// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command.\r
	456	/// 0: Cleared to 0 by TPM to acknowledge the request.\r
	457	/// TPM SHALL complete this transition within TIMEOUT_C.\r
	458	///\r
2f88bd3a	459	#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0\r
fb7abaca JY	460	\r
	461	//\r
	462	// Define bits of CRB Control Area Status Register\r
	463	//\r
	464	\r
	465	///\r
	466	/// Used by TPM to indicate it is in the Idle State\r
	467	/// 1: Set by TPM when in the Idle State\r
	468	/// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.\r
	469	/// SHALL be cleared by TIMEOUT_C.\r
	470	///\r
2f88bd3a	471	#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1\r
fb7abaca JY	472	\r
	473	///\r
	474	/// Used by the TPM to indicate current status.\r
	475	/// 1: Set by TPM to indicate a FATAL Error\r
	476	/// 0: Indicates TPM is operational\r
	477	///\r
2f88bd3a	478	#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0\r
fb7abaca JY	479	\r
	480	//\r
	481	// Define bits of CRB Control Cancel Register\r
	482	//\r
	483	\r
	484	///\r
	485	/// Used by software to cancel command processing Reads return correct value\r
	486	/// Writes (0000 0001h): Cancel a command\r
	487	/// Writes (0000 0000h): Clears field when command has been cancelled\r
	488	///\r
2f88bd3a	489	#define PTP_CRB_CONTROL_CANCEL BIT0\r
fb7abaca JY	490	\r
	491	//\r
	492	// Define bits of CRB Control Start Register\r
	493	//\r
	494	\r
	495	///\r
	496	/// When set by software, indicates a command is ready for processing.\r
	497	/// Writes (0000 0001h): TPM transitions to Command Execution\r
	498	/// Writes (0000 0000h): TPM clears this field and transitions to Command Completion\r
	499	///\r
2f88bd3a	500	#define PTP_CRB_CONTROL_START BIT0\r
fb7abaca JY	501	\r
	502	//\r
	503	// Restore original structure alignment\r
	504	//\r
	505	#pragma pack ()\r
	506	\r
	507	//\r
	508	// Default TimeOut value\r
	509	//\r
2f88bd3a MK	510	#define PTP_TIMEOUT_A (750 * 1000) // 750ms\r
	511	#define PTP_TIMEOUT_B (2000 * 1000) // 2s\r
	512	#define PTP_TIMEOUT_C (200 * 1000) // 200ms\r
	513	#define PTP_TIMEOUT_D (30 * 1000) // 30ms\r
fb7abaca	514	\r
9095d37b	515	#endif\r