[mirror_edk2.git] / MdePkg / Include / IndustryStandard / TpmTis.h

/** @file\r
  TPM Interface Specification definition.\r
  It covers both TPM1.2 and TPM2.0.\r
\r
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _TPM_TIS_H_\r
#define _TPM_TIS_H_\r
\r
//\r
// Set structure alignment to 1-byte\r
//\r
#pragma pack (1)\r
\r
//\r
// Register set map as specified in TIS specification Chapter 10\r
//\r
typedef struct {\r
  ///\r
  /// Used to gain ownership for this particular port.\r
  ///\r
  UINT8                             Access;             // 0\r
  UINT8                             Reserved1[7];       // 1\r
  ///\r
  /// Controls interrupts.\r
  ///\r
  UINT32                            IntEnable;          // 8\r
  ///\r
  /// SIRQ vector to be used by the TPM.\r
  ///\r
  UINT8                             IntVector;          // 0ch\r
  UINT8                             Reserved2[3];       // 0dh\r
  ///\r
  /// What caused interrupt.\r
  ///\r
  UINT32                            IntSts;             // 10h\r
  ///\r
  /// Shows which interrupts are supported by that particular TPM.\r
  ///\r
  UINT32                            IntfCapability;     // 14h\r
  ///\r
  /// Status Register. Provides status of the TPM.\r
  ///\r
  UINT8                             Status;             // 18h\r
  ///\r
  /// Number of consecutive writes that can be done to the TPM.\r
  ///\r
  UINT16                            BurstCount;         // 19h\r
  UINT8                             Reserved3[9];\r
  ///\r
  /// Read or write FIFO, depending on transaction.\r
  ///\r
  UINT32                            DataFifo;           // 24h\r
  UINT8                             Reserved4[0xed8];   // 28h\r
  ///\r
  /// Vendor ID\r
  ///\r
  UINT16                            Vid;                // 0f00h\r
  ///\r
  /// Device ID\r
  ///\r
  UINT16                            Did;                // 0f02h\r
  ///\r
  /// Revision ID\r
  ///\r
  UINT8                             Rid;                // 0f04h\r
  UINT8                             Reserved[0x7b];     // 0f05h\r
  ///\r
  /// Alias to I/O legacy space.\r
  ///\r
  UINT32                            LegacyAddress1;     // 0f80h\r
  ///\r
  /// Additional 8 bits for I/O legacy space extension.\r
  ///\r
  UINT32                            LegacyAddress1Ex;   // 0f84h\r
  ///\r
  /// Alias to second I/O legacy space.\r
  ///\r
  UINT32                            LegacyAddress2;     // 0f88h\r
  ///\r
  /// Additional 8 bits for second I/O legacy space extension.\r
  ///\r
  UINT32                            LegacyAddress2Ex;   // 0f8ch\r
  ///\r
  /// Vendor-defined configuration registers.\r
  ///\r
  UINT8                             VendorDefined[0x70];// 0f90h\r
} TIS_PC_REGISTERS;\r
\r
//\r
// Restore original structure alignment\r
//\r
#pragma pack ()\r
\r
//\r
// Define pointer types used to access TIS registers on PC\r
//\r
typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;\r
\r
//\r
// Define bits of ACCESS and STATUS registers\r
//\r
\r
///\r
/// This bit is a 1 to indicate that the other bits in this register are valid.\r
///\r
#define TIS_PC_VALID                BIT7\r
///\r
/// Indicate that this locality is active.\r
///\r
#define TIS_PC_ACC_ACTIVE           BIT5\r
///\r
/// Set to 1 to indicate that this locality had the TPM taken away while\r
/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
///\r
#define TIS_PC_ACC_SEIZED           BIT4\r
///\r
/// Set to 1 to indicate that TPM MUST reset the\r
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
/// locality that is writing this bit.\r
///\r
#define TIS_PC_ACC_SEIZE            BIT3\r
///\r
/// When this bit is 1, another locality is requesting usage of the TPM.\r
///\r
#define TIS_PC_ACC_PENDIND          BIT2\r
///\r
/// Set to 1 to indicate that this locality is requesting to use TPM.\r
///\r
#define TIS_PC_ACC_RQUUSE           BIT1\r
///\r
/// A value of 1 indicates that a T/OS has not been established on the platform\r
///\r
#define TIS_PC_ACC_ESTABLISH        BIT0\r
\r
///\r
/// Write a 1 to this bit to notify TPM to cancel currently executing command\r
///\r
#define TIS_PC_STS_CANCEL           BIT24\r
///\r
/// This field indicates that STS_DATA and STS_EXPECT are valid\r
///\r
#define TIS_PC_STS_VALID            BIT7\r
///\r
/// When this bit is 1, TPM is in the Ready state,\r
/// indicating it is ready to receive a new command.\r
///\r
#define TIS_PC_STS_READY            BIT6\r
///\r
/// Write a 1 to this bit to cause the TPM to execute that command.\r
///\r
#define TIS_PC_STS_GO               BIT5\r
///\r
/// This bit indicates that the TPM has data available as a response.\r
///\r
#define TIS_PC_STS_DATA             BIT4\r
///\r
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
///\r
#define TIS_PC_STS_EXPECT           BIT3\r
///\r
/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
///\r
#define TIS_PC_STS_SELFTEST_DONE    BIT2\r
///\r
/// Writes a 1 to this bit to force the TPM to re-send the response.\r
///\r
#define TIS_PC_STS_RETRY            BIT1\r
\r
//\r
// Default TimeOut value\r
//\r
#define TIS_TIMEOUT_A               (750  * 1000)  // 750ms\r
#define TIS_TIMEOUT_B               (2000 * 1000)  // 2s\r
#define TIS_TIMEOUT_C               (750  * 1000)  // 750ms\r
#define TIS_TIMEOUT_D               (750  * 1000)  // 750ms\r
\r
#endif\r
Commit	Line	Data
ac6f9d7c JY	1	/** @file\r
	2	TPM Interface Specification definition.\r
	3	It covers both TPM1.2 and TPM2.0.\r
	4	\r
11cf02f6	5	Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
ac6f9d7c JY	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef _TPM_TIS_H_\r
	17	#define _TPM_TIS_H_\r
	18	\r
	19	//\r
	20	// Set structure alignment to 1-byte\r
	21	//\r
	22	#pragma pack (1)\r
	23	\r
	24	//\r
	25	// Register set map as specified in TIS specification Chapter 10\r
	26	//\r
	27	typedef struct {\r
	28	///\r
	29	/// Used to gain ownership for this particular port.\r
	30	///\r
	31	UINT8 Access; // 0\r
	32	UINT8 Reserved1[7]; // 1\r
	33	///\r
	34	/// Controls interrupts.\r
	35	///\r
	36	UINT32 IntEnable; // 8\r
	37	///\r
	38	/// SIRQ vector to be used by the TPM.\r
	39	///\r
	40	UINT8 IntVector; // 0ch\r
	41	UINT8 Reserved2[3]; // 0dh\r
	42	///\r
	43	/// What caused interrupt.\r
	44	///\r
	45	UINT32 IntSts; // 10h\r
	46	///\r
	47	/// Shows which interrupts are supported by that particular TPM.\r
	48	///\r
	49	UINT32 IntfCapability; // 14h\r
	50	///\r
	51	/// Status Register. Provides status of the TPM.\r
	52	///\r
	53	UINT8 Status; // 18h\r
	54	///\r
	55	/// Number of consecutive writes that can be done to the TPM.\r
	56	///\r
	57	UINT16 BurstCount; // 19h\r
	58	UINT8 Reserved3[9];\r
	59	///\r
	60	/// Read or write FIFO, depending on transaction.\r
	61	///\r
	62	UINT32 DataFifo; // 24h\r
	63	UINT8 Reserved4[0xed8]; // 28h\r
	64	///\r
	65	/// Vendor ID\r
	66	///\r
	67	UINT16 Vid; // 0f00h\r
	68	///\r
	69	/// Device ID\r
70	///\r
71	UINT16 Did; // 0f02h\r
72	///\r
73	/// Revision ID\r
74	///\r
75	UINT8 Rid; // 0f04h\r
76	UINT8 Reserved[0x7b]; // 0f05h\r
77	///\r
78	/// Alias to I/O legacy space.\r
79	///\r
80	UINT32 LegacyAddress1; // 0f80h\r
81	///\r
82	/// Additional 8 bits for I/O legacy space extension.\r
83	///\r
84	UINT32 LegacyAddress1Ex; // 0f84h\r
85	///\r
86	/// Alias to second I/O legacy space.\r
87	///\r
88	UINT32 LegacyAddress2; // 0f88h\r
89	///\r
90	/// Additional 8 bits for second I/O legacy space extension.\r
91	///\r
92	UINT32 LegacyAddress2Ex; // 0f8ch\r
93	///\r
94	/// Vendor-defined configuration registers.\r
95	///\r
96	UINT8 VendorDefined[0x70];// 0f90h\r
97	} TIS_PC_REGISTERS;\r
98	\r
99	//\r
100	// Restore original structure alignment\r
101	//\r
102	#pragma pack ()\r
103	\r
104	//\r
105	// Define pointer types used to access TIS registers on PC\r
106	//\r
107	typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
108	\r
109	//\r
110	// Define bits of ACCESS and STATUS registers\r
111	//\r
112	\r
113	///\r
114	/// This bit is a 1 to indicate that the other bits in this register are valid.\r
115	///\r
116	#define TIS_PC_VALID BIT7\r
117	///\r
118	/// Indicate that this locality is active.\r
119	///\r
120	#define TIS_PC_ACC_ACTIVE BIT5\r
121	///\r
122	/// Set to 1 to indicate that this locality had the TPM taken away while\r
123	/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
124	///\r
125	#define TIS_PC_ACC_SEIZED BIT4\r
126	///\r
127	/// Set to 1 to indicate that TPM MUST reset the\r
128	/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
129	/// locality that is writing this bit.\r
130	///\r
131	#define TIS_PC_ACC_SEIZE BIT3\r
132	///\r
133	/// When this bit is 1, another locality is requesting usage of the TPM.\r
134	///\r
135	#define TIS_PC_ACC_PENDIND BIT2\r
136	///\r
137	/// Set to 1 to indicate that this locality is requesting to use TPM.\r
138	///\r
139	#define TIS_PC_ACC_RQUUSE BIT1\r
140	///\r
141	/// A value of 1 indicates that a T/OS has not been established on the platform\r
142	///\r
143	#define TIS_PC_ACC_ESTABLISH BIT0\r
144	\r
11cf02f6 ZC	145	///\r
	146	/// Write a 1 to this bit to notify TPM to cancel currently executing command\r
	147	///\r
	148	#define TIS_PC_STS_CANCEL BIT24\r
ac6f9d7c JY	149	///\r
	150	/// This field indicates that STS_DATA and STS_EXPECT are valid\r
	151	///\r
	152	#define TIS_PC_STS_VALID BIT7\r
	153	///\r
	154	/// When this bit is 1, TPM is in the Ready state,\r
	155	/// indicating it is ready to receive a new command.\r
	156	///\r
	157	#define TIS_PC_STS_READY BIT6\r
	158	///\r
	159	/// Write a 1 to this bit to cause the TPM to execute that command.\r
	160	///\r
	161	#define TIS_PC_STS_GO BIT5\r
	162	///\r
	163	/// This bit indicates that the TPM has data available as a response.\r
	164	///\r
	165	#define TIS_PC_STS_DATA BIT4\r
	166	///\r
	167	/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
	168	///\r
	169	#define TIS_PC_STS_EXPECT BIT3\r
	170	///\r
	171	/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
	172	///\r
	173	#define TIS_PC_STS_SELFTEST_DONE BIT2\r
	174	///\r
	175	/// Writes a 1 to this bit to force the TPM to re-send the response.\r
	176	///\r
	177	#define TIS_PC_STS_RETRY BIT1\r
	178	\r
	179	//\r
	180	// Default TimeOut value\r
	181	//\r
	182	#define TIS_TIMEOUT_A (750 * 1000) // 750ms\r
	183	#define TIS_TIMEOUT_B (2000 * 1000) // 2s\r
	184	#define TIS_TIMEOUT_C (750 * 1000) // 750ms\r
	185	#define TIS_TIMEOUT_D (750 * 1000) // 750ms\r
	186	\r
11cf02f6	187	#endif\r