Import Pal.h and Sal.h.
[mirror_edk2.git] / MdePkg / Include / Ipf / Pal.h
CommitLineData
959ccb23 1/** @file\r
2 Main PAL API's defined in IPF PAL Spec.\r
3\r
4 Copyright (c) 2006 - 2007, Intel Corporation\r
5 All rights reserved. This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13 Module Name: PalApi.h\r
14\r
15**/\r
16\r
17#ifndef __PAL_API_H__\r
18#define __PAL_API_H__\r
19\r
20//\r
21// IPF Specific Functions\r
22//\r
23\r
24typedef struct {\r
25 UINT64 Status;\r
26 UINT64 r9;\r
27 UINT64 r10;\r
28 UINT64 r11;\r
29} PAL_CALL_RETURN;\r
30\r
d1f95000 31\r
32\r
33//\r
34// CacheType of PAL_CACHE_FLUSH.\r
35//\r
36#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r
37#define PAL_CACHE_FLUSH_DATA_ALL 2\r
38#define PAL_CACHE_FLUSH_ALL 3\r
39#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r
40\r
41\r
42//\r
43// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
44// \r
45#define PAL_CACHE_FLUSH_INVIDED_LINES BIT0\r
46#define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1\r
47\r
48/**\r
49 \r
50 Flush the instruction or data caches. It is required by IPF.\r
51 The PAL procedure supports the Static Registers calling\r
52 convention. It could be called at virtual mode and physical\r
53 mode.\r
54\r
55 @param Index Index of PAL_CACHE_FLUSH within the\r
56 list of PAL procedures.\r
57 \r
58 @param CacheType Unsigned 64-bit integer indicating\r
59 which cache to flush.\r
60\r
61 @param Operation Formatted bit vector indicating the\r
62 operation of this call.\r
63\r
64 @param ProgressIndicator Unsigned 64-bit integer specifying\r
65 the starting position of the flush\r
66 operation.\r
67 \r
68 @return R9 Unsigned 64-bit integer specifying the vector\r
69 number of the pending interrupt.\r
70 \r
71 @return R10 Unsigned 64-bit integer specifying the\r
72 starting position of the flush operation.\r
73 \r
74 @return R11 Unsigned 64-bit integer specifying the vector\r
75 number of the pending interrupt.\r
76 \r
77 @return Status 2 - Call completed without error, but a PMI\r
78 was taken during the execution of this\r
79 procedure.\r
80\r
81 @return Status 1 - Call has not completed flushing due to\r
82 a pending interrupt.\r
83\r
84 @return Status 0 - Call completed without error\r
85\r
86 @return Status -2 - Invalid argument\r
87\r
88 @return Status -3 - Call completed with error\r
89 \r
90**/\r
91#define PAL_CACHE_FLUSH 1\r
92\r
93\r
94//\r
95// Attributes of PAL_CACHE_CONFIG_INFO1\r
96// \r
97#define PAL_CACHE_ATTR_WT 0\r
98#define PAL_CACHE_ATTR_WB 1\r
99\r
100//\r
101// PAL_CACHE_CONFIG_INFO1.StoreHint\r
102// \r
103#define PAL_CACHE_STORE_TEMPORAL 0\r
104#define PAL_CACHE_STORE_NONE_TEMPORAL 3\r
105\r
106//\r
107// PAL_CACHE_CONFIG_INFO1.StoreHint\r
108// \r
109#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r
110#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r
111\r
112//\r
113// PAL_CACHE_CONFIG_INFO1.StoreHint\r
114// \r
115#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r
116#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r
117#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r
118\r
119//\r
120// Detail the characteristics of a given processor controlled\r
121// cache in the cache hierarchy.\r
122// \r
123typedef struct {\r
124 UINT64 IsUnified : 1;\r
125 UINT64 Attributes : 2;\r
126 UINT64 Associativity:8;\r
127 UINT64 LineSize:8;\r
128 UINT64 Stride:8;\r
129 UINT64 StoreLatency:8;\r
130 UINT64 StoreHint:8;\r
131 UINT64 LoadHint:8;\r
132} PAL_CACHE_INFO_RETURN1;\r
133\r
134//\r
135// Detail the characteristics of a given processor controlled\r
136// cache in the cache hierarchy.\r
137// \r
138typedef struct {\r
139 UINT64 CacheSize:32;\r
140 UINT64 AliasBoundary:8;\r
141 UINT64 TagLsBits:8;\r
142 UINT64 TagMsBits:8;\r
143} PAL_CACHE_INFO_RETURN2;\r
144\r
145/**\r
146 \r
147 Return detailed instruction or data cache information. It is\r
148 required by IPF. The PAL procedure supports the Static\r
149 Registers calling convention. It could be called at virtual\r
150 mode and physical mode.\r
151 \r
152 @param Index Index of PAL_CACHE_INFO within the list of\r
153 PAL procedures.\r
154 \r
155 @param CacheLevel Unsigned 64-bit integer specifying the\r
156 level in the cache hierarchy for which\r
157 information is requested. This value must\r
158 be between 0 and one less than the value\r
159 returned in the cache_levels return value\r
160 from PAL_CACHE_SUMMARY.\r
161 \r
162 @param CacheType Unsigned 64-bit integer with a value of 1\r
163 for instruction cache and 2 for data or\r
164 unified cache. All other values are\r
165 reserved.\r
166 \r
167 @param Reserved Should be 0.\r
168 \r
169 \r
170 @return R9 Detail the characteristics of a given\r
171 processor controlled cache in the cache\r
172 hierarchy. See PAL_CACHE_INFO_RETURN1.\r
173 \r
174 @return R10 Detail the characteristics of a given\r
175 processor controlled cache in the cache\r
176 hierarchy. See PAL_CACHE_INFO_RETURN2.\r
177 \r
178 @return R11 Reserved with 0.\r
179 \r
180 \r
181 @return Status 0 - Call completed without error\r
182\r
183 @return Status -2 - Invalid argument\r
184\r
185 @return Status -3 - Call completed with error\r
186 \r
187**/\r
188#define PAL_CACHE_INFO 2\r
189\r
190\r
191\r
192//\r
193// Level of PAL_CACHE_INIT.\r
194// \r
195#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r
196\r
197//\r
198// Restrict of PAL_CACHE_INIT.\r
199// \r
200#define PAL_CACHE_INIT_NO_RESTRICT 0\r
201#define PAL_CACHE_INIT_RESTRICTED 1\r
202\r
203/**\r
204 \r
205 Initialize the instruction or data caches. It is required by\r
206 IPF. The PAL procedure supports the Static Registers calling\r
207 convention. It could be called at physical mode.\r
208\r
209 @param Index Index of PAL_CACHE_INIT within the list of PAL\r
210 procedures.\r
211 \r
212 @param Level Unsigned 64-bit integer containing the level of\r
213 cache to initialize. If the cache level can be\r
214 initialized independently, only that level will\r
215 be initialized. Otherwise\r
216 implementation-dependent side-effects will\r
217 occur.\r
218 \r
219 @param CacheType Unsigned 64-bit integer with a value of 1 to\r
220 initialize the instruction cache, 2 to\r
221 initialize the data cache, or 3 to\r
222 initialize both. All other values are\r
223 reserved.\r
224\r
225 @param Restrict Unsigned 64-bit integer with a value of 0 or\r
226 1. All other values are reserved. If\r
227 restrict is 1 and initializing the specified\r
228 level and cache_type of the cache would\r
229 cause side-effects, PAL_CACHE_INIT will\r
230 return -4 instead of initializing the cache.\r
231 \r
232 \r
233 @return Status 0 - Call completed without error\r
234\r
235 @return Status -2 - Invalid argument\r
236\r
237 @return Status -3 - Call completed with error.\r
238 \r
239 @return Status -4 - Call could not initialize the specified\r
240 level and cache_type of the cache without\r
241 side-effects and restrict was 1. \r
242 \r
243**/\r
244#define PAL_CACHE_INIT 3 \r
245\r
246\r
247//\r
248// PAL_CACHE_PROTECTION.Method.\r
249// \r
250#define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r
251#define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r
252#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r
253#define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r
254\r
255\r
256\r
257//\r
258// PAL_CACHE_PROTECTION.TagOrData.\r
259// \r
260#define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r
261#define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r
262#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r
263#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r
264\r
265//\r
266// 32-bit protection information structures.\r
267// \r
268typedef struct {\r
269 UINT32 DataBits:8;\r
270 UINT32 TagProtLsb:6;\r
271 UINT32 TagProtMsb:6;\r
272 UINT32 ProtBits:6;\r
273 UINT32 Method:4;\r
274 UINT32 TagOrData:2;\r
275} PAL_CACHE_PROTECTION;\r
276\r
277/**\r
278 \r
279 Return instruction or data cache protection information. It is\r
280 required by IPF. The PAL procedure supports the Static\r
281 Registers calling convention. It could be called at physical\r
282 mode and Virtual mode.\r
283\r
284 @param Index Index of PAL_CACHE_PROT_INFO within the list of\r
285 PAL procedures.\r
286\r
287 @param CacheLevel Unsigned 64-bit integer specifying the level\r
288 in the cache hierarchy for which information\r
289 is requested. This value must be between 0\r
290 and one less than the value returned in the\r
291 cache_levels return value from\r
292 PAL_CACHE_SUMMARY.\r
293\r
294 @param CacheType Unsigned 64-bit integer with a value of 1\r
295 for instruction cache and 2 for data or\r
296 unified cache. All other values are\r
297 reserved.\r
298 \r
299 @return R9 Detail the characteristics of a given\r
300 processor controlled cache in the cache\r
301 hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
302 \r
303 @return R10 Detail the characteristics of a given\r
304 processor controlled cache in the cache\r
305 hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
306 \r
307 @return R11 Detail the characteristics of a given\r
308 processor controlled cache in the cache\r
309 hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
310 \r
311 \r
312 @return Status 0 - Call completed without error\r
313\r
314 @return Status -2 - Invalid argument\r
315\r
316 @return Status -3 - Call completed with error.\r
317 \r
318**/\r
319#define PAL_CACHE_PROT_INFO 38\r
320\r
321\r
322\r
323\r
324\r
325\r
326\r
327///\r
328// ?????????\r
329\r
330\r
331\r
332/**\r
333 \r
334 Returns information on which logical processors share caches.\r
335 It is optional.\r
336\r
337 @param CallingConvention Static Registers\r
338\r
339 @param Mode Physical/Virtual\r
340 \r
341**/\r
342#define PAL_CACHE_SHARED_INFO 43\r
343\r
344\r
345/**\r
346 \r
347 Return a summary of the cache hierarchy. It is required by\r
348 IPF.\r
349\r
350 @param CallingConvention Static Registers\r
351\r
352 @param Mode Physical/Virtual\r
353 \r
354**/\r
355#define PAL_CACHE_SUMMARY 4\r
356\r
357/**\r
358 \r
359 Return a list of supported memory attributes.. It is required\r
360 by IPF.\r
361\r
362 @param CallingConvention Static Registers\r
363\r
364 @param Mode Physical/Virtual\r
365 \r
366**/\r
367#define PAL_MEM_ATTRIB 5\r
368\r
369/**\r
370 \r
371 Used in architected sequence to transition pages from a\r
372 cacheable, speculative attribute to an uncacheable attribute.\r
373 It is required by IPF.\r
374\r
375 @param CallingConvention Static Registers\r
376\r
377 @param Mode Physical/Virtual\r
378 \r
379**/\r
380#define PAL_PREFETCH_VISIBILITY 41\r
381\r
382/**\r
383 \r
384 Return information needed for ptc.e instruction to purge\r
385 entire TC. It is required by IPF.\r
386\r
387 @param CallingConvention Static Registers\r
388\r
389 @param Mode Physical/Virtual\r
390 \r
391**/\r
392#define PAL_PTCE_INFO 6\r
393\r
394/**\r
395 \r
396 Return detailed information about virtual memory features\r
397 supported in the processor. It is required by IPF.\r
398\r
399 @param CallingConvention Static Registers\r
400\r
401 @param Mode Physical/Virtual\r
402 \r
403**/\r
404#define PAL_VM_INFO 7\r
405\r
406\r
407/**\r
408 \r
409 Return virtual memory TC and hardware walker page sizes\r
410 supported in the processor. It is required by IPF.\r
411\r
412 @param CallingConvention Static Registers\r
413\r
414 @param Mode Physical\r
415 \r
416**/\r
417#define PAL_VM_PAGE_SIZE 34\r
418\r
419/**\r
420 \r
421 Return summary information about virtual memory features\r
422 supported in the processor. It is required by IPF.\r
423\r
424 @param CallingConvention Static Registers\r
425\r
426 @param Mode Physical/Virtual\r
427 \r
428**/\r
429#define PAL_VM_SUMMARY 8\r
430\r
431/**\r
432 \r
433 Read contents of a translation register. It is required by\r
434 IPF.\r
435\r
436 @param CallingConvention Stacked Register\r
437\r
438 @param Mode Physical\r
439 \r
440**/\r
441#define PAL_VM_TR_READ 261 \r
442\r
443/**\r
444 \r
445 Return configurable processor bus interface features and their\r
446 current settings. It is required by IPF.\r
447\r
448 @param CallingConvention Static Registers\r
449\r
450 @param Mode Physical\r
451 \r
452**/\r
453#define PAL_BUS_GET_FEATURES 9\r
454\r
455\r
456/**\r
457 \r
458 Enable or disable configurable features in processor bus\r
459 interface. It is required by IPF.\r
460\r
461 @param CallingConvention Static Registers\r
462\r
463 @param Mode Physical\r
464 \r
465**/\r
466#define PAL_BUS_SET_FEATURES 10\r
467\r
468\r
469/**\r
470 \r
471 Return the number of instruction and data breakpoint\r
472 registers. It is required by IPF.\r
473\r
474 @param CallingConvention Static Registers\r
475\r
476 @param Mode Physical/Virtual\r
477 \r
478**/\r
479#define PAL_DEBUG_INFO 11\r
480\r
481/**\r
482 \r
483