Updated function headers for CacheMaintenanceLib
[mirror_edk2.git] / MdePkg / Include / Library / CacheMaintenanceLib.h
CommitLineData
878ddf1f 1/** @file\r
2 Cache Maintenance Functions\r
3\r
4 Copyright (c) 2006, Intel Corporation\r
5 All rights reserved. This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13 Module Name: CacheMaintenanceLib.h\r
14\r
15**/\r
16\r
17#ifndef __CACHE_MAINTENANCE_LIB__\r
18#define __CACHE_MAINTENANCE_LIB__\r
19\r
b546c3ad 20/**\r
21 Invalidates the entire instruction cache in cache coherency domain of the\r
22 calling CPU.\r
23\r
24 Invalidates the entire instruction cache in cache coherency domain of the\r
25 calling CPU.\r
26\r
27**/\r
878ddf1f 28VOID\r
29EFIAPI\r
30InvalidateInstructionCache (\r
31 VOID\r
32 );\r
33\r
b546c3ad 34/**\r
35 Invalidates a range of instruction cache lines in the cache coherency domain\r
36 of the calling CPU.\r
37\r
38 Invalidates the instruction cache lines specified by Address and Length. If\r
39 Address is not aligned on a cache line boundary, then entire instruction\r
40 cache line containing Address is invalidated. If Address + Length is not\r
41 aligned on a cache line boundary, then the entire instruction cache line\r
42 containing Address + Length -1 is invalidated. This function may choose to\r
43 invalidate the entire instruction cache if that is more efficient than\r
44 invalidating the specified range. If Length is 0, the no instruction cache\r
45 lines are invalidated. Address is returned.\r
46\r
47 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
48\r
49 @param Address The base address of the instruction cache lines to\r
50 invalidate. If the CPU is in a physical addressing mode, then\r
51 Address is a physical address. If the CPU is in a virtual\r
52 addressing mode, then Address is a virtual address.\r
53\r
54 @param Length The number of bytes to invalidate from the instruction cache.\r
55\r
56 @return Address\r
57\r
58**/\r
878ddf1f 59VOID *\r
60EFIAPI\r
61InvalidateInstructionCacheRange (\r
62 IN VOID *Address,\r
63 IN UINTN Length\r
64 );\r
65\r
b546c3ad 66/**\r
67 Writes Back and Invalidates the entire data cache in cache coherency domain\r
68 of the calling CPU.\r
69\r
70 Writes Back and Invalidates the entire data cache in cache coherency domain\r
71 of the calling CPU. This function guarantees that all dirty cache lines are\r
72 written back to system memory, and also invalidates all the data cache lines\r
73 in the cache coherency domain of the calling CPU.\r
74\r
75**/\r
878ddf1f 76VOID\r
77EFIAPI\r
78WriteBackInvalidateDataCache (\r
79 VOID\r
80 );\r
81\r
b546c3ad 82/**\r
83 Writes Back and Invalidates a range of data cache lines in the cache\r
84 coherency domain of the calling CPU.\r
85\r
86 Writes Back and Invalidate the data cache lines specified by Address and\r
87 Length. If Address is not aligned on a cache line boundary, then entire data\r
88 cache line containing Address is written back and invalidated. If Address +\r
89 Length is not aligned on a cache line boundary, then the entire data cache\r
90 line containing Address + Length -1 is written back and invalidated. This\r
91 function may choose to write back and invalidate the entire data cache if\r
92 that is more efficient than writing back and invalidating the specified\r
93 range. If Length is 0, the no data cache lines are written back and\r
94 invalidated. Address is returned.\r
95\r
96 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
97\r
98 @param Address The base address of the data cache lines to write back and\r
99 invalidate. If the CPU is in a physical addressing mode, then\r
100 Address is a physical address. If the CPU is in a virtual\r
101 addressing mode, then Address is a virtual address.\r
102 @param Length The number of bytes to write back and invalidate from the\r
103 data cache.\r
104\r
105 @return Address\r
106\r
107**/\r
878ddf1f 108VOID *\r
109EFIAPI\r
110WriteBackInvalidateDataCacheRange (\r
111 IN VOID *Address,\r
112 IN UINTN Length\r
113 );\r
114\r
b546c3ad 115/**\r
116 Writes Back the entire data cache in cache coherency domain of the calling\r
117 CPU.\r
118\r
119 Writes Back the entire data cache in cache coherency domain of the calling\r
120 CPU. This function guarantees that all dirty cache lines are written back to\r
121 system memory. This function may also invalidate all the data cache lines in\r
122 the cache coherency domain of the calling CPU.\r
123\r
124**/\r
878ddf1f 125VOID\r
126EFIAPI\r
127WriteBackDataCache (\r
128 VOID\r
129 );\r
130\r
b546c3ad 131/**\r
132 Writes Back a range of data cache lines in the cache coherency domain of the\r
133 calling CPU.\r
134\r
135 Writes Back the data cache lines specified by Address and Length. If Address\r
136 is not aligned on a cache line boundary, then entire data cache line\r
137 containing Address is written back. If Address + Length is not aligned on a\r
138 cache line boundary, then the entire data cache line containing Address +\r
139 Length -1 is written back. This function may choose to write back the entire\r
140 data cache if that is more efficient than writing back the specified range.\r
141 If Length is 0, the no data cache lines are written back. This function may\r
142 also invalidate all the data cache lines in the specified range of the cache\r
143 coherency domain of the calling CPU. Address is returned.\r
144\r
145 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
146\r
147 @param Address The base address of the data cache lines to write back. If\r
148 the CPU is in a physical addressing mode, then Address is a\r
149 physical address. If the CPU is in a virtual addressing\r
150 mode, then Address is a virtual address.\r
151 @param Length The number of bytes to write back from the data cache.\r
152\r
153 @return Address\r
154\r
155**/\r
878ddf1f 156VOID *\r
157EFIAPI\r
158WriteBackDataCacheRange (\r
159 IN VOID *Address,\r
160 IN UINTN Length\r
161 );\r
162\r
b546c3ad 163/**\r
164 Invalidates the entire data cache in cache coherency domain of the calling\r
165 CPU.\r
166\r
167 Invalidates the entire data cache in cache coherency domain of the calling\r
168 CPU. This function must be used with care because dirty cache lines are not\r
169 written back to system memory. It is typically used for cache diagnostics. If\r
170 the CPU does not support invalidation of the entire data cache, then a write\r
171 back and invalidate operation should be performed on the entire data cache.\r
172\r
173**/\r
878ddf1f 174VOID\r
175EFIAPI\r
176InvalidateDataCache (\r
177 VOID\r
178 );\r
179\r
b546c3ad 180/**\r
181 Invalidates a range of data cache lines in the cache coherency domain of the\r
182 calling CPU.\r
183\r
184 Invalidates the data cache lines specified by Address and Length. If Address\r
185 is not aligned on a cache line boundary, then entire data cache line\r
186 containing Address is invalidated. If Address + Length is not aligned on a\r
187 cache line boundary, then the entire data cache line containing Address +\r
188 Length -1 is invalidated. This function must never invalidate any cache lines\r
189 outside the specified range. If Length is 0, the no data cache lines are\r
190 invalidated. Address is returned. This function must be used with care\r
191 because dirty cache lines are not written back to system memory. It is\r
192 typically used for cache diagnostics. If the CPU does not support\r
193 invalidation of a data cache range, then a write back and invalidate\r
194 operation should be performed on the data cache range.\r
195\r
196 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
197\r
198 @param Address The base address of the data cache lines to invalidate. If\r
199 the CPU is in a physical addressing mode, then Address is a\r
200 physical address. If the CPU is in a virtual addressing mode,\r
201 then Address is a virtual address.\r
202 @param Length The number of bytes to invalidate from the data cache.\r
203\r
204 @return Address\r
205\r
206**/\r
878ddf1f 207VOID *\r
208EFIAPI\r
b546c3ad 209InvalidateDataCacheRange (\r
878ddf1f 210 IN VOID *Address,\r
211 IN UINTN Length\r
212 );\r
213\r
214#endif\r