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1 | /** @file\r |
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2 | Pci Express Library Services for PCI Segment #0\r |
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3 | \r |
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4 | Copyright (c) 2006, Intel Corporation\r |
| 5 | All rights reserved. This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | which accompanies this distribution. The full text of the license may be found at\r |
| 8 | http://opensource.org/licenses/bsd-license.php\r |
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9 | \r |
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10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
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12 | \r |
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13 | Module Name: PciExpressLib.h\r |
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14 | \r |
| 15 | **/\r |
| 16 | \r |
| 17 | #ifndef __PCI_EXPRESS_LIB_H__\r |
| 18 | #define __PCI_EXPRESS_LIB_H__\r |
| 19 | \r |
| 20 | #include <Library/PciLib.h>\r |
| 21 | \r |
| 22 | /**\r |
| 23 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r |
| 24 | address that can be passed to the PCI Library functions.\r |
| 25 | \r |
| 26 | Computes an address that is compatible with the PCI Library functions. The\r |
| 27 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r |
| 28 | the generation of the address.\r |
| 29 | \r |
| 30 | @param Bus PCI Bus number. Range 0..255.\r |
| 31 | @param Device PCI Device number. Range 0..31.\r |
| 32 | @param Function PCI Function number. Range 0..7.\r |
| 33 | @param Register PCI Register number. Range 0..4095.\r |
| 34 | \r |
| 35 | @return The encode PCI address.\r |
| 36 | \r |
| 37 | **/\r |
| 38 | #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \\r |
| 2ce31132 |
39 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r |
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40 | \r |
| 41 | /**\r |
| 42 | Reads an 8-bit PCI configuration register.\r |
| 43 | \r |
| 44 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 45 | This function must guarantee that all PCI read and write operations are\r |
| 46 | serialized.\r |
| 47 | \r |
| 48 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 49 | \r |
| 50 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 51 | Register.\r |
| 52 | \r |
| 53 | @return The read value from the PCI configuration register.\r |
| 54 | \r |
| 55 | **/\r |
| 56 | UINT8\r |
| 57 | EFIAPI\r |
| 58 | PciExpressRead8 (\r |
| 59 | IN UINTN Address\r |
| 60 | );\r |
| 61 | \r |
| 62 | /**\r |
| 63 | Writes an 8-bit PCI configuration register.\r |
| 64 | \r |
| 65 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 66 | value specified by Value. Value is returned. This function must guarantee\r |
| 67 | that all PCI read and write operations are serialized.\r |
| 68 | \r |
| 69 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 70 | \r |
| 71 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 72 | Register.\r |
| 73 | @param Value The value to write.\r |
| 74 | \r |
| 75 | @return The value written to the PCI configuration register.\r |
| 76 | \r |
| 77 | **/\r |
| 78 | UINT8\r |
| 79 | EFIAPI\r |
| 80 | PciExpressWrite8 (\r |
| 81 | IN UINTN Address,\r |
| 82 | IN UINT8 Data\r |
| 83 | );\r |
| 84 | \r |
| 85 | /**\r |
| 86 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r |
| 87 | an 8-bit value.\r |
| 88 | \r |
| 89 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 90 | bitwise inclusive OR between the read result and the value specified by\r |
| 91 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 92 | specified by Address. The value written to the PCI configuration register is\r |
| 93 | returned. This function must guarantee that all PCI read and write operations\r |
| 94 | are serialized.\r |
| 95 | \r |
| 96 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 97 | \r |
| 98 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 99 | Register.\r |
| 100 | @param OrData The value to OR with the PCI configuration register.\r |
| 101 | \r |
| 102 | @return The value written back to the PCI configuration register.\r |
| 103 | \r |
| 104 | **/\r |
| 105 | UINT8\r |
| 106 | EFIAPI\r |
| 107 | PciExpressOr8 (\r |
| 108 | IN UINTN Address,\r |
| 109 | IN UINT8 OrData\r |
| 110 | );\r |
| 111 | \r |
| 112 | /**\r |
| 113 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 114 | value.\r |
| 115 | \r |
| 116 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 117 | bitwise AND between the read result and the value specified by AndData, and\r |
| 118 | writes the result to the 8-bit PCI configuration register specified by\r |
| 119 | Address. The value written to the PCI configuration register is returned.\r |
| 120 | This function must guarantee that all PCI read and write operations are\r |
| 121 | serialized.\r |
| 122 | \r |
| 123 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 124 | \r |
| 125 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 126 | Register.\r |
| 127 | @param AndData The value to AND with the PCI configuration register.\r |
| 128 | \r |
| 129 | @return The value written back to the PCI configuration register.\r |
| 130 | \r |
| 131 | **/\r |
| 132 | UINT8\r |
| 133 | EFIAPI\r |
| 134 | PciExpressAnd8 (\r |
| 135 | IN UINTN Address,\r |
| 136 | IN UINT8 AndData\r |
| 137 | );\r |
| 138 | \r |
| 139 | /**\r |
| 140 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 141 | value, followed a bitwise inclusive OR with another 8-bit value.\r |
| 142 | \r |
| 143 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 144 | bitwise AND between the read result and the value specified by AndData,\r |
| 145 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 146 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 147 | configuration register specified by Address. The value written to the PCI\r |
| 148 | configuration register is returned. This function must guarantee that all PCI\r |
| 149 | read and write operations are serialized.\r |
| 150 | \r |
| 151 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 152 | \r |
| 153 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 154 | Register.\r |
| 155 | @param AndData The value to AND with the PCI configuration register.\r |
| 156 | @param OrData The value to OR with the result of the AND operation.\r |
| 157 | \r |
| 158 | @return The value written back to the PCI configuration register.\r |
| 159 | \r |
| 160 | **/\r |
| 161 | UINT8\r |
| 162 | EFIAPI\r |
| 163 | PciExpressAndThenOr8 (\r |
| 164 | IN UINTN Address,\r |
| 165 | IN UINT8 AndData,\r |
| 166 | IN UINT8 OrData\r |
| 167 | );\r |
| 168 | \r |
| 169 | /**\r |
| 170 | Reads a bit field of a PCI configuration register.\r |
| 171 | \r |
| 172 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 173 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 174 | returned.\r |
| 175 | \r |
| 176 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 177 | If StartBit is greater than 7, then ASSERT().\r |
| 178 | If EndBit is greater than 7, then ASSERT().\r |
| 0ffa1286 |
179 | If EndBit is less than StartBit, then ASSERT().\r |
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180 | \r |
| 181 | @param Address PCI configuration register to read.\r |
| 182 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 183 | Range 0..7.\r |
| 184 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 185 | Range 0..7.\r |
| 186 | \r |
| 187 | @return The value of the bit field read from the PCI configuration register.\r |
| 188 | \r |
| 189 | **/\r |
| 190 | UINT8\r |
| 191 | EFIAPI\r |
| 192 | PciExpressBitFieldRead8 (\r |
| 193 | IN UINTN Address,\r |
| 194 | IN UINTN StartBit,\r |
| 195 | IN UINTN EndBit\r |
| 196 | );\r |
| 197 | \r |
| 198 | /**\r |
| 199 | Writes a bit field to a PCI configuration register.\r |
| 200 | \r |
| 201 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 202 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 203 | destination PCI configuration register are preserved. The new value of the\r |
| 204 | 8-bit register is returned.\r |
| 205 | \r |
| 206 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 207 | If StartBit is greater than 7, then ASSERT().\r |
| 208 | If EndBit is greater than 7, then ASSERT().\r |
| 0ffa1286 |
209 | If EndBit is less than StartBit, then ASSERT().\r |
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210 | \r |
| 211 | @param Address PCI configuration register to write.\r |
| 212 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 213 | Range 0..7.\r |
| 214 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 215 | Range 0..7.\r |
| 216 | @param Value New value of the bit field.\r |
| 217 | \r |
| 218 | @return The value written back to the PCI configuration register.\r |
| 219 | \r |
| 220 | **/\r |
| 221 | UINT8\r |
| 222 | EFIAPI\r |
| 223 | PciExpressBitFieldWrite8 (\r |
| 224 | IN UINTN Address,\r |
| 225 | IN UINTN StartBit,\r |
| 226 | IN UINTN EndBit,\r |
| 227 | IN UINT8 Value\r |
| 228 | );\r |
| 229 | \r |
| 230 | /**\r |
| 231 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 232 | writes the result back to the bit field in the 8-bit port.\r |
| 233 | \r |
| 234 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 235 | bitwise inclusive OR between the read result and the value specified by\r |
| 236 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 237 | specified by Address. The value written to the PCI configuration register is\r |
| 238 | returned. This function must guarantee that all PCI read and write operations\r |
| 239 | are serialized. Extra left bits in OrData are stripped.\r |
| 240 | \r |
| 241 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 242 | If StartBit is greater than 7, then ASSERT().\r |
| 243 | If EndBit is greater than 7, then ASSERT().\r |
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244 | If EndBit is less than StartBit, then ASSERT().\r |
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245 | \r |
| 246 | @param Address PCI configuration register to write.\r |
| 247 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 248 | Range 0..7.\r |
| 249 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 250 | Range 0..7.\r |
| 251 | @param OrData The value to OR with the PCI configuration register.\r |
| 252 | \r |
| 253 | @return The value written back to the PCI configuration register.\r |
| 254 | \r |
| 255 | **/\r |
| 256 | UINT8\r |
| 257 | EFIAPI\r |
| 258 | PciExpressBitFieldOr8 (\r |
| 259 | IN UINTN Address,\r |
| 260 | IN UINTN StartBit,\r |
| 261 | IN UINTN EndBit,\r |
| 262 | IN UINT8 OrData\r |
| 263 | );\r |
| 264 | \r |
| 265 | /**\r |
| 266 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 267 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 268 | \r |
| 269 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 270 | bitwise AND between the read result and the value specified by AndData, and\r |
| 271 | writes the result to the 8-bit PCI configuration register specified by\r |
| 272 | Address. The value written to the PCI configuration register is returned.\r |
| 273 | This function must guarantee that all PCI read and write operations are\r |
| 274 | serialized. Extra left bits in AndData are stripped.\r |
| 275 | \r |
| 276 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 277 | If StartBit is greater than 7, then ASSERT().\r |
| 278 | If EndBit is greater than 7, then ASSERT().\r |
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279 | If EndBit is less than StartBit, then ASSERT().\r |
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280 | \r |
| 281 | @param Address PCI configuration register to write.\r |
| 282 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 283 | Range 0..7.\r |
| 284 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 285 | Range 0..7.\r |
| 286 | @param AndData The value to AND with the PCI configuration register.\r |
| 287 | \r |
| 288 | @return The value written back to the PCI configuration register.\r |
| 289 | \r |
| 290 | **/\r |
| 291 | UINT8\r |
| 292 | EFIAPI\r |
| 293 | PciExpressBitFieldAnd8 (\r |
| 294 | IN UINTN Address,\r |
| 295 | IN UINTN StartBit,\r |
| 296 | IN UINTN EndBit,\r |
| 297 | IN UINT8 AndData\r |
| 298 | );\r |
| 299 | \r |
| 300 | /**\r |
| 301 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 302 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 303 | 8-bit port.\r |
| 304 | \r |
| 305 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 306 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 307 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 308 | configuration register specified by Address. The value written to the PCI\r |
| 309 | configuration register is returned. This function must guarantee that all PCI\r |
| 310 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 311 | OrData are stripped.\r |
| 312 | \r |
| 313 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 314 | If StartBit is greater than 7, then ASSERT().\r |
| 315 | If EndBit is greater than 7, then ASSERT().\r |
| 0ffa1286 |
316 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
317 | \r |
| 318 | @param Address PCI configuration register to write.\r |
| 319 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 320 | Range 0..7.\r |
| 321 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 322 | Range 0..7.\r |
| 323 | @param AndData The value to AND with the PCI configuration register.\r |
| 324 | @param OrData The value to OR with the result of the AND operation.\r |
| 325 | \r |
| 326 | @return The value written back to the PCI configuration register.\r |
| 327 | \r |
| 328 | **/\r |
| 329 | UINT8\r |
| 330 | EFIAPI\r |
| 331 | PciExpressBitFieldAndThenOr8 (\r |
| 332 | IN UINTN Address,\r |
| 333 | IN UINTN StartBit,\r |
| 334 | IN UINTN EndBit,\r |
| 335 | IN UINT8 AndData,\r |
| 336 | IN UINT8 OrData\r |
| 337 | );\r |
| 338 | \r |
| 339 | /**\r |
| 340 | Reads a 16-bit PCI configuration register.\r |
| 341 | \r |
| 342 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 343 | This function must guarantee that all PCI read and write operations are\r |
| 344 | serialized.\r |
| 345 | \r |
| 346 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 347 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 348 | \r |
| 349 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 350 | Register.\r |
| 351 | \r |
| 352 | @return The read value from the PCI configuration register.\r |
| 353 | \r |
| 354 | **/\r |
| 355 | UINT16\r |
| 356 | EFIAPI\r |
| 357 | PciExpressRead16 (\r |
| 358 | IN UINTN Address\r |
| 359 | );\r |
| 360 | \r |
| 361 | /**\r |
| 362 | Writes a 16-bit PCI configuration register.\r |
| 363 | \r |
| 364 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 365 | value specified by Value. Value is returned. This function must guarantee\r |
| 366 | that all PCI read and write operations are serialized.\r |
| 367 | \r |
| 368 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 369 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 370 | \r |
| 371 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 372 | Register.\r |
| 373 | @param Value The value to write.\r |
| 374 | \r |
| 375 | @return The value written to the PCI configuration register.\r |
| 376 | \r |
| 377 | **/\r |
| 378 | UINT16\r |
| 379 | EFIAPI\r |
| 380 | PciExpressWrite16 (\r |
| 381 | IN UINTN Address,\r |
| 382 | IN UINT16 Data\r |
| 383 | );\r |
| 384 | \r |
| 385 | /**\r |
| 386 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r |
| 387 | a 16-bit value.\r |
| 388 | \r |
| 389 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 390 | bitwise inclusive OR between the read result and the value specified by\r |
| 391 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 392 | specified by Address. The value written to the PCI configuration register is\r |
| 393 | returned. This function must guarantee that all PCI read and write operations\r |
| 394 | are serialized.\r |
| 395 | \r |
| 396 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 397 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 398 | \r |
| 399 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 400 | Register.\r |
| 401 | @param OrData The value to OR with the PCI configuration register.\r |
| 402 | \r |
| 403 | @return The value written back to the PCI configuration register.\r |
| 404 | \r |
| 405 | **/\r |
| 406 | UINT16\r |
| 407 | EFIAPI\r |
| 408 | PciExpressOr16 (\r |
| 409 | IN UINTN Address,\r |
| 410 | IN UINT16 OrData\r |
| 411 | );\r |
| 412 | \r |
| 413 | /**\r |
| 414 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 415 | value.\r |
| 416 | \r |
| 417 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 418 | bitwise AND between the read result and the value specified by AndData, and\r |
| 419 | writes the result to the 16-bit PCI configuration register specified by\r |
| 420 | Address. The value written to the PCI configuration register is returned.\r |
| 421 | This function must guarantee that all PCI read and write operations are\r |
| 422 | serialized.\r |
| 423 | \r |
| 424 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 425 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 426 | \r |
| 427 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 428 | Register.\r |
| 429 | @param AndData The value to AND with the PCI configuration register.\r |
| 430 | \r |
| 431 | @return The value written back to the PCI configuration register.\r |
| 432 | \r |
| 433 | **/\r |
| 434 | UINT16\r |
| 435 | EFIAPI\r |
| 436 | PciExpressAnd16 (\r |
| 437 | IN UINTN Address,\r |
| 438 | IN UINT16 AndData\r |
| 439 | );\r |
| 440 | \r |
| 441 | /**\r |
| 442 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 443 | value, followed a bitwise inclusive OR with another 16-bit value.\r |
| 444 | \r |
| 445 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 446 | bitwise AND between the read result and the value specified by AndData,\r |
| 447 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 448 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 449 | configuration register specified by Address. The value written to the PCI\r |
| 450 | configuration register is returned. This function must guarantee that all PCI\r |
| 451 | read and write operations are serialized.\r |
| 452 | \r |
| 453 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 454 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 455 | \r |
| 456 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 457 | Register.\r |
| 458 | @param AndData The value to AND with the PCI configuration register.\r |
| 459 | @param OrData The value to OR with the result of the AND operation.\r |
| 460 | \r |
| 461 | @return The value written back to the PCI configuration register.\r |
| 462 | \r |
| 463 | **/\r |
| 464 | UINT16\r |
| 465 | EFIAPI\r |
| 466 | PciExpressAndThenOr16 (\r |
| 467 | IN UINTN Address,\r |
| 468 | IN UINT16 AndData,\r |
| 469 | IN UINT16 OrData\r |
| 470 | );\r |
| 471 | \r |
| 472 | /**\r |
| 473 | Reads a bit field of a PCI configuration register.\r |
| 474 | \r |
| 475 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 476 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 477 | returned.\r |
| 478 | \r |
| 479 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 480 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 481 | If StartBit is greater than 15, then ASSERT().\r |
| 482 | If EndBit is greater than 15, then ASSERT().\r |
| 0ffa1286 |
483 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
484 | \r |
| 485 | @param Address PCI configuration register to read.\r |
| 486 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 487 | Range 0..15.\r |
| 488 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 489 | Range 0..15.\r |
| 490 | \r |
| 491 | @return The value of the bit field read from the PCI configuration register.\r |
| 492 | \r |
| 493 | **/\r |
| 494 | UINT16\r |
| 495 | EFIAPI\r |
| 496 | PciExpressBitFieldRead16 (\r |
| 497 | IN UINTN Address,\r |
| 498 | IN UINTN StartBit,\r |
| 499 | IN UINTN EndBit\r |
| 500 | );\r |
| 501 | \r |
| 502 | /**\r |
| 503 | Writes a bit field to a PCI configuration register.\r |
| 504 | \r |
| 505 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 506 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 507 | destination PCI configuration register are preserved. The new value of the\r |
| 508 | 16-bit register is returned.\r |
| 509 | \r |
| 510 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 511 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 512 | If StartBit is greater than 15, then ASSERT().\r |
| 513 | If EndBit is greater than 15, then ASSERT().\r |
| 0ffa1286 |
514 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
515 | \r |
| 516 | @param Address PCI configuration register to write.\r |
| 517 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 518 | Range 0..15.\r |
| 519 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 520 | Range 0..15.\r |
| 521 | @param Value New value of the bit field.\r |
| 522 | \r |
| 523 | @return The value written back to the PCI configuration register.\r |
| 524 | \r |
| 525 | **/\r |
| 526 | UINT16\r |
| 527 | EFIAPI\r |
| 528 | PciExpressBitFieldWrite16 (\r |
| 529 | IN UINTN Address,\r |
| 530 | IN UINTN StartBit,\r |
| 531 | IN UINTN EndBit,\r |
| 532 | IN UINT16 Value\r |
| 533 | );\r |
| 534 | \r |
| 535 | /**\r |
| 536 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 537 | writes the result back to the bit field in the 16-bit port.\r |
| 538 | \r |
| 539 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 540 | bitwise inclusive OR between the read result and the value specified by\r |
| 541 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 542 | specified by Address. The value written to the PCI configuration register is\r |
| 543 | returned. This function must guarantee that all PCI read and write operations\r |
| 544 | are serialized. Extra left bits in OrData are stripped.\r |
| 545 | \r |
| 546 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 547 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 548 | If StartBit is greater than 15, then ASSERT().\r |
| 549 | If EndBit is greater than 15, then ASSERT().\r |
| 0ffa1286 |
550 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
551 | \r |
| 552 | @param Address PCI configuration register to write.\r |
| 553 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 554 | Range 0..15.\r |
| 555 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 556 | Range 0..15.\r |
| 557 | @param OrData The value to OR with the PCI configuration register.\r |
| 558 | \r |
| 559 | @return The value written back to the PCI configuration register.\r |
| 560 | \r |
| 561 | **/\r |
| 562 | UINT16\r |
| 563 | EFIAPI\r |
| 564 | PciExpressBitFieldOr16 (\r |
| 565 | IN UINTN Address,\r |
| 566 | IN UINTN StartBit,\r |
| 567 | IN UINTN EndBit,\r |
| 568 | IN UINT16 OrData\r |
| 569 | );\r |
| 570 | \r |
| 571 | /**\r |
| 572 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 573 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 574 | \r |
| 575 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 576 | bitwise AND between the read result and the value specified by AndData, and\r |
| 577 | writes the result to the 16-bit PCI configuration register specified by\r |
| 578 | Address. The value written to the PCI configuration register is returned.\r |
| 579 | This function must guarantee that all PCI read and write operations are\r |
| 580 | serialized. Extra left bits in AndData are stripped.\r |
| 581 | \r |
| 582 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 583 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 584 | If StartBit is greater than 15, then ASSERT().\r |
| 585 | If EndBit is greater than 15, then ASSERT().\r |
| 0ffa1286 |
586 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
587 | \r |
| 588 | @param Address PCI configuration register to write.\r |
| 589 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 590 | Range 0..15.\r |
| 591 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 592 | Range 0..15.\r |
| 593 | @param AndData The value to AND with the PCI configuration register.\r |
| 594 | \r |
| 595 | @return The value written back to the PCI configuration register.\r |
| 596 | \r |
| 597 | **/\r |
| 598 | UINT16\r |
| 599 | EFIAPI\r |
| 600 | PciExpressBitFieldAnd16 (\r |
| 601 | IN UINTN Address,\r |
| 602 | IN UINTN StartBit,\r |
| 603 | IN UINTN EndBit,\r |
| 604 | IN UINT16 AndData\r |
| 605 | );\r |
| 606 | \r |
| 607 | /**\r |
| 608 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 609 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 610 | 16-bit port.\r |
| 611 | \r |
| 612 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 613 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 614 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 615 | configuration register specified by Address. The value written to the PCI\r |
| 616 | configuration register is returned. This function must guarantee that all PCI\r |
| 617 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 618 | OrData are stripped.\r |
| 619 | \r |
| 620 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 621 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 622 | If StartBit is greater than 15, then ASSERT().\r |
| 623 | If EndBit is greater than 15, then ASSERT().\r |
| 0ffa1286 |
624 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
625 | \r |
| 626 | @param Address PCI configuration register to write.\r |
| 627 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 628 | Range 0..15.\r |
| 629 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 630 | Range 0..15.\r |
| 631 | @param AndData The value to AND with the PCI configuration register.\r |
| 632 | @param OrData The value to OR with the result of the AND operation.\r |
| 633 | \r |
| 634 | @return The value written back to the PCI configuration register.\r |
| 635 | \r |
| 636 | **/\r |
| 637 | UINT16\r |
| 638 | EFIAPI\r |
| 639 | PciExpressBitFieldAndThenOr16 (\r |
| 640 | IN UINTN Address,\r |
| 641 | IN UINTN StartBit,\r |
| 642 | IN UINTN EndBit,\r |
| 643 | IN UINT16 AndData,\r |
| 644 | IN UINT16 OrData\r |
| 645 | );\r |
| 646 | \r |
| 647 | /**\r |
| 648 | Reads a 32-bit PCI configuration register.\r |
| 649 | \r |
| 650 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 651 | This function must guarantee that all PCI read and write operations are\r |
| 652 | serialized.\r |
| 653 | \r |
| 654 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 655 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 656 | \r |
| 657 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 658 | Register.\r |
| 659 | \r |
| 660 | @return The read value from the PCI configuration register.\r |
| 661 | \r |
| 662 | **/\r |
| 663 | UINT32\r |
| 664 | EFIAPI\r |
| 665 | PciExpressRead32 (\r |
| 666 | IN UINTN Address\r |
| 667 | );\r |
| 668 | \r |
| 669 | /**\r |
| 670 | Writes a 32-bit PCI configuration register.\r |
| 671 | \r |
| 672 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 673 | value specified by Value. Value is returned. This function must guarantee\r |
| 674 | that all PCI read and write operations are serialized.\r |
| 675 | \r |
| 676 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 677 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 678 | \r |
| 679 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 680 | Register.\r |
| 681 | @param Value The value to write.\r |
| 682 | \r |
| 683 | @return The value written to the PCI configuration register.\r |
| 684 | \r |
| 685 | **/\r |
| 686 | UINT32\r |
| 687 | EFIAPI\r |
| 688 | PciExpressWrite32 (\r |
| 689 | IN UINTN Address,\r |
| 690 | IN UINT32 Data\r |
| 691 | );\r |
| 692 | \r |
| 693 | /**\r |
| 694 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r |
| 695 | a 32-bit value.\r |
| 696 | \r |
| 697 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 698 | bitwise inclusive OR between the read result and the value specified by\r |
| 699 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 700 | specified by Address. The value written to the PCI configuration register is\r |
| 701 | returned. This function must guarantee that all PCI read and write operations\r |
| 702 | are serialized.\r |
| 703 | \r |
| 704 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 705 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 706 | \r |
| 707 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 708 | Register.\r |
| 709 | @param OrData The value to OR with the PCI configuration register.\r |
| 710 | \r |
| 711 | @return The value written back to the PCI configuration register.\r |
| 712 | \r |
| 713 | **/\r |
| 714 | UINT32\r |
| 715 | EFIAPI\r |
| 716 | PciExpressOr32 (\r |
| 717 | IN UINTN Address,\r |
| 718 | IN UINT32 OrData\r |
| 719 | );\r |
| 720 | \r |
| 721 | /**\r |
| 722 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 723 | value.\r |
| 724 | \r |
| 725 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 726 | bitwise AND between the read result and the value specified by AndData, and\r |
| 727 | writes the result to the 32-bit PCI configuration register specified by\r |
| 728 | Address. The value written to the PCI configuration register is returned.\r |
| 729 | This function must guarantee that all PCI read and write operations are\r |
| 730 | serialized.\r |
| 731 | \r |
| 732 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 733 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 734 | \r |
| 735 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 736 | Register.\r |
| 737 | @param AndData The value to AND with the PCI configuration register.\r |
| 738 | \r |
| 739 | @return The value written back to the PCI configuration register.\r |
| 740 | \r |
| 741 | **/\r |
| 742 | UINT32\r |
| 743 | EFIAPI\r |
| 744 | PciExpressAnd32 (\r |
| 745 | IN UINTN Address,\r |
| 746 | IN UINT32 AndData\r |
| 747 | );\r |
| 748 | \r |
| 749 | /**\r |
| 750 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 751 | value, followed a bitwise inclusive OR with another 32-bit value.\r |
| 752 | \r |
| 753 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 754 | bitwise AND between the read result and the value specified by AndData,\r |
| 755 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 756 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 757 | configuration register specified by Address. The value written to the PCI\r |
| 758 | configuration register is returned. This function must guarantee that all PCI\r |
| 759 | read and write operations are serialized.\r |
| 760 | \r |
| 761 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 762 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 763 | \r |
| 764 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 765 | Register.\r |
| 766 | @param AndData The value to AND with the PCI configuration register.\r |
| 767 | @param OrData The value to OR with the result of the AND operation.\r |
| 768 | \r |
| 769 | @return The value written back to the PCI configuration register.\r |
| 770 | \r |
| 771 | **/\r |
| 772 | UINT32\r |
| 773 | EFIAPI\r |
| 774 | PciExpressAndThenOr32 (\r |
| 775 | IN UINTN Address,\r |
| 776 | IN UINT32 AndData,\r |
| 777 | IN UINT32 OrData\r |
| 778 | );\r |
| 779 | \r |
| 780 | /**\r |
| 781 | Reads a bit field of a PCI configuration register.\r |
| 782 | \r |
| 783 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 784 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 785 | returned.\r |
| 786 | \r |
| 787 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 788 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 789 | If StartBit is greater than 31, then ASSERT().\r |
| 790 | If EndBit is greater than 31, then ASSERT().\r |
| 0ffa1286 |
791 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
792 | \r |
| 793 | @param Address PCI configuration register to read.\r |
| 794 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 795 | Range 0..31.\r |
| 796 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 797 | Range 0..31.\r |
| 798 | \r |
| 799 | @return The value of the bit field read from the PCI configuration register.\r |
| 800 | \r |
| 801 | **/\r |
| 802 | UINT32\r |
| 803 | EFIAPI\r |
| 804 | PciExpressBitFieldRead32 (\r |
| 805 | IN UINTN Address,\r |
| 806 | IN UINTN StartBit,\r |
| 807 | IN UINTN EndBit\r |
| 808 | );\r |
| 809 | \r |
| 810 | /**\r |
| 811 | Writes a bit field to a PCI configuration register.\r |
| 812 | \r |
| 813 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 814 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 815 | destination PCI configuration register are preserved. The new value of the\r |
| 816 | 32-bit register is returned.\r |
| 817 | \r |
| 818 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 819 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 820 | If StartBit is greater than 31, then ASSERT().\r |
| 821 | If EndBit is greater than 31, then ASSERT().\r |
| 0ffa1286 |
822 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
823 | \r |
| 824 | @param Address PCI configuration register to write.\r |
| 825 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 826 | Range 0..31.\r |
| 827 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 828 | Range 0..31.\r |
| 829 | @param Value New value of the bit field.\r |
| 830 | \r |
| 831 | @return The value written back to the PCI configuration register.\r |
| 832 | \r |
| 833 | **/\r |
| 834 | UINT32\r |
| 835 | EFIAPI\r |
| 836 | PciExpressBitFieldWrite32 (\r |
| 837 | IN UINTN Address,\r |
| 838 | IN UINTN StartBit,\r |
| 839 | IN UINTN EndBit,\r |
| 840 | IN UINT32 Value\r |
| 841 | );\r |
| 842 | \r |
| 843 | /**\r |
| 844 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 845 | writes the result back to the bit field in the 32-bit port.\r |
| 846 | \r |
| 847 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 848 | bitwise inclusive OR between the read result and the value specified by\r |
| 849 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 850 | specified by Address. The value written to the PCI configuration register is\r |
| 851 | returned. This function must guarantee that all PCI read and write operations\r |
| 852 | are serialized. Extra left bits in OrData are stripped.\r |
| 853 | \r |
| 854 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 855 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 856 | If StartBit is greater than 31, then ASSERT().\r |
| 857 | If EndBit is greater than 31, then ASSERT().\r |
| 0ffa1286 |
858 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
859 | \r |
| 860 | @param Address PCI configuration register to write.\r |
| 861 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 862 | Range 0..31.\r |
| 863 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 864 | Range 0..31.\r |
| 865 | @param OrData The value to OR with the PCI configuration register.\r |
| 866 | \r |
| 867 | @return The value written back to the PCI configuration register.\r |
| 868 | \r |
| 869 | **/\r |
| 870 | UINT32\r |
| 871 | EFIAPI\r |
| 872 | PciExpressBitFieldOr32 (\r |
| 873 | IN UINTN Address,\r |
| 874 | IN UINTN StartBit,\r |
| 875 | IN UINTN EndBit,\r |
| 876 | IN UINT32 OrData\r |
| 877 | );\r |
| 878 | \r |
| 879 | /**\r |
| 880 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 881 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 882 | \r |
| 883 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 884 | bitwise AND between the read result and the value specified by AndData, and\r |
| 885 | writes the result to the 32-bit PCI configuration register specified by\r |
| 886 | Address. The value written to the PCI configuration register is returned.\r |
| 887 | This function must guarantee that all PCI read and write operations are\r |
| 888 | serialized. Extra left bits in AndData are stripped.\r |
| 889 | \r |
| 890 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 891 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 892 | If StartBit is greater than 31, then ASSERT().\r |
| 893 | If EndBit is greater than 31, then ASSERT().\r |
| 0ffa1286 |
894 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
895 | \r |
| 896 | @param Address PCI configuration register to write.\r |
| 897 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 898 | Range 0..31.\r |
| 899 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 900 | Range 0..31.\r |
| 901 | @param AndData The value to AND with the PCI configuration register.\r |
| 902 | \r |
| 903 | @return The value written back to the PCI configuration register.\r |
| 904 | \r |
| 905 | **/\r |
| 906 | UINT32\r |
| 907 | EFIAPI\r |
| 908 | PciExpressBitFieldAnd32 (\r |
| 909 | IN UINTN Address,\r |
| 910 | IN UINTN StartBit,\r |
| 911 | IN UINTN EndBit,\r |
| 912 | IN UINT32 AndData\r |
| 913 | );\r |
| 914 | \r |
| 915 | /**\r |
| 916 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 917 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 918 | 32-bit port.\r |
| 919 | \r |
| 920 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 921 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 922 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 923 | configuration register specified by Address. The value written to the PCI\r |
| 924 | configuration register is returned. This function must guarantee that all PCI\r |
| 925 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 926 | OrData are stripped.\r |
| 927 | \r |
| 928 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 929 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 930 | If StartBit is greater than 31, then ASSERT().\r |
| 931 | If EndBit is greater than 31, then ASSERT().\r |
| 0ffa1286 |
932 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
933 | \r |
| 934 | @param Address PCI configuration register to write.\r |
| 935 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 936 | Range 0..31.\r |
| 937 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 938 | Range 0..31.\r |
| 939 | @param AndData The value to AND with the PCI configuration register.\r |
| 940 | @param OrData The value to OR with the result of the AND operation.\r |
| 941 | \r |
| 942 | @return The value written back to the PCI configuration register.\r |
| 943 | \r |
| 944 | **/\r |
| 945 | UINT32\r |
| 946 | EFIAPI\r |
| 947 | PciExpressBitFieldAndThenOr32 (\r |
| 948 | IN UINTN Address,\r |
| 949 | IN UINTN StartBit,\r |
| 950 | IN UINTN EndBit,\r |
| 951 | IN UINT32 AndData,\r |
| 952 | IN UINT32 OrData\r |
| 953 | );\r |
| 954 | \r |
| 955 | /**\r |
| 956 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 957 | \r |
| 958 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 959 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 960 | configuration registers from a single PCI function to be read. Size is\r |
| 961 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 962 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 963 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 964 | end of the range.\r |
| 965 | \r |
| 966 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 967 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| add13dc2 |
968 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 878ddf1f |
969 | \r |
| 970 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 971 | Function and Register.\r |
| 972 | @param Size Size in bytes of the transfer.\r |
| 973 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 974 | \r |
| 975 | @return Size\r |
| 976 | \r |
| 977 | **/\r |
| 978 | UINTN\r |
| 979 | EFIAPI\r |
| 980 | PciExpressReadBuffer (\r |
| 981 | IN UINTN StartAddress,\r |
| 982 | IN UINTN Size,\r |
| 983 | OUT VOID *Buffer\r |
| 984 | );\r |
| 985 | \r |
| 986 | /**\r |
| 987 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 988 | configuration space.\r |
| 989 | \r |
| 990 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 991 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 992 | configuration registers from a single PCI function to be written. Size is\r |
| 993 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 994 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 995 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 996 | and the end of the range.\r |
| 997 | \r |
| 998 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 999 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| add13dc2 |
1000 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 878ddf1f |
1001 | \r |
| 1002 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1003 | Function and Register.\r |
| 1004 | @param Size Size in bytes of the transfer.\r |
| 1005 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1006 | \r |
| 1007 | @return Size\r |
| 1008 | \r |
| 1009 | **/\r |
| 1010 | UINTN\r |
| 1011 | EFIAPI\r |
| 1012 | PciExpressWriteBuffer (\r |
| 1013 | IN UINTN StartAddress,\r |
| 1014 | IN UINTN Size,\r |
| 1015 | IN VOID *Buffer\r |
| 1016 | );\r |
| 1017 | \r |
| 1018 | #endif\r |
projects / mirror_edk2.git / blame