| fb3df220 |
1 | /** @file\r |
| 2 | Functions accessing PCI configuration registers on any supported PCI segment\r |
| 3 | \r |
| 4 | Copyright (c) 2006, Intel Corporation\r |
| 5 | All rights reserved. This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | which accompanies this distribution. The full text of the license may be found at\r |
| 8 | http://opensource.org/licenses/bsd-license.php\r |
| 9 | \r |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 12 | \r |
| 13 | Module Name: PciSegmentLib.h\r |
| 14 | \r |
| 15 | **/\r |
| 16 | \r |
| 17 | #ifndef __PCI_SEGMENT_LIB__\r |
| 18 | #define __PCI_SEGMENT_LIB__\r |
| 19 | \r |
| 20 | \r |
| 21 | /**\r |
| 22 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r |
| 23 | and PCI Register to an address that can be passed to the PCI Segment Library functions.\r |
| 24 | \r |
| 25 | Computes an address that is compatible with the PCI Segment Library functions.\r |
| 26 | The unused upper bits of Segment, Bus, Device, Function,\r |
| 27 | and Register are stripped prior to the generation of the address.\r |
| 28 | \r |
| 29 | @param Segment PCI Segment number. Range 0..65535.\r |
| 30 | @param Bus PCI Bus number. Range 0..255.\r |
| 31 | @param Device PCI Device number. Range 0..31.\r |
| 32 | @param Function PCI Function number. Range 0..7.\r |
| 33 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r |
| 34 | \r |
| 35 | @return The address that is compatible with the PCI Segment Library functions.\r |
| 36 | \r |
| 37 | **/\r |
| 38 | #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r |
| 39 | ( ((Register) & 0xfff) | \\r |
| 40 | (((Function) & 0x07) << 12) | \\r |
| 41 | (((Device) & 0x1f) << 15) | \\r |
| 42 | (((Bus) & 0xff) << 20) | \\r |
| 43 | (LShiftU64((Segment) & 0xffff, 32)) \\r |
| 44 | )\r |
| 45 | \r |
| 46 | /**\r |
| 47 | Reads an 8-bit PCI configuration register.\r |
| 48 | \r |
| 49 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 50 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 51 | If any reserved bits in Address are set, then ASSERT().\r |
| 52 | \r |
| 53 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 54 | \r |
| 55 | @return The 8-bit PCI configuration register specified by Address.\r |
| 56 | \r |
| 57 | **/\r |
| 58 | UINT8\r |
| 59 | EFIAPI\r |
| 60 | PciSegmentRead8 (\r |
| 61 | IN UINT64 Address\r |
| 62 | )\r |
| 63 | ;\r |
| 64 | \r |
| 65 | /**\r |
| 66 | Writes an 8-bit PCI configuration register.\r |
| 67 | \r |
| 68 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r |
| 69 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| 70 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 71 | \r |
| 72 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 73 | @param Value The value to write.\r |
| 74 | \r |
| 75 | @return The parameter of Value.\r |
| 76 | \r |
| 77 | **/\r |
| 78 | UINT8\r |
| 79 | EFIAPI\r |
| 80 | PciSegmentWrite8 (\r |
| 81 | IN UINT64 Address,\r |
| 82 | IN UINT8 Value\r |
| 83 | )\r |
| 84 | ;\r |
| 85 | \r |
| 86 | /**\r |
| 87 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.\r |
| 88 | \r |
| 89 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 90 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 91 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 92 | The value written to the PCI configuration register is returned.\r |
| 93 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 94 | If any reserved bits in Address are set, then ASSERT().\r |
| 95 | \r |
| 96 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 97 | @param OrData The value to OR with the PCI configuration register.\r |
| 98 | \r |
| 99 | @return The value written to the PCI configuration register.\r |
| 100 | \r |
| 101 | **/\r |
| 102 | UINT8\r |
| 103 | EFIAPI\r |
| 104 | PciSegmentOr8 (\r |
| 105 | IN UINT64 Address,\r |
| 106 | IN UINT8 OrData\r |
| 107 | )\r |
| 108 | ;\r |
| 109 | \r |
| 110 | /**\r |
| 111 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r |
| 112 | \r |
| 113 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 114 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 115 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 116 | The value written to the PCI configuration register is returned.\r |
| 117 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 118 | If any reserved bits in Address are set, then ASSERT().\r |
| 119 | \r |
| 120 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 121 | @param Andata The value to AND with the PCI configuration register.\r |
| 122 | \r |
| 123 | @return The value written to the PCI configuration register.\r |
| 124 | \r |
| 125 | **/\r |
| 126 | UINT8\r |
| 127 | EFIAPI\r |
| 128 | PciSegmentAnd8 (\r |
| 129 | IN UINT64 Address,\r |
| 130 | IN UINT8 AndData\r |
| 131 | )\r |
| 132 | ;\r |
| 133 | \r |
| 134 | /**\r |
| 135 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r |
| 136 | followed a bitwise inclusive OR with another 8-bit value.\r |
| 137 | \r |
| 138 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 139 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 140 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r |
| 141 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 142 | The value written to the PCI configuration register is returned.\r |
| 143 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 144 | If any reserved bits in Address are set, then ASSERT().\r |
| 145 | \r |
| 146 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 147 | @param Andata The value to AND with the PCI configuration register.\r |
| 148 | @param OrData The value to OR with the PCI configuration register.\r |
| 149 | \r |
| 150 | @return The value written to the PCI configuration register.\r |
| 151 | \r |
| 152 | **/\r |
| 153 | UINT8\r |
| 154 | EFIAPI\r |
| 155 | PciSegmentAndThenOr8 (\r |
| 156 | IN UINT64 Address,\r |
| 157 | IN UINT8 AndData,\r |
| 158 | IN UINT8 OrData\r |
| 159 | )\r |
| 160 | ;\r |
| 161 | \r |
| 162 | /**\r |
| 163 | Reads a bit field of a PCI configuration register.\r |
| 164 | \r |
| 165 | Reads the bit field in an 8-bit PCI configuration register.\r |
| 166 | The bit field is specified by the StartBit and the EndBit.\r |
| 167 | The value of the bit field is returned.\r |
| 168 | If any reserved bits in Address are set, then ASSERT().\r |
| 169 | If StartBit is greater than 7, then ASSERT().\r |
| 170 | If EndBit is greater than 7, then ASSERT().\r |
| 171 | If EndBit is less than StartBit, then ASSERT().\r |
| 172 | \r |
| 173 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 174 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 175 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 176 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 177 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 178 | \r |
| 179 | @return The value of the bit field.\r |
| 180 | \r |
| 181 | **/\r |
| 182 | UINT8\r |
| 183 | EFIAPI\r |
| 184 | PciSegmentBitFieldRead8 (\r |
| 185 | IN UINT64 Address,\r |
| 186 | IN UINTN StartBit,\r |
| 187 | IN UINTN EndBit\r |
| 188 | )\r |
| 189 | ;\r |
| 190 | \r |
| 191 | /**\r |
| 192 | Writes a bit field to a PCI configuration register.\r |
| 193 | \r |
| 194 | Writes Value to the bit field of the PCI configuration register.\r |
| 195 | The bit field is specified by the StartBit and the EndBit.\r |
| 196 | All other bits in the destination PCI configuration register are preserved.\r |
| 197 | The new value of the 8-bit register is returned.\r |
| 198 | If any reserved bits in Address are set, then ASSERT().\r |
| 199 | If StartBit is greater than 7, then ASSERT().\r |
| 200 | If EndBit is greater than 7, then ASSERT().\r |
| 201 | If EndBit is less than StartBit, then ASSERT().\r |
| 202 | \r |
| 203 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 204 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 205 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 206 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 207 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 208 | @param Value New value of the bit field.\r |
| 209 | \r |
| 210 | @return The new value of the 8-bit register.\r |
| 211 | \r |
| 212 | **/\r |
| 213 | UINT8\r |
| 214 | EFIAPI\r |
| 215 | PciSegmentBitFieldWrite8 (\r |
| 216 | IN UINT64 Address,\r |
| 217 | IN UINTN StartBit,\r |
| 218 | IN UINTN EndBit,\r |
| 219 | IN UINT8 Value\r |
| 220 | )\r |
| 221 | ;\r |
| 222 | \r |
| 223 | /**\r |
| 224 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 225 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 226 | and writes the result to the 8-bit PCI configuration register specified by Address. \r |
| 227 | \r |
| 228 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 229 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 230 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 231 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 232 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 233 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 234 | \r |
| 235 | @return The value written to the PCI configuration register.\r |
| 236 | \r |
| 237 | **/\r |
| 238 | UINT8\r |
| 239 | EFIAPI\r |
| 240 | PciSegmentBitFieldOr8 (\r |
| 241 | IN UINT64 Address,\r |
| 242 | IN UINTN StartBit,\r |
| 243 | IN UINTN EndBit,\r |
| 244 | IN UINT8 OrData\r |
| 245 | )\r |
| 246 | ;\r |
| 247 | \r |
| 248 | /**\r |
| 249 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,\r |
| 250 | and writes the result back to the bit field in the 8-bit port.\r |
| 251 | \r |
| 252 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 253 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 254 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 255 | The value written to the PCI configuration register is returned.\r |
| 256 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 257 | Extra left bits in OrData are stripped.\r |
| 258 | If any reserved bits in Address are set, then ASSERT().\r |
| 259 | If StartBit is greater than 7, then ASSERT().\r |
| 260 | If EndBit is greater than 7, then ASSERT().\r |
| 261 | If EndBit is less than StartBit, then ASSERT().\r |
| 262 | \r |
| 263 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 264 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 265 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 266 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 267 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 268 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 269 | \r |
| 270 | @return The value written to the PCI configuration register.\r |
| 271 | \r |
| 272 | **/\r |
| 273 | UINT8\r |
| 274 | EFIAPI\r |
| 275 | PciSegmentBitFieldAnd8 (\r |
| 276 | IN UINT64 Address,\r |
| 277 | IN UINTN StartBit,\r |
| 278 | IN UINTN EndBit,\r |
| 279 | IN UINT8 AndData\r |
| 280 | )\r |
| 281 | ;\r |
| 282 | \r |
| 283 | /**\r |
| 284 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,\r |
| 285 | and writes the result back to the bit field in the 8-bit register.\r |
| 286 | \r |
| 287 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 288 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 289 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 290 | The value written to the PCI configuration register is returned.\r |
| 291 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 292 | Extra left bits in AndData are stripped.\r |
| 293 | If any reserved bits in Address are set, then ASSERT().\r |
| 294 | If StartBit is greater than 7, then ASSERT().\r |
| 295 | If EndBit is greater than 7, then ASSERT().\r |
| 296 | If EndBit is less than StartBit, then ASSERT().\r |
| 297 | \r |
| 298 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 299 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 300 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 301 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 302 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 303 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 304 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 305 | \r |
| 306 | @return The value written to the PCI configuration register.\r |
| 307 | \r |
| 308 | **/\r |
| 309 | UINT8\r |
| 310 | EFIAPI\r |
| 311 | PciSegmentBitFieldAndThenOr8 (\r |
| 312 | IN UINT64 Address,\r |
| 313 | IN UINTN StartBit,\r |
| 314 | IN UINTN EndBit,\r |
| 315 | IN UINT8 AndData,\r |
| 316 | IN UINT8 OrData\r |
| 317 | )\r |
| 318 | ;\r |
| 319 | \r |
| 320 | /**\r |
| 321 | Reads a 16-bit PCI configuration register.\r |
| 322 | \r |
| 323 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 324 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 325 | If any reserved bits in Address are set, then ASSERT().\r |
| 326 | \r |
| 327 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 328 | \r |
| 329 | @return The 16-bit PCI configuration register specified by Address.\r |
| 330 | \r |
| 331 | **/\r |
| 332 | UINT16\r |
| 333 | EFIAPI\r |
| 334 | PciSegmentRead16 (\r |
| 335 | IN UINT64 Address\r |
| 336 | )\r |
| 337 | ;\r |
| 338 | \r |
| 339 | /**\r |
| 340 | Writes a 16-bit PCI configuration register.\r |
| 341 | \r |
| 342 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r |
| 343 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| 344 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 345 | \r |
| 346 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 347 | @param Value The value to write.\r |
| 348 | \r |
| 349 | @return The parameter of Value.\r |
| 350 | \r |
| 351 | **/\r |
| 352 | UINT16\r |
| 353 | EFIAPI\r |
| 354 | PciSegmentWrite16 (\r |
| 355 | IN UINT64 Address,\r |
| 356 | IN UINT16 Value\r |
| 357 | )\r |
| 358 | ;\r |
| 359 | \r |
| 360 | /**\r |
| 361 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.\r |
| 362 | \r |
| 363 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 364 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 365 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 366 | The value written to the PCI configuration register is returned.\r |
| 367 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 368 | If any reserved bits in Address are set, then ASSERT().\r |
| 369 | \r |
| 370 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 371 | @param OrData The value to OR with the PCI configuration register.\r |
| 372 | \r |
| 373 | @return The value written to the PCI configuration register.\r |
| 374 | \r |
| 375 | **/\r |
| 376 | UINT16\r |
| 377 | EFIAPI\r |
| 378 | PciSegmentOr16 (\r |
| 379 | IN UINT64 Address,\r |
| 380 | IN UINT16 OrData\r |
| 381 | )\r |
| 382 | ;\r |
| 383 | \r |
| 384 | /**\r |
| 385 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r |
| 386 | \r |
| 387 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 388 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 389 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 390 | The value written to the PCI configuration register is returned.\r |
| 391 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 392 | If any reserved bits in Address are set, then ASSERT().\r |
| 393 | \r |
| 394 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 395 | @param Andata The value to AND with the PCI configuration register.\r |
| 396 | \r |
| 397 | @return The value written to the PCI configuration register.\r |
| 398 | \r |
| 399 | **/\r |
| 400 | UINT16\r |
| 401 | EFIAPI\r |
| 402 | PciSegmentAnd16 (\r |
| 403 | IN UINT64 Address,\r |
| 404 | IN UINT16 AndData\r |
| 405 | )\r |
| 406 | ;\r |
| 407 | \r |
| 408 | /**\r |
| 409 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r |
| 410 | followed a bitwise inclusive OR with another 16-bit value.\r |
| 411 | \r |
| 412 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 413 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 414 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r |
| 415 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 416 | The value written to the PCI configuration register is returned.\r |
| 417 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 418 | If any reserved bits in Address are set, then ASSERT().\r |
| 419 | \r |
| 420 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 421 | @param Andata The value to AND with the PCI configuration register.\r |
| 422 | @param OrData The value to OR with the PCI configuration register.\r |
| 423 | \r |
| 424 | @return The value written to the PCI configuration register.\r |
| 425 | \r |
| 426 | **/\r |
| 427 | UINT16\r |
| 428 | EFIAPI\r |
| 429 | PciSegmentAndThenOr16 (\r |
| 430 | IN UINT64 Address,\r |
| 431 | IN UINT16 AndData,\r |
| 432 | IN UINT16 OrData\r |
| 433 | )\r |
| 434 | ;\r |
| 435 | \r |
| 436 | /**\r |
| 437 | Reads a bit field of a PCI configuration register.\r |
| 438 | \r |
| 439 | Reads the bit field in a 16-bit PCI configuration register.\r |
| 440 | The bit field is specified by the StartBit and the EndBit.\r |
| 441 | The value of the bit field is returned.\r |
| 442 | If any reserved bits in Address are set, then ASSERT().\r |
| 443 | If StartBit is greater than 7, then ASSERT().\r |
| 444 | If EndBit is greater than 7, then ASSERT().\r |
| 445 | If EndBit is less than StartBit, then ASSERT().\r |
| 446 | \r |
| 447 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 448 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 449 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 450 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 451 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 452 | \r |
| 453 | @return The value of the bit field.\r |
| 454 | \r |
| 455 | **/\r |
| 456 | UINT16\r |
| 457 | EFIAPI\r |
| 458 | PciSegmentBitFieldRead16 (\r |
| 459 | IN UINT64 Address,\r |
| 460 | IN UINTN StartBit,\r |
| 461 | IN UINTN EndBit\r |
| 462 | )\r |
| 463 | ;\r |
| 464 | \r |
| 465 | /**\r |
| 466 | Writes a bit field to a PCI configuration register.\r |
| 467 | \r |
| 468 | Writes Value to the bit field of the PCI configuration register.\r |
| 469 | The bit field is specified by the StartBit and the EndBit.\r |
| 470 | All other bits in the destination PCI configuration register are preserved.\r |
| 471 | The new value of the 16-bit register is returned.\r |
| 472 | If any reserved bits in Address are set, then ASSERT().\r |
| 473 | If StartBit is greater than 7, then ASSERT().\r |
| 474 | If EndBit is greater than 7, then ASSERT().\r |
| 475 | If EndBit is less than StartBit, then ASSERT().\r |
| 476 | \r |
| 477 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 478 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 479 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 480 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 481 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 482 | @param Value New value of the bit field.\r |
| 483 | \r |
| 484 | @return The new value of the 16-bit register.\r |
| 485 | \r |
| 486 | **/\r |
| 487 | UINT16\r |
| 488 | EFIAPI\r |
| 489 | PciSegmentBitFieldWrite16 (\r |
| 490 | IN UINT64 Address,\r |
| 491 | IN UINTN StartBit,\r |
| 492 | IN UINTN EndBit,\r |
| 493 | IN UINT16 Value\r |
| 494 | )\r |
| 495 | ;\r |
| 496 | \r |
| 497 | /**\r |
| 498 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 499 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 500 | and writes the result to the 16-bit PCI configuration register specified by Address. \r |
| 501 | \r |
| 502 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 503 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 504 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 505 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 506 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 507 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 508 | \r |
| 509 | @return The value written to the PCI configuration register.\r |
| 510 | \r |
| 511 | **/\r |
| 512 | UINT16\r |
| 513 | EFIAPI\r |
| 514 | PciSegmentBitFieldOr16 (\r |
| 515 | IN UINT64 Address,\r |
| 516 | IN UINTN StartBit,\r |
| 517 | IN UINTN EndBit,\r |
| 518 | IN UINT16 OrData\r |
| 519 | )\r |
| 520 | ;\r |
| 521 | \r |
| 522 | /**\r |
| 523 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r |
| 524 | and writes the result back to the bit field in the 16-bit port.\r |
| 525 | \r |
| 526 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 527 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 528 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 529 | The value written to the PCI configuration register is returned.\r |
| 530 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 531 | Extra left bits in OrData are stripped.\r |
| 532 | If any reserved bits in Address are set, then ASSERT().\r |
| 533 | If StartBit is greater than 7, then ASSERT().\r |
| 534 | If EndBit is greater than 7, then ASSERT().\r |
| 535 | If EndBit is less than StartBit, then ASSERT().\r |
| 536 | \r |
| 537 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 538 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 539 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 540 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 541 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 542 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 543 | \r |
| 544 | @return The value written to the PCI configuration register.\r |
| 545 | \r |
| 546 | **/\r |
| 547 | UINT16\r |
| 548 | EFIAPI\r |
| 549 | PciSegmentBitFieldAnd16 (\r |
| 550 | IN UINT64 Address,\r |
| 551 | IN UINTN StartBit,\r |
| 552 | IN UINTN EndBit,\r |
| 553 | IN UINT16 AndData\r |
| 554 | )\r |
| 555 | ;\r |
| 556 | \r |
| 557 | /**\r |
| 558 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,\r |
| 559 | and writes the result back to the bit field in the 16-bit register.\r |
| 560 | \r |
| 561 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 562 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 563 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 564 | The value written to the PCI configuration register is returned.\r |
| 565 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 566 | Extra left bits in AndData are stripped.\r |
| 567 | If any reserved bits in Address are set, then ASSERT().\r |
| 568 | If StartBit is greater than 7, then ASSERT().\r |
| 569 | If EndBit is greater than 7, then ASSERT().\r |
| 570 | If EndBit is less than StartBit, then ASSERT().\r |
| 571 | \r |
| 572 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 573 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 574 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 575 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 576 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 577 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 578 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 579 | \r |
| 580 | @return The value written to the PCI configuration register.\r |
| 581 | \r |
| 582 | **/\r |
| 583 | UINT16\r |
| 584 | EFIAPI\r |
| 585 | PciSegmentBitFieldAndThenOr16 (\r |
| 586 | IN UINT64 Address,\r |
| 587 | IN UINTN StartBit,\r |
| 588 | IN UINTN EndBit,\r |
| 589 | IN UINT16 AndData,\r |
| 590 | IN UINT16 OrData\r |
| 591 | )\r |
| 592 | ;\r |
| 593 | \r |
| 594 | /**\r |
| 595 | Reads a 32-bit PCI configuration register.\r |
| 596 | \r |
| 597 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 598 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 599 | If any reserved bits in Address are set, then ASSERT().\r |
| 600 | \r |
| 601 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 602 | \r |
| 603 | @return The 32-bit PCI configuration register specified by Address.\r |
| 604 | \r |
| 605 | **/\r |
| 606 | UINT32\r |
| 607 | EFIAPI\r |
| 608 | PciSegmentRead32 (\r |
| 609 | IN UINT64 Address\r |
| 610 | )\r |
| 611 | ;\r |
| 612 | \r |
| 613 | /**\r |
| 614 | Writes a 32-bit PCI configuration register.\r |
| 615 | \r |
| 616 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r |
| 617 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| 618 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 619 | \r |
| 620 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 621 | @param Value The value to write.\r |
| 622 | \r |
| 623 | @return The parameter of Value.\r |
| 624 | \r |
| 625 | **/\r |
| 626 | UINT32\r |
| 627 | EFIAPI\r |
| 628 | PciSegmentWrite32 (\r |
| 629 | IN UINT64 Address,\r |
| 630 | IN UINT32 Value\r |
| 631 | )\r |
| 632 | ;\r |
| 633 | \r |
| 634 | /**\r |
| 635 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.\r |
| 636 | \r |
| 637 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 638 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 639 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 640 | The value written to the PCI configuration register is returned.\r |
| 641 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 642 | If any reserved bits in Address are set, then ASSERT().\r |
| 643 | \r |
| 644 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 645 | @param OrData The value to OR with the PCI configuration register.\r |
| 646 | \r |
| 647 | @return The value written to the PCI configuration register.\r |
| 648 | \r |
| 649 | **/\r |
| 650 | UINT32\r |
| 651 | EFIAPI\r |
| 652 | PciSegmentOr32 (\r |
| 653 | IN UINT64 Address,\r |
| 654 | IN UINT32 OrData\r |
| 655 | )\r |
| 656 | ;\r |
| 657 | \r |
| 658 | /**\r |
| 659 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r |
| 660 | \r |
| 661 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 662 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 663 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 664 | The value written to the PCI configuration register is returned.\r |
| 665 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 666 | If any reserved bits in Address are set, then ASSERT().\r |
| 667 | \r |
| 668 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 669 | @param Andata The value to AND with the PCI configuration register.\r |
| 670 | \r |
| 671 | @return The value written to the PCI configuration register.\r |
| 672 | \r |
| 673 | **/\r |
| 674 | UINT32\r |
| 675 | EFIAPI\r |
| 676 | PciSegmentAnd32 (\r |
| 677 | IN UINT64 Address,\r |
| 678 | IN UINT32 AndData\r |
| 679 | )\r |
| 680 | ;\r |
| 681 | \r |
| 682 | /**\r |
| 683 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r |
| 684 | followed a bitwise inclusive OR with another 32-bit value.\r |
| 685 | \r |
| 686 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 687 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 688 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r |
| 689 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 690 | The value written to the PCI configuration register is returned.\r |
| 691 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 692 | If any reserved bits in Address are set, then ASSERT().\r |
| 693 | \r |
| 694 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 695 | @param Andata The value to AND with the PCI configuration register.\r |
| 696 | @param OrData The value to OR with the PCI configuration register.\r |
| 697 | \r |
| 698 | @return The value written to the PCI configuration register.\r |
| 699 | \r |
| 700 | **/\r |
| 701 | UINT32\r |
| 702 | EFIAPI\r |
| 703 | PciSegmentAndThenOr32 (\r |
| 704 | IN UINT64 Address,\r |
| 705 | IN UINT32 AndData,\r |
| 706 | IN UINT32 OrData\r |
| 707 | )\r |
| 708 | ;\r |
| 709 | \r |
| 710 | /**\r |
| 711 | Reads a bit field of a PCI configuration register.\r |
| 712 | \r |
| 713 | Reads the bit field in a 32-bit PCI configuration register.\r |
| 714 | The bit field is specified by the StartBit and the EndBit.\r |
| 715 | The value of the bit field is returned.\r |
| 716 | If any reserved bits in Address are set, then ASSERT().\r |
| 717 | If StartBit is greater than 7, then ASSERT().\r |
| 718 | If EndBit is greater than 7, then ASSERT().\r |
| 719 | If EndBit is less than StartBit, then ASSERT().\r |
| 720 | \r |
| 721 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 722 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 723 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 724 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 725 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 726 | \r |
| 727 | @return The value of the bit field.\r |
| 728 | \r |
| 729 | **/\r |
| 730 | UINT32\r |
| 731 | EFIAPI\r |
| 732 | PciSegmentBitFieldRead32 (\r |
| 733 | IN UINT64 Address,\r |
| 734 | IN UINTN StartBit,\r |
| 735 | IN UINTN EndBit\r |
| 736 | )\r |
| 737 | ;\r |
| 738 | \r |
| 739 | /**\r |
| 740 | Writes a bit field to a PCI configuration register.\r |
| 741 | \r |
| 742 | Writes Value to the bit field of the PCI configuration register.\r |
| 743 | The bit field is specified by the StartBit and the EndBit.\r |
| 744 | All other bits in the destination PCI configuration register are preserved.\r |
| 745 | The new value of the 32-bit register is returned.\r |
| 746 | If any reserved bits in Address are set, then ASSERT().\r |
| 747 | If StartBit is greater than 7, then ASSERT().\r |
| 748 | If EndBit is greater than 7, then ASSERT().\r |
| 749 | If EndBit is less than StartBit, then ASSERT().\r |
| 750 | \r |
| 751 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 752 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 753 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 754 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 755 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 756 | @param Value New value of the bit field.\r |
| 757 | \r |
| 758 | @return The new value of the 32-bit register.\r |
| 759 | \r |
| 760 | **/\r |
| 761 | UINT32\r |
| 762 | EFIAPI\r |
| 763 | PciSegmentBitFieldWrite32 (\r |
| 764 | IN UINT64 Address,\r |
| 765 | IN UINTN StartBit,\r |
| 766 | IN UINTN EndBit,\r |
| 767 | IN UINT32 Value\r |
| 768 | )\r |
| 769 | ;\r |
| 770 | \r |
| 771 | /**\r |
| 772 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 773 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 774 | and writes the result to the 32-bit PCI configuration register specified by Address. \r |
| 775 | \r |
| 776 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 777 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 778 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 779 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 780 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 781 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 782 | \r |
| 783 | @return The value written to the PCI configuration register.\r |
| 784 | \r |
| 785 | **/\r |
| 786 | UINT32\r |
| 787 | EFIAPI\r |
| 788 | PciSegmentBitFieldOr32 (\r |
| 789 | IN UINT64 Address,\r |
| 790 | IN UINTN StartBit,\r |
| 791 | IN UINTN EndBit,\r |
| 792 | IN UINT32 OrData\r |
| 793 | )\r |
| 794 | ;\r |
| 795 | \r |
| 796 | /**\r |
| 797 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,\r |
| 798 | and writes the result back to the bit field in the 32-bit port.\r |
| 799 | \r |
| 800 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 801 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 802 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 803 | The value written to the PCI configuration register is returned.\r |
| 804 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 805 | Extra left bits in OrData are stripped.\r |
| 806 | If any reserved bits in Address are set, then ASSERT().\r |
| 807 | If StartBit is greater than 7, then ASSERT().\r |
| 808 | If EndBit is greater than 7, then ASSERT().\r |
| 809 | If EndBit is less than StartBit, then ASSERT().\r |
| 810 | \r |
| 811 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 812 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 813 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 814 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 815 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 816 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 817 | \r |
| 818 | @return The value written to the PCI configuration register.\r |
| 819 | \r |
| 820 | **/\r |
| 821 | UINT32\r |
| 822 | EFIAPI\r |
| 823 | PciSegmentBitFieldAnd32 (\r |
| 824 | IN UINT64 Address,\r |
| 825 | IN UINTN StartBit,\r |
| 826 | IN UINTN EndBit,\r |
| 827 | IN UINT32 AndData\r |
| 828 | )\r |
| 829 | ;\r |
| 830 | \r |
| 831 | /**\r |
| 832 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,\r |
| 833 | and writes the result back to the bit field in the 32-bit register.\r |
| 834 | \r |
| 835 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 836 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 837 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 838 | The value written to the PCI configuration register is returned.\r |
| 839 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 840 | Extra left bits in AndData are stripped.\r |
| 841 | If any reserved bits in Address are set, then ASSERT().\r |
| 842 | If StartBit is greater than 7, then ASSERT().\r |
| 843 | If EndBit is greater than 7, then ASSERT().\r |
| 844 | If EndBit is less than StartBit, then ASSERT().\r |
| 845 | \r |
| 846 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 847 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 848 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 849 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 850 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 851 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 852 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 853 | \r |
| 854 | @return The value written to the PCI configuration register.\r |
| 855 | \r |
| 856 | **/\r |
| 857 | UINT32\r |
| 858 | EFIAPI\r |
| 859 | PciSegmentBitFieldAndThenOr32 (\r |
| 860 | IN UINT64 Address,\r |
| 861 | IN UINTN StartBit,\r |
| 862 | IN UINTN EndBit,\r |
| 863 | IN UINT32 AndData,\r |
| 864 | IN UINT32 OrData\r |
| 865 | )\r |
| 866 | ;\r |
| 867 | \r |
| 868 | /**\r |
| 869 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 870 | \r |
| 871 | Reads the range of PCI configuration registers specified by StartAddress\r |
| 872 | and Size into the buffer specified by Buffer.\r |
| 873 | This function only allows the PCI configuration registers from a single PCI function to be read.\r |
| 874 | Size is returned.\r |
| 875 | If any reserved bits in StartAddress are set, then ASSERT().\r |
| 876 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 877 | If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r |
| 878 | If Buffer is NULL, then ASSERT().\r |
| 879 | \r |
| 880 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 881 | @param Size Size in bytes of the transfer.\r |
| 882 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 883 | \r |
| 884 | @return The paramter of Size.\r |
| 885 | \r |
| 886 | **/\r |
| 887 | UINTN\r |
| 888 | EFIAPI\r |
| 889 | PciSegmentReadBuffer (\r |
| 890 | IN UINT64 StartAddress,\r |
| 891 | IN UINTN Size,\r |
| 892 | OUT VOID *Buffer\r |
| 893 | )\r |
| 894 | ;\r |
| 895 | \r |
| 896 | /**\r |
| 897 | Copies the data in a caller supplied buffer to a specified range of PCI configuration space.\r |
| 898 | \r |
| 899 | Writes the range of PCI configuration registers specified by StartAddress\r |
| 900 | and Size from the buffer specified by Buffer.\r |
| 901 | This function only allows the PCI configuration registers from a single PCI function to be written.\r |
| 902 | Size is returned.\r |
| 903 | If any reserved bits in StartAddress are set, then ASSERT().\r |
| 904 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 905 | If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r |
| 906 | If Buffer is NULL, then ASSERT().\r |
| 907 | \r |
| 908 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 909 | @param Size Size in bytes of the transfer.\r |
| 910 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 911 | \r |
| 912 | @return The paramter of Size.\r |
| 913 | \r |
| 914 | **/\r |
| 915 | UINTN\r |
| 916 | EFIAPI\r |
| 917 | PciSegmentWriteBuffer (\r |
| 918 | IN UINT64 StartAddress,\r |
| 919 | IN UINTN Size,\r |
| 920 | IN VOID *Buffer\r |
| 921 | )\r |
| 922 | ;\r |
| 923 | \r |
| 924 | #endif\r |
projects / mirror_edk2.git / blame