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1 | /** @file\r |
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2 | Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r |
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3 | \r |
4 | The PCI Segment Library function provide services to read, write, and modify the PCI configuration\r |
5 | registers on PCI root bridges on any supported PCI segment. These library services take a single \r |
6 | address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register. \r |
7 | The layout of this address parameter is as follows:\r |
8 | \r |
9 | PCI Register: Bits 0..11\r |
10 | PCI Function Bits 12..14\r |
11 | PCI Device Bits 15..19\r |
12 | PCI Bus Bits 20..27\r |
13 | Reserved Bits 28..31. Must be 0.\r |
14 | PCI Segment Bits 32..47\r |
15 | Reserved Bits 48..63. Must be 0.\r |
16 | \r |
17 | | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r |
18 | 63 48 47 32 31 28 27 20 19 15 14 12 11 0\r |
19 | \r |
20 | These functions perform PCI configuration cycles using the default PCI configuration access \r |
21 | method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it \r |
22 | may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate \r |
23 | access method. Modules will typically use the PCI Segment Library for its PCI configuration \r |
24 | accesses when PCI Segments other than Segment #0 must be accessed. \r |
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25 | \r |
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26 | Copyright (c) 2006 - 2008, Intel Corporation\r |
27 | All rights reserved. This program and the accompanying materials\r |
28 | are licensed and made available under the terms and conditions of the BSD License\r |
29 | which accompanies this distribution. The full text of the license may be found at\r |
30 | http://opensource.org/licenses/bsd-license.php\r |
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31 | \r |
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32 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
33 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
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34 | \r |
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35 | **/\r |
36 | \r |
37 | #ifndef __PCI_SEGMENT_LIB__\r |
38 | #define __PCI_SEGMENT_LIB__\r |
39 | \r |
40 | \r |
41 | /**\r |
42 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r |
43 | and PCI Register to an address that can be passed to the PCI Segment Library functions.\r |
44 | \r |
45 | Computes an address that is compatible with the PCI Segment Library functions.\r |
46 | The unused upper bits of Segment, Bus, Device, Function,\r |
47 | and Register are stripped prior to the generation of the address.\r |
48 | \r |
49 | @param Segment PCI Segment number. Range 0..65535.\r |
50 | @param Bus PCI Bus number. Range 0..255.\r |
51 | @param Device PCI Device number. Range 0..31.\r |
52 | @param Function PCI Function number. Range 0..7.\r |
53 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r |
54 | \r |
55 | @return The address that is compatible with the PCI Segment Library functions.\r |
56 | \r |
57 | **/\r |
58 | #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r |
59 | ( ((Register) & 0xfff) | \\r |
60 | (((Function) & 0x07) << 12) | \\r |
61 | (((Device) & 0x1f) << 15) | \\r |
62 | (((Bus) & 0xff) << 20) | \\r |
63 | (LShiftU64((Segment) & 0xffff, 32)) \\r |
64 | )\r |
65 | \r |
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66 | /**\r |
67 | Register a PCI device so PCI configuration registers may be accessed after \r |
68 | SetVirtualAddressMap().\r |
69 | \r |
70 | If Address > 0x0FFFFFFF, then ASSERT().\r |
71 | \r |
72 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
73 | Register.\r |
74 | \r |
75 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
76 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r |
77 | after ExitBootServices().\r |
78 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r |
79 | at runtime could not be mapped.\r |
80 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r |
81 | complete the registration.\r |
82 | \r |
83 | **/\r |
84 | RETURN_STATUS\r |
85 | EFIAPI\r |
86 | PciSegmentRegisterForRuntimeAccess (\r |
87 | IN UINTN Address\r |
88 | );\r |
89 | \r |
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90 | /**\r |
91 | Reads an 8-bit PCI configuration register.\r |
92 | \r |
93 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
94 | This function must guarantee that all PCI read and write operations are serialized.\r |
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95 | \r |
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96 | If any reserved bits in Address are set, then ASSERT().\r |
97 | \r |
98 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
99 | \r |
100 | @return The 8-bit PCI configuration register specified by Address.\r |
101 | \r |
102 | **/\r |
103 | UINT8\r |
104 | EFIAPI\r |
105 | PciSegmentRead8 (\r |
106 | IN UINT64 Address\r |
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107 | );\r |
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108 | \r |
109 | /**\r |
110 | Writes an 8-bit PCI configuration register.\r |
111 | \r |
112 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r |
113 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
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114 | \r |
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115 | If Address > 0x0FFFFFFF, then ASSERT().\r |
116 | \r |
117 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
118 | @param Value The value to write.\r |
119 | \r |
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120 | @return The value written to the PCI configuration register.\r |
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121 | \r |
122 | **/\r |
123 | UINT8\r |
124 | EFIAPI\r |
125 | PciSegmentWrite8 (\r |
126 | IN UINT64 Address,\r |
127 | IN UINT8 Value\r |
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128 | );\r |
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129 | \r |
130 | /**\r |
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131 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r |
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132 | \r |
133 | Reads the 8-bit PCI configuration register specified by Address,\r |
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134 | performs a bitwise OR between the read result and the value specified by OrData,\r |
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135 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
136 | The value written to the PCI configuration register is returned.\r |
137 | This function must guarantee that all PCI read and write operations are serialized.\r |
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138 | \r |
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139 | If any reserved bits in Address are set, then ASSERT().\r |
140 | \r |
141 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
142 | @param OrData The value to OR with the PCI configuration register.\r |
143 | \r |
144 | @return The value written to the PCI configuration register.\r |
145 | \r |
146 | **/\r |
147 | UINT8\r |
148 | EFIAPI\r |
149 | PciSegmentOr8 (\r |
150 | IN UINT64 Address,\r |
151 | IN UINT8 OrData\r |
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152 | );\r |
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153 | \r |
154 | /**\r |
155 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r |
156 | \r |
157 | Reads the 8-bit PCI configuration register specified by Address,\r |
158 | performs a bitwise AND between the read result and the value specified by AndData,\r |
159 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
160 | The value written to the PCI configuration register is returned.\r |
161 | This function must guarantee that all PCI read and write operations are serialized.\r |
162 | If any reserved bits in Address are set, then ASSERT().\r |
163 | \r |
164 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
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165 | @param AndData The value to AND with the PCI configuration register.\r |
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166 | \r |
167 | @return The value written to the PCI configuration register.\r |
168 | \r |
169 | **/\r |
170 | UINT8\r |
171 | EFIAPI\r |
172 | PciSegmentAnd8 (\r |
173 | IN UINT64 Address,\r |
174 | IN UINT8 AndData\r |
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175 | );\r |
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176 | \r |
177 | /**\r |
178 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r |
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179 | followed a bitwise OR with another 8-bit value.\r |
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180 | \r |
181 | Reads the 8-bit PCI configuration register specified by Address,\r |
182 | performs a bitwise AND between the read result and the value specified by AndData,\r |
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183 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
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184 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
185 | The value written to the PCI configuration register is returned.\r |
186 | This function must guarantee that all PCI read and write operations are serialized.\r |
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187 | \r |
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188 | If any reserved bits in Address are set, then ASSERT().\r |
189 | \r |
190 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
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191 | @param AndData The value to AND with the PCI configuration register.\r |
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192 | @param OrData The value to OR with the PCI configuration register.\r |
193 | \r |
194 | @return The value written to the PCI configuration register.\r |
195 | \r |
196 | **/\r |
197 | UINT8\r |
198 | EFIAPI\r |
199 | PciSegmentAndThenOr8 (\r |
200 | IN UINT64 Address,\r |
201 | IN UINT8 AndData,\r |
202 | IN UINT8 OrData\r |
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203 | );\r |
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204 | \r |
205 | /**\r |
206 | Reads a bit field of a PCI configuration register.\r |
207 | \r |
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208 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
209 | specified by the StartBit and the EndBit. The value of the bit field is\r |
210 | returned.\r |
211 | \r |
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212 | If any reserved bits in Address are set, then ASSERT().\r |
213 | If StartBit is greater than 7, then ASSERT().\r |
214 | If EndBit is greater than 7, then ASSERT().\r |
215 | If EndBit is less than StartBit, then ASSERT().\r |
216 | \r |
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217 | @param Address PCI configuration register to read.\r |
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218 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
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219 | Range 0..7.\r |
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220 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
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221 | Range 0..7.\r |
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222 | \r |
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223 | @return The value of the bit field read from the PCI configuration register.\r |
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224 | \r |
225 | **/\r |
226 | UINT8\r |
227 | EFIAPI\r |
228 | PciSegmentBitFieldRead8 (\r |
229 | IN UINT64 Address,\r |
230 | IN UINTN StartBit,\r |
231 | IN UINTN EndBit\r |
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232 | );\r |
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233 | \r |
234 | /**\r |
235 | Writes a bit field to a PCI configuration register.\r |
236 | \r |
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237 | Writes Value to the bit field of the PCI configuration register. The bit\r |
238 | field is specified by the StartBit and the EndBit. All other bits in the\r |
239 | destination PCI configuration register are preserved. The new value of the\r |
240 | 8-bit register is returned.\r |
241 | \r |
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242 | If any reserved bits in Address are set, then ASSERT().\r |
243 | If StartBit is greater than 7, then ASSERT().\r |
244 | If EndBit is greater than 7, then ASSERT().\r |
245 | If EndBit is less than StartBit, then ASSERT().\r |
246 | \r |
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247 | @param Address PCI configuration register to write.\r |
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248 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
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249 | Range 0..7.\r |
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250 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
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251 | Range 0..7.\r |
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252 | @param Value New value of the bit field.\r |
253 | \r |
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254 | @return The value written back to the PCI configuration register.\r |
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255 | \r |
256 | **/\r |
257 | UINT8\r |
258 | EFIAPI\r |
259 | PciSegmentBitFieldWrite8 (\r |
260 | IN UINT64 Address,\r |
261 | IN UINTN StartBit,\r |
262 | IN UINTN EndBit,\r |
263 | IN UINT8 Value\r |
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264 | );\r |
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265 | \r |
266 | /**\r |
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267 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
268 | writes the result back to the bit field in the 8-bit port.\r |
269 | \r |
270 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
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271 | bitwise OR between the read result and the value specified by\r |
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272 | OrData, and writes the result to the 8-bit PCI configuration register\r |
273 | specified by Address. The value written to the PCI configuration register is\r |
274 | returned. This function must guarantee that all PCI read and write operations\r |
275 | are serialized. Extra left bits in OrData are stripped.\r |
276 | \r |
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277 | If any reserved bits in Address are set, then ASSERT().\r |
278 | If StartBit is greater than 7, then ASSERT().\r |
279 | If EndBit is greater than 7, then ASSERT().\r |
280 | If EndBit is less than StartBit, then ASSERT().\r |
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281 | \r |
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282 | @param Address PCI configuration register to write.\r |
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283 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
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284 | Range 0..7.\r |
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285 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
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286 | Range 0..7.\r |
287 | @param OrData The value to OR with the PCI configuration register.\r |
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288 | \r |
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289 | @return The value written back to the PCI configuration register.\r |
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290 | \r |
291 | **/\r |
292 | UINT8\r |
293 | EFIAPI\r |
294 | PciSegmentBitFieldOr8 (\r |
295 | IN UINT64 Address,\r |
296 | IN UINTN StartBit,\r |
297 | IN UINTN EndBit,\r |
298 | IN UINT8 OrData\r |
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299 | );\r |
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300 | \r |
301 | /**\r |
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302 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
303 | AND, and writes the result back to the bit field in the 8-bit register.\r |
304 | \r |
305 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
306 | bitwise AND between the read result and the value specified by AndData, and\r |
307 | writes the result to the 8-bit PCI configuration register specified by\r |
308 | Address. The value written to the PCI configuration register is returned.\r |
309 | This function must guarantee that all PCI read and write operations are\r |
310 | serialized. Extra left bits in AndData are stripped.\r |
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311 | \r |
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312 | If any reserved bits in Address are set, then ASSERT().\r |
313 | If StartBit is greater than 7, then ASSERT().\r |
314 | If EndBit is greater than 7, then ASSERT().\r |
315 | If EndBit is less than StartBit, then ASSERT().\r |
316 | \r |
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317 | @param Address PCI configuration register to write.\r |
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318 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
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319 | Range 0..7.\r |
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320 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
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321 | Range 0..7.\r |
322 | @param AndData The value to AND with the PCI configuration register.\r |
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323 | \r |
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324 | @return The value written back to the PCI configuration register.\r |
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325 | \r |
326 | **/\r |
327 | UINT8\r |
328 | EFIAPI\r |
329 | PciSegmentBitFieldAnd8 (\r |
330 | IN UINT64 Address,\r |
331 | IN UINTN StartBit,\r |
332 | IN UINTN EndBit,\r |
333 | IN UINT8 AndData\r |
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334 | );\r |
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335 | \r |
336 | /**\r |
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337 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
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338 | bitwise OR, and writes the result back to the bit field in the\r |
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339 | 8-bit port.\r |
340 | \r |
341 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
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342 | bitwise AND followed by a bitwise OR between the read result and\r |
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343 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
344 | configuration register specified by Address. The value written to the PCI\r |
345 | configuration register is returned. This function must guarantee that all PCI\r |
346 | read and write operations are serialized. Extra left bits in both AndData and\r |
347 | OrData are stripped.\r |
348 | \r |
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349 | If any reserved bits in Address are set, then ASSERT().\r |
350 | If StartBit is greater than 7, then ASSERT().\r |
351 | If EndBit is greater than 7, then ASSERT().\r |
352 | If EndBit is less than StartBit, then ASSERT().\r |
353 | \r |
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354 | @param Address PCI configuration register to write.\r |
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355 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
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356 | Range 0..7.\r |
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357 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
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358 | Range 0..7.\r |
359 | @param AndData The value to AND with the PCI configuration register.\r |
360 | @param OrData The value to OR with the result of the AND operation.\r |
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361 | \r |
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362 | @return The value written back to the PCI configuration register.\r |
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363 | \r |
364 | **/\r |
365 | UINT8\r |
366 | EFIAPI\r |
367 | PciSegmentBitFieldAndThenOr8 (\r |
368 | IN UINT64 Address,\r |
369 | IN UINTN StartBit,\r |
370 | IN UINTN EndBit,\r |
371 | IN UINT8 AndData,\r |
372 | IN UINT8 OrData\r |
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373 | );\r |
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374 | \r |
375 | /**\r |
376 | Reads a 16-bit PCI configuration register.\r |
377 | \r |
378 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
379 | This function must guarantee that all PCI read and write operations are serialized.\r |
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380 | \r |
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381 | If any reserved bits in Address are set, then ASSERT().\r |
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382 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
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383 | \r |
384 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
385 | \r |
386 | @return The 16-bit PCI configuration register specified by Address.\r |
387 | \r |
388 | **/\r |
389 | UINT16\r |
390 | EFIAPI\r |
391 | PciSegmentRead16 (\r |
392 | IN UINT64 Address\r |
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393 | );\r |
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394 | \r |
395 | /**\r |
396 | Writes a 16-bit PCI configuration register.\r |
397 | \r |
398 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r |
399 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
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400 | \r |
401 | If any reserved bits in Address are set, then ASSERT().\r |
402 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
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403 | \r |
404 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
405 | @param Value The value to write.\r |
406 | \r |
407 | @return The parameter of Value.\r |
408 | \r |
409 | **/\r |
410 | UINT16\r |
411 | EFIAPI\r |
412 | PciSegmentWrite16 (\r |
413 | IN UINT64 Address,\r |
414 | IN UINT16 Value\r |
ed66e1bc |
415 | );\r |
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416 | \r |
417 | /**\r |
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418 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
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419 | a 16-bit value.\r |
420 | \r |
421 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
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422 | bitwise OR between the read result and the value specified by\r |
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423 | OrData, and writes the result to the 16-bit PCI configuration register\r |
424 | specified by Address. The value written to the PCI configuration register is\r |
425 | returned. This function must guarantee that all PCI read and write operations\r |
426 | are serialized.\r |
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427 | \r |
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428 | If any reserved bits in Address are set, then ASSERT().\r |
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429 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
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430 | \r |
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431 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
432 | Register.\r |
433 | @param OrData The value to OR with the PCI configuration register.\r |
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434 | \r |
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435 | @return The value written back to the PCI configuration register.\r |
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436 | \r |
437 | **/\r |
438 | UINT16\r |
439 | EFIAPI\r |
440 | PciSegmentOr16 (\r |
441 | IN UINT64 Address,\r |
442 | IN UINT16 OrData\r |
ed66e1bc |
443 | );\r |
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444 | \r |
445 | /**\r |
446 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r |
447 | \r |
448 | Reads the 16-bit PCI configuration register specified by Address,\r |
449 | performs a bitwise AND between the read result and the value specified by AndData,\r |
450 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
451 | The value written to the PCI configuration register is returned.\r |
452 | This function must guarantee that all PCI read and write operations are serialized.\r |
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453 | \r |
fb3df220 |
454 | If any reserved bits in Address are set, then ASSERT().\r |
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455 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
456 | \r |
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457 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
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458 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 |
459 | \r |
460 | @return The value written to the PCI configuration register.\r |
461 | \r |
462 | **/\r |
463 | UINT16\r |
464 | EFIAPI\r |
465 | PciSegmentAnd16 (\r |
466 | IN UINT64 Address,\r |
467 | IN UINT16 AndData\r |
ed66e1bc |
468 | );\r |
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469 | \r |
470 | /**\r |
471 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r |
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472 | followed a bitwise OR with another 16-bit value.\r |
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473 | \r |
474 | Reads the 16-bit PCI configuration register specified by Address,\r |
475 | performs a bitwise AND between the read result and the value specified by AndData,\r |
62991af2 |
476 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
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477 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
478 | The value written to the PCI configuration register is returned.\r |
479 | This function must guarantee that all PCI read and write operations are serialized.\r |
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480 | \r |
fb3df220 |
481 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 |
482 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
fb3df220 |
483 | \r |
484 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
42eedea9 |
485 | @param AndData The value to AND with the PCI configuration register.\r |
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486 | @param OrData The value to OR with the PCI configuration register.\r |
487 | \r |
488 | @return The value written to the PCI configuration register.\r |
489 | \r |
490 | **/\r |
491 | UINT16\r |
492 | EFIAPI\r |
493 | PciSegmentAndThenOr16 (\r |
494 | IN UINT64 Address,\r |
495 | IN UINT16 AndData,\r |
496 | IN UINT16 OrData\r |
ed66e1bc |
497 | );\r |
fb3df220 |
498 | \r |
499 | /**\r |
500 | Reads a bit field of a PCI configuration register.\r |
501 | \r |
d5979dc0 |
502 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
503 | specified by the StartBit and the EndBit. The value of the bit field is\r |
504 | returned.\r |
505 | \r |
fb3df220 |
506 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 |
507 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
d5979dc0 |
508 | If StartBit is greater than 15, then ASSERT().\r |
509 | If EndBit is greater than 15, then ASSERT().\r |
fb3df220 |
510 | If EndBit is less than StartBit, then ASSERT().\r |
511 | \r |
d5979dc0 |
512 | @param Address PCI configuration register to read.\r |
fb3df220 |
513 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 |
514 | Range 0..15.\r |
fb3df220 |
515 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 |
516 | Range 0..15.\r |
fb3df220 |
517 | \r |
d5979dc0 |
518 | @return The value of the bit field read from the PCI configuration register.\r |
fb3df220 |
519 | \r |
520 | **/\r |
521 | UINT16\r |
522 | EFIAPI\r |
523 | PciSegmentBitFieldRead16 (\r |
524 | IN UINT64 Address,\r |
525 | IN UINTN StartBit,\r |
526 | IN UINTN EndBit\r |
ed66e1bc |
527 | );\r |
fb3df220 |
528 | \r |
529 | /**\r |
530 | Writes a bit field to a PCI configuration register.\r |
531 | \r |
d5979dc0 |
532 | Writes Value to the bit field of the PCI configuration register. The bit\r |
533 | field is specified by the StartBit and the EndBit. All other bits in the\r |
534 | destination PCI configuration register are preserved. The new value of the\r |
535 | 16-bit register is returned.\r |
536 | \r |
fb3df220 |
537 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 |
538 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
d5979dc0 |
539 | If StartBit is greater than 15, then ASSERT().\r |
540 | If EndBit is greater than 15, then ASSERT().\r |
fb3df220 |
541 | If EndBit is less than StartBit, then ASSERT().\r |
542 | \r |
d5979dc0 |
543 | @param Address PCI configuration register to write.\r |
fb3df220 |
544 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 |
545 | Range 0..15.\r |
fb3df220 |
546 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 |
547 | Range 0..15.\r |
fb3df220 |
548 | @param Value New value of the bit field.\r |
549 | \r |
d5979dc0 |
550 | @return The value written back to the PCI configuration register.\r |
fb3df220 |
551 | \r |
552 | **/\r |
553 | UINT16\r |
554 | EFIAPI\r |
555 | PciSegmentBitFieldWrite16 (\r |
556 | IN UINT64 Address,\r |
557 | IN UINTN StartBit,\r |
558 | IN UINTN EndBit,\r |
559 | IN UINT16 Value\r |
ed66e1bc |
560 | );\r |
fb3df220 |
561 | \r |
562 | /**\r |
563 | Reads the 16-bit PCI configuration register specified by Address,\r |
62991af2 |
564 | performs a bitwise OR between the read result and the value specified by OrData,\r |
fb3df220 |
565 | and writes the result to the 16-bit PCI configuration register specified by Address. \r |
566 | \r |
badcbfb2 |
567 | If any reserved bits in Address are set, then ASSERT().\r |
568 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
569 | If StartBit is greater than 15, then ASSERT().\r |
570 | If EndBit is greater than 15, then ASSERT().\r |
571 | If EndBit is less than StartBit, then ASSERT().\r |
572 | \r |
d5979dc0 |
573 | @param Address PCI configuration register to write.\r |
fb3df220 |
574 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 |
575 | Range 0..15.\r |
fb3df220 |
576 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 |
577 | Range 0..15.\r |
578 | @param OrData The value to OR with the PCI configuration register.\r |
fb3df220 |
579 | \r |
d5979dc0 |
580 | @return The value written back to the PCI configuration register.\r |
fb3df220 |
581 | \r |
582 | **/\r |
583 | UINT16\r |
584 | EFIAPI\r |
585 | PciSegmentBitFieldOr16 (\r |
586 | IN UINT64 Address,\r |
587 | IN UINTN StartBit,\r |
588 | IN UINTN EndBit,\r |
589 | IN UINT16 OrData\r |
ed66e1bc |
590 | );\r |
fb3df220 |
591 | \r |
592 | /**\r |
593 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r |
594 | and writes the result back to the bit field in the 16-bit port.\r |
595 | \r |
596 | Reads the 16-bit PCI configuration register specified by Address,\r |
62991af2 |
597 | performs a bitwise OR between the read result and the value specified by OrData,\r |
fb3df220 |
598 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
599 | The value written to the PCI configuration register is returned.\r |
600 | This function must guarantee that all PCI read and write operations are serialized.\r |
601 | Extra left bits in OrData are stripped.\r |
badcbfb2 |
602 | \r |
fb3df220 |
603 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 |
604 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
fb3df220 |
605 | If StartBit is greater than 7, then ASSERT().\r |
606 | If EndBit is greater than 7, then ASSERT().\r |
607 | If EndBit is less than StartBit, then ASSERT().\r |
608 | \r |
609 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
610 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
611 | The ordinal of the least significant bit in a byte is bit 0.\r |
612 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
613 | The ordinal of the most significant bit in a byte is bit 7.\r |
614 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
615 | \r |
616 | @return The value written to the PCI configuration register.\r |
617 | \r |
618 | **/\r |
619 | UINT16\r |
620 | EFIAPI\r |
621 | PciSegmentBitFieldAnd16 (\r |
622 | IN UINT64 Address,\r |
623 | IN UINTN StartBit,\r |
624 | IN UINTN EndBit,\r |
625 | IN UINT16 AndData\r |
ed66e1bc |
626 | );\r |
fb3df220 |
627 | \r |
628 | /**\r |
d5979dc0 |
629 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
62991af2 |
630 | bitwise OR, and writes the result back to the bit field in the\r |
d5979dc0 |
631 | 16-bit port.\r |
632 | \r |
633 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
62991af2 |
634 | bitwise AND followed by a bitwise OR between the read result and\r |
d5979dc0 |
635 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
636 | configuration register specified by Address. The value written to the PCI\r |
637 | configuration register is returned. This function must guarantee that all PCI\r |
638 | read and write operations are serialized. Extra left bits in both AndData and\r |
639 | OrData are stripped.\r |
640 | \r |
fb3df220 |
641 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 |
642 | If StartBit is greater than 15, then ASSERT().\r |
643 | If EndBit is greater than 15, then ASSERT().\r |
fb3df220 |
644 | If EndBit is less than StartBit, then ASSERT().\r |
645 | \r |
d5979dc0 |
646 | @param Address PCI configuration register to write.\r |
fb3df220 |
647 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 |
648 | Range 0..15.\r |
fb3df220 |
649 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 |
650 | Range 0..15.\r |
651 | @param AndData The value to AND with the PCI configuration register.\r |
652 | @param OrData The value to OR with the result of the AND operation.\r |
fb3df220 |
653 | \r |
d5979dc0 |
654 | @return The value written back to the PCI configuration register.\r |
fb3df220 |
655 | \r |
656 | **/\r |
657 | UINT16\r |
658 | EFIAPI\r |
659 | PciSegmentBitFieldAndThenOr16 (\r |
660 | IN UINT64 Address,\r |
661 | IN UINTN StartBit,\r |
662 | IN UINTN EndBit,\r |
663 | IN UINT16 AndData,\r |
664 | IN UINT16 OrData\r |
ed66e1bc |
665 | );\r |
fb3df220 |
666 | \r |
667 | /**\r |
668 | Reads a 32-bit PCI configuration register.\r |
669 | \r |
670 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
671 | This function must guarantee that all PCI read and write operations are serialized.\r |
fb3df220 |
672 | \r |
badcbfb2 |
673 | If any reserved bits in Address are set, then ASSERT().\r |
674 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
675 | \r |
fb3df220 |
676 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
677 | \r |
678 | @return The 32-bit PCI configuration register specified by Address.\r |
679 | \r |
680 | **/\r |
681 | UINT32\r |
682 | EFIAPI\r |
683 | PciSegmentRead32 (\r |
684 | IN UINT64 Address\r |
ed66e1bc |
685 | );\r |
fb3df220 |
686 | \r |
687 | /**\r |
688 | Writes a 32-bit PCI configuration register.\r |
689 | \r |
690 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r |
691 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
badcbfb2 |
692 | \r |
693 | If any reserved bits in Address are set, then ASSERT().\r |
694 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
fb3df220 |
695 | \r |
696 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
697 | @param Value The value to write.\r |
698 | \r |
699 | @return The parameter of Value.\r |
700 | \r |
701 | **/\r |
702 | UINT32\r |
703 | EFIAPI\r |
704 | PciSegmentWrite32 (\r |
705 | IN UINT64 Address,\r |
706 | IN UINT32 Value\r |
ed66e1bc |
707 | );\r |
fb3df220 |
708 | \r |
709 | /**\r |
62991af2 |
710 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r |
fb3df220 |
711 | \r |
712 | Reads the 32-bit PCI configuration register specified by Address,\r |
62991af2 |
713 | performs a bitwise OR between the read result and the value specified by OrData,\r |
fb3df220 |
714 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
715 | The value written to the PCI configuration register is returned.\r |
716 | This function must guarantee that all PCI read and write operations are serialized.\r |
badcbfb2 |
717 | \r |
fb3df220 |
718 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 |
719 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
fb3df220 |
720 | \r |
721 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
722 | @param OrData The value to OR with the PCI configuration register.\r |
723 | \r |
724 | @return The value written to the PCI configuration register.\r |
725 | \r |
726 | **/\r |
727 | UINT32\r |
728 | EFIAPI\r |
729 | PciSegmentOr32 (\r |
730 | IN UINT64 Address,\r |
731 | IN UINT32 OrData\r |
ed66e1bc |
732 | );\r |
fb3df220 |
733 | \r |
734 | /**\r |
735 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r |
736 | \r |
737 | Reads the 32-bit PCI configuration register specified by Address,\r |
738 | performs a bitwise AND between the read result and the value specified by AndData,\r |
739 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
740 | The value written to the PCI configuration register is returned.\r |
741 | This function must guarantee that all PCI read and write operations are serialized.\r |
badcbfb2 |
742 | \r |
fb3df220 |
743 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 |
744 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
fb3df220 |
745 | \r |
746 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
7d9333a9 |
747 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 |
748 | \r |
749 | @return The value written to the PCI configuration register.\r |
750 | \r |
751 | **/\r |
752 | UINT32\r |
753 | EFIAPI\r |
754 | PciSegmentAnd32 (\r |
755 | IN UINT64 Address,\r |
756 | IN UINT32 AndData\r |
ed66e1bc |
757 | );\r |
fb3df220 |
758 | \r |
759 | /**\r |
760 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r |
62991af2 |
761 | followed a bitwise OR with another 32-bit value.\r |
fb3df220 |
762 | \r |
763 | Reads the 32-bit PCI configuration register specified by Address,\r |
764 | performs a bitwise AND between the read result and the value specified by AndData,\r |
62991af2 |
765 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
fb3df220 |
766 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
767 | The value written to the PCI configuration register is returned.\r |
768 | This function must guarantee that all PCI read and write operations are serialized.\r |
badcbfb2 |
769 | \r |
fb3df220 |
770 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 |
771 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
fb3df220 |
772 | \r |
773 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
7d9333a9 |
774 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 |
775 | @param OrData The value to OR with the PCI configuration register.\r |
776 | \r |
777 | @return The value written to the PCI configuration register.\r |
778 | \r |
779 | **/\r |
780 | UINT32\r |
781 | EFIAPI\r |
782 | PciSegmentAndThenOr32 (\r |
783 | IN UINT64 Address,\r |
784 | IN UINT32 AndData,\r |
785 | IN UINT32 OrData\r |
ed66e1bc |
786 | );\r |
fb3df220 |
787 | \r |
788 | /**\r |
789 | Reads a bit field of a PCI configuration register.\r |
790 | \r |
d5979dc0 |
791 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
792 | specified by the StartBit and the EndBit. The value of the bit field is\r |
793 | returned.\r |
794 | \r |
fb3df220 |
795 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 |
796 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
d5979dc0 |
797 | If StartBit is greater than 31, then ASSERT().\r |
798 | If EndBit is greater than 31, then ASSERT().\r |
fb3df220 |
799 | If EndBit is less than StartBit, then ASSERT().\r |
800 | \r |
d5979dc0 |
801 | @param Address PCI configuration register to read.\r |
fb3df220 |
802 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 |
803 | Range 0..31.\r |
fb3df220 |
804 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 |
805 | Range 0..31.\r |
fb3df220 |
806 | \r |
d5979dc0 |
807 | @return The value of the bit field read from the PCI configuration register.\r |
fb3df220 |
808 | \r |
809 | **/\r |
810 | UINT32\r |
811 | EFIAPI\r |
812 | PciSegmentBitFieldRead32 (\r |
813 | IN UINT64 Address,\r |
814 | IN UINTN StartBit,\r |
815 | IN UINTN EndBit\r |
ed66e1bc |
816 | );\r |
fb3df220 |
817 | \r |
818 | /**\r |
819 | Writes a bit field to a PCI configuration register.\r |
820 | \r |
d5979dc0 |
821 | Writes Value to the bit field of the PCI configuration register. The bit\r |
822 | field is specified by the StartBit and the EndBit. All other bits in the\r |
823 | destination PCI configuration register are preserved. The new value of the\r |
824 | 32-bit register is returned.\r |
825 | \r |
fb3df220 |
826 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 |
827 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
d5979dc0 |
828 | If StartBit is greater than 31, then ASSERT().\r |
829 | If EndBit is greater than 31, then ASSERT().\r |
fb3df220 |
830 | If EndBit is less than StartBit, then ASSERT().\r |
831 | \r |
d5979dc0 |
832 | @param Address PCI configuration register to write.\r |
fb3df220 |
833 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 |
834 | Range 0..31.\r |
fb3df220 |
835 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 |
836 | Range 0..31.\r |
fb3df220 |
837 | @param Value New value of the bit field.\r |
838 | \r |
d5979dc0 |
839 | @return The value written back to the PCI configuration register.\r |
fb3df220 |
840 | \r |
841 | **/\r |
842 | UINT32\r |
843 | EFIAPI\r |
844 | PciSegmentBitFieldWrite32 (\r |
845 | IN UINT64 Address,\r |
846 | IN UINTN StartBit,\r |
847 | IN UINTN EndBit,\r |
848 | IN UINT32 Value\r |
ed66e1bc |
849 | );\r |
fb3df220 |
850 | \r |
851 | /**\r |
d5979dc0 |
852 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
853 | writes the result back to the bit field in the 32-bit port.\r |
854 | \r |
855 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
62991af2 |
856 | bitwise OR between the read result and the value specified by\r |
d5979dc0 |
857 | OrData, and writes the result to the 32-bit PCI configuration register\r |
858 | specified by Address. The value written to the PCI configuration register is\r |
859 | returned. This function must guarantee that all PCI read and write operations\r |
860 | are serialized. Extra left bits in OrData are stripped.\r |
861 | \r |
badcbfb2 |
862 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 |
863 | If StartBit is greater than 31, then ASSERT().\r |
864 | If EndBit is greater than 31, then ASSERT().\r |
badcbfb2 |
865 | If EndBit is less than StartBit, then ASSERT().\r |
d5979dc0 |
866 | \r |
867 | @param Address PCI configuration register to write.\r |
fb3df220 |
868 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 |
869 | Range 0..31.\r |
fb3df220 |
870 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 |
871 | Range 0..31.\r |
872 | @param OrData The value to OR with the PCI configuration register.\r |
fb3df220 |
873 | \r |
d5979dc0 |
874 | @return The value written back to the PCI configuration register.\r |
fb3df220 |
875 | \r |
876 | **/\r |
877 | UINT32\r |
878 | EFIAPI\r |
879 | PciSegmentBitFieldOr32 (\r |
880 | IN UINT64 Address,\r |
881 | IN UINTN StartBit,\r |
882 | IN UINTN EndBit,\r |
883 | IN UINT32 OrData\r |
ed66e1bc |
884 | );\r |
fb3df220 |
885 | \r |
886 | /**\r |
d5979dc0 |
887 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
888 | AND, and writes the result back to the bit field in the 32-bit register.\r |
fb3df220 |
889 | \r |
badcbfb2 |
890 | \r |
d5979dc0 |
891 | Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r |
892 | AND between the read result and the value specified by AndData, and writes the result\r |
893 | to the 32-bit PCI configuration register specified by Address. The value written to\r |
894 | the PCI configuration register is returned. This function must guarantee that all PCI\r |
895 | read and write operations are serialized. Extra left bits in AndData are stripped.\r |
fb3df220 |
896 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 |
897 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
d5979dc0 |
898 | If StartBit is greater than 31, then ASSERT().\r |
899 | If EndBit is greater than 31, then ASSERT().\r |
fb3df220 |
900 | If EndBit is less than StartBit, then ASSERT().\r |
d5979dc0 |
901 | \r |
fb3df220 |
902 | \r |
d5979dc0 |
903 | @param Address PCI configuration register to write.\r |
fb3df220 |
904 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 |
905 | Range 0..31.\r |
fb3df220 |
906 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 |
907 | Range 0..31.\r |
908 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 |
909 | \r |
d5979dc0 |
910 | @return The value written back to the PCI configuration register.\r |
fb3df220 |
911 | \r |
912 | **/\r |
913 | UINT32\r |
914 | EFIAPI\r |
915 | PciSegmentBitFieldAnd32 (\r |
916 | IN UINT64 Address,\r |
917 | IN UINTN StartBit,\r |
918 | IN UINTN EndBit,\r |
919 | IN UINT32 AndData\r |
ed66e1bc |
920 | );\r |
fb3df220 |
921 | \r |
922 | /**\r |
d5979dc0 |
923 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
62991af2 |
924 | bitwise OR, and writes the result back to the bit field in the\r |
d5979dc0 |
925 | 32-bit port.\r |
926 | \r |
927 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
62991af2 |
928 | bitwise AND followed by a bitwise OR between the read result and\r |
d5979dc0 |
929 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
930 | configuration register specified by Address. The value written to the PCI\r |
931 | configuration register is returned. This function must guarantee that all PCI\r |
932 | read and write operations are serialized. Extra left bits in both AndData and\r |
933 | OrData are stripped.\r |
934 | \r |
fb3df220 |
935 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 |
936 | If StartBit is greater than 31, then ASSERT().\r |
937 | If EndBit is greater than 31, then ASSERT().\r |
fb3df220 |
938 | If EndBit is less than StartBit, then ASSERT().\r |
939 | \r |
d5979dc0 |
940 | @param Address PCI configuration register to write.\r |
fb3df220 |
941 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 |
942 | Range 0..31.\r |
fb3df220 |
943 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 |
944 | Range 0..31.\r |
945 | @param AndData The value to AND with the PCI configuration register.\r |
946 | @param OrData The value to OR with the result of the AND operation.\r |
fb3df220 |
947 | \r |
d5979dc0 |
948 | @return The value written back to the PCI configuration register.\r |
fb3df220 |
949 | \r |
950 | **/\r |
951 | UINT32\r |
952 | EFIAPI\r |
953 | PciSegmentBitFieldAndThenOr32 (\r |
954 | IN UINT64 Address,\r |
955 | IN UINTN StartBit,\r |
956 | IN UINTN EndBit,\r |
957 | IN UINT32 AndData,\r |
958 | IN UINT32 OrData\r |
ed66e1bc |
959 | );\r |
fb3df220 |
960 | \r |
961 | /**\r |
962 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
963 | \r |
d5979dc0 |
964 | Reads the range of PCI configuration registers specified by StartAddress and\r |
965 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
966 | configuration registers from a single PCI function to be read. Size is\r |
967 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
968 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
969 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
970 | end of the range.\r |
971 | \r |
972 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
fb3df220 |
973 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
badcbfb2 |
974 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
fb3df220 |
975 | \r |
d5979dc0 |
976 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r |
977 | Function and Register.\r |
fb3df220 |
978 | @param Size Size in bytes of the transfer.\r |
979 | @param Buffer Pointer to a buffer receiving the data read.\r |
980 | \r |
d5979dc0 |
981 | @return Size\r |
fb3df220 |
982 | \r |
983 | **/\r |
984 | UINTN\r |
985 | EFIAPI\r |
986 | PciSegmentReadBuffer (\r |
987 | IN UINT64 StartAddress,\r |
988 | IN UINTN Size,\r |
989 | OUT VOID *Buffer\r |
ed66e1bc |
990 | );\r |
fb3df220 |
991 | \r |
992 | /**\r |
d5979dc0 |
993 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
994 | configuration space.\r |
995 | \r |
996 | Writes the range of PCI configuration registers specified by StartAddress and\r |
997 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
998 | configuration registers from a single PCI function to be written. Size is\r |
999 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
1000 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
1001 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
1002 | and the end of the range.\r |
1003 | \r |
1004 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
fb3df220 |
1005 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
d5979dc0 |
1006 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
fb3df220 |
1007 | \r |
d5979dc0 |
1008 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r |
1009 | Function and Register.\r |
fb3df220 |
1010 | @param Size Size in bytes of the transfer.\r |
1011 | @param Buffer Pointer to a buffer containing the data to write.\r |
1012 | \r |
badcbfb2 |
1013 | @return The parameter of Size.\r |
fb3df220 |
1014 | \r |
1015 | **/\r |
1016 | UINTN\r |
1017 | EFIAPI\r |
1018 | PciSegmentWriteBuffer (\r |
1019 | IN UINT64 StartAddress,\r |
1020 | IN UINTN Size,\r |
1021 | IN VOID *Buffer\r |
ed66e1bc |
1022 | );\r |
fb3df220 |
1023 | \r |
1024 | #endif\r |