| fb3df220 |
1 | /** @file\r |
| 50a64e5b |
2 | Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r |
| badcbfb2 |
3 | \r |
| 4 | The PCI Segment Library function provide services to read, write, and modify the PCI configuration\r |
| 5 | registers on PCI root bridges on any supported PCI segment. These library services take a single \r |
| 6 | address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register. \r |
| 7 | The layout of this address parameter is as follows:\r |
| 8 | \r |
| 9 | PCI Register: Bits 0..11\r |
| 10 | PCI Function Bits 12..14\r |
| 11 | PCI Device Bits 15..19\r |
| 12 | PCI Bus Bits 20..27\r |
| 13 | Reserved Bits 28..31. Must be 0.\r |
| 14 | PCI Segment Bits 32..47\r |
| 15 | Reserved Bits 48..63. Must be 0.\r |
| 16 | \r |
| 17 | | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r |
| 18 | 63 48 47 32 31 28 27 20 19 15 14 12 11 0\r |
| 19 | \r |
| 20 | These functions perform PCI configuration cycles using the default PCI configuration access \r |
| 21 | method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it \r |
| 22 | may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate \r |
| 23 | access method. Modules will typically use the PCI Segment Library for its PCI configuration \r |
| 24 | accesses when PCI Segments other than Segment #0 must be accessed. \r |
| fb3df220 |
25 | \r |
| 50a64e5b |
26 | Copyright (c) 2006 - 2008, Intel Corporation\r |
| 27 | All rights reserved. This program and the accompanying materials\r |
| 28 | are licensed and made available under the terms and conditions of the BSD License\r |
| 29 | which accompanies this distribution. The full text of the license may be found at\r |
| 30 | http://opensource.org/licenses/bsd-license.php\r |
| fb3df220 |
31 | \r |
| 50a64e5b |
32 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 33 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| fb3df220 |
34 | \r |
| fb3df220 |
35 | **/\r |
| 36 | \r |
| 37 | #ifndef __PCI_SEGMENT_LIB__\r |
| 38 | #define __PCI_SEGMENT_LIB__\r |
| 39 | \r |
| 40 | \r |
| 41 | /**\r |
| 42 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r |
| 43 | and PCI Register to an address that can be passed to the PCI Segment Library functions.\r |
| 44 | \r |
| 45 | Computes an address that is compatible with the PCI Segment Library functions.\r |
| 46 | The unused upper bits of Segment, Bus, Device, Function,\r |
| 47 | and Register are stripped prior to the generation of the address.\r |
| 48 | \r |
| 49 | @param Segment PCI Segment number. Range 0..65535.\r |
| 50 | @param Bus PCI Bus number. Range 0..255.\r |
| 51 | @param Device PCI Device number. Range 0..31.\r |
| 52 | @param Function PCI Function number. Range 0..7.\r |
| 53 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r |
| 54 | \r |
| 55 | @return The address that is compatible with the PCI Segment Library functions.\r |
| 56 | \r |
| 57 | **/\r |
| 58 | #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r |
| 59 | ( ((Register) & 0xfff) | \\r |
| 60 | (((Function) & 0x07) << 12) | \\r |
| 61 | (((Device) & 0x1f) << 15) | \\r |
| 62 | (((Bus) & 0xff) << 20) | \\r |
| 63 | (LShiftU64((Segment) & 0xffff, 32)) \\r |
| 64 | )\r |
| 65 | \r |
| 66 | /**\r |
| 67 | Reads an 8-bit PCI configuration register.\r |
| 68 | \r |
| 69 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 70 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
71 | \r |
| fb3df220 |
72 | If any reserved bits in Address are set, then ASSERT().\r |
| 73 | \r |
| 74 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 75 | \r |
| 76 | @return The 8-bit PCI configuration register specified by Address.\r |
| 77 | \r |
| 78 | **/\r |
| 79 | UINT8\r |
| 80 | EFIAPI\r |
| 81 | PciSegmentRead8 (\r |
| 82 | IN UINT64 Address\r |
| ed66e1bc |
83 | );\r |
| fb3df220 |
84 | \r |
| 85 | /**\r |
| 86 | Writes an 8-bit PCI configuration register.\r |
| 87 | \r |
| 88 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r |
| 89 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
90 | \r |
| fb3df220 |
91 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 92 | \r |
| 93 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 94 | @param Value The value to write.\r |
| 95 | \r |
| 96 | @return The parameter of Value.\r |
| 97 | \r |
| 98 | **/\r |
| 99 | UINT8\r |
| 100 | EFIAPI\r |
| 101 | PciSegmentWrite8 (\r |
| 102 | IN UINT64 Address,\r |
| 103 | IN UINT8 Value\r |
| ed66e1bc |
104 | );\r |
| fb3df220 |
105 | \r |
| 106 | /**\r |
| 107 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.\r |
| 108 | \r |
| 109 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 110 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 111 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 112 | The value written to the PCI configuration register is returned.\r |
| 113 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
114 | \r |
| fb3df220 |
115 | If any reserved bits in Address are set, then ASSERT().\r |
| 116 | \r |
| 117 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 118 | @param OrData The value to OR with the PCI configuration register.\r |
| 119 | \r |
| 120 | @return The value written to the PCI configuration register.\r |
| 121 | \r |
| 122 | **/\r |
| 123 | UINT8\r |
| 124 | EFIAPI\r |
| 125 | PciSegmentOr8 (\r |
| 126 | IN UINT64 Address,\r |
| 127 | IN UINT8 OrData\r |
| ed66e1bc |
128 | );\r |
| fb3df220 |
129 | \r |
| 130 | /**\r |
| 131 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r |
| 132 | \r |
| 133 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 134 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 135 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 136 | The value written to the PCI configuration register is returned.\r |
| 137 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 138 | If any reserved bits in Address are set, then ASSERT().\r |
| 139 | \r |
| 140 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 7d9333a9 |
141 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
142 | \r |
| 143 | @return The value written to the PCI configuration register.\r |
| 144 | \r |
| 145 | **/\r |
| 146 | UINT8\r |
| 147 | EFIAPI\r |
| 148 | PciSegmentAnd8 (\r |
| 149 | IN UINT64 Address,\r |
| 150 | IN UINT8 AndData\r |
| ed66e1bc |
151 | );\r |
| fb3df220 |
152 | \r |
| 153 | /**\r |
| 154 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r |
| 155 | followed a bitwise inclusive OR with another 8-bit value.\r |
| 156 | \r |
| 157 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 158 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 159 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r |
| 160 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 161 | The value written to the PCI configuration register is returned.\r |
| 162 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
163 | \r |
| fb3df220 |
164 | If any reserved bits in Address are set, then ASSERT().\r |
| 165 | \r |
| 166 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 42eedea9 |
167 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
168 | @param OrData The value to OR with the PCI configuration register.\r |
| 169 | \r |
| 170 | @return The value written to the PCI configuration register.\r |
| 171 | \r |
| 172 | **/\r |
| 173 | UINT8\r |
| 174 | EFIAPI\r |
| 175 | PciSegmentAndThenOr8 (\r |
| 176 | IN UINT64 Address,\r |
| 177 | IN UINT8 AndData,\r |
| 178 | IN UINT8 OrData\r |
| ed66e1bc |
179 | );\r |
| fb3df220 |
180 | \r |
| 181 | /**\r |
| 182 | Reads a bit field of a PCI configuration register.\r |
| 183 | \r |
| 184 | Reads the bit field in an 8-bit PCI configuration register.\r |
| 185 | The bit field is specified by the StartBit and the EndBit.\r |
| 186 | The value of the bit field is returned.\r |
| badcbfb2 |
187 | \r |
| fb3df220 |
188 | If any reserved bits in Address are set, then ASSERT().\r |
| 189 | If StartBit is greater than 7, then ASSERT().\r |
| 190 | If EndBit is greater than 7, then ASSERT().\r |
| 191 | If EndBit is less than StartBit, then ASSERT().\r |
| 192 | \r |
| 193 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 194 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 195 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 196 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 197 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 198 | \r |
| 199 | @return The value of the bit field.\r |
| 200 | \r |
| 201 | **/\r |
| 202 | UINT8\r |
| 203 | EFIAPI\r |
| 204 | PciSegmentBitFieldRead8 (\r |
| 205 | IN UINT64 Address,\r |
| 206 | IN UINTN StartBit,\r |
| 207 | IN UINTN EndBit\r |
| ed66e1bc |
208 | );\r |
| fb3df220 |
209 | \r |
| 210 | /**\r |
| 211 | Writes a bit field to a PCI configuration register.\r |
| 212 | \r |
| 213 | Writes Value to the bit field of the PCI configuration register.\r |
| 214 | The bit field is specified by the StartBit and the EndBit.\r |
| 215 | All other bits in the destination PCI configuration register are preserved.\r |
| 216 | The new value of the 8-bit register is returned.\r |
| 217 | If any reserved bits in Address are set, then ASSERT().\r |
| 218 | If StartBit is greater than 7, then ASSERT().\r |
| 219 | If EndBit is greater than 7, then ASSERT().\r |
| 220 | If EndBit is less than StartBit, then ASSERT().\r |
| 221 | \r |
| 222 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 223 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 224 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 225 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 226 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 227 | @param Value New value of the bit field.\r |
| 228 | \r |
| 229 | @return The new value of the 8-bit register.\r |
| 230 | \r |
| 231 | **/\r |
| 232 | UINT8\r |
| 233 | EFIAPI\r |
| 234 | PciSegmentBitFieldWrite8 (\r |
| 235 | IN UINT64 Address,\r |
| 236 | IN UINTN StartBit,\r |
| 237 | IN UINTN EndBit,\r |
| 238 | IN UINT8 Value\r |
| ed66e1bc |
239 | );\r |
| fb3df220 |
240 | \r |
| 241 | /**\r |
| 242 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 243 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 244 | and writes the result to the 8-bit PCI configuration register specified by Address. \r |
| badcbfb2 |
245 | \r |
| 246 | If any reserved bits in Address are set, then ASSERT().\r |
| 247 | If StartBit is greater than 7, then ASSERT().\r |
| 248 | If EndBit is greater than 7, then ASSERT().\r |
| 249 | If EndBit is less than StartBit, then ASSERT().\r |
| fb3df220 |
250 | \r |
| 251 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 252 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 253 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 254 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 255 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 256 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 257 | \r |
| 258 | @return The value written to the PCI configuration register.\r |
| 259 | \r |
| 260 | **/\r |
| 261 | UINT8\r |
| 262 | EFIAPI\r |
| 263 | PciSegmentBitFieldOr8 (\r |
| 264 | IN UINT64 Address,\r |
| 265 | IN UINTN StartBit,\r |
| 266 | IN UINTN EndBit,\r |
| 267 | IN UINT8 OrData\r |
| ed66e1bc |
268 | );\r |
| fb3df220 |
269 | \r |
| 270 | /**\r |
| 271 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,\r |
| 272 | and writes the result back to the bit field in the 8-bit port.\r |
| 273 | \r |
| 274 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 275 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 276 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 277 | The value written to the PCI configuration register is returned.\r |
| 278 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 279 | Extra left bits in OrData are stripped.\r |
| badcbfb2 |
280 | \r |
| fb3df220 |
281 | If any reserved bits in Address are set, then ASSERT().\r |
| 282 | If StartBit is greater than 7, then ASSERT().\r |
| 283 | If EndBit is greater than 7, then ASSERT().\r |
| 284 | If EndBit is less than StartBit, then ASSERT().\r |
| 285 | \r |
| 286 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 287 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 288 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 289 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 290 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 291 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 292 | \r |
| 293 | @return The value written to the PCI configuration register.\r |
| 294 | \r |
| 295 | **/\r |
| 296 | UINT8\r |
| 297 | EFIAPI\r |
| 298 | PciSegmentBitFieldAnd8 (\r |
| 299 | IN UINT64 Address,\r |
| 300 | IN UINTN StartBit,\r |
| 301 | IN UINTN EndBit,\r |
| 302 | IN UINT8 AndData\r |
| ed66e1bc |
303 | );\r |
| fb3df220 |
304 | \r |
| 305 | /**\r |
| 306 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,\r |
| 307 | and writes the result back to the bit field in the 8-bit register.\r |
| 308 | \r |
| 309 | Reads the 8-bit PCI configuration register specified by Address,\r |
| 310 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 311 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
| 312 | The value written to the PCI configuration register is returned.\r |
| 313 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 314 | Extra left bits in AndData are stripped.\r |
| badcbfb2 |
315 | \r |
| fb3df220 |
316 | If any reserved bits in Address are set, then ASSERT().\r |
| 317 | If StartBit is greater than 7, then ASSERT().\r |
| 318 | If EndBit is greater than 7, then ASSERT().\r |
| 319 | If EndBit is less than StartBit, then ASSERT().\r |
| 320 | \r |
| 321 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 322 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 323 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 324 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 325 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 326 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 327 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 328 | \r |
| 329 | @return The value written to the PCI configuration register.\r |
| 330 | \r |
| 331 | **/\r |
| 332 | UINT8\r |
| 333 | EFIAPI\r |
| 334 | PciSegmentBitFieldAndThenOr8 (\r |
| 335 | IN UINT64 Address,\r |
| 336 | IN UINTN StartBit,\r |
| 337 | IN UINTN EndBit,\r |
| 338 | IN UINT8 AndData,\r |
| 339 | IN UINT8 OrData\r |
| ed66e1bc |
340 | );\r |
| fb3df220 |
341 | \r |
| 342 | /**\r |
| 343 | Reads a 16-bit PCI configuration register.\r |
| 344 | \r |
| 345 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 346 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
347 | \r |
| fb3df220 |
348 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
349 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
350 | \r |
| 351 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 352 | \r |
| 353 | @return The 16-bit PCI configuration register specified by Address.\r |
| 354 | \r |
| 355 | **/\r |
| 356 | UINT16\r |
| 357 | EFIAPI\r |
| 358 | PciSegmentRead16 (\r |
| 359 | IN UINT64 Address\r |
| ed66e1bc |
360 | );\r |
| fb3df220 |
361 | \r |
| 362 | /**\r |
| 363 | Writes a 16-bit PCI configuration register.\r |
| 364 | \r |
| 365 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r |
| 366 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
367 | \r |
| 368 | If any reserved bits in Address are set, then ASSERT().\r |
| 369 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
370 | \r |
| 371 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 372 | @param Value The value to write.\r |
| 373 | \r |
| 374 | @return The parameter of Value.\r |
| 375 | \r |
| 376 | **/\r |
| 377 | UINT16\r |
| 378 | EFIAPI\r |
| 379 | PciSegmentWrite16 (\r |
| 380 | IN UINT64 Address,\r |
| 381 | IN UINT16 Value\r |
| ed66e1bc |
382 | );\r |
| fb3df220 |
383 | \r |
| 384 | /**\r |
| 385 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.\r |
| 386 | \r |
| 387 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 388 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 389 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 390 | The value written to the PCI configuration register is returned.\r |
| 391 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
392 | \r |
| fb3df220 |
393 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
394 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
395 | \r |
| 396 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 397 | @param OrData The value to OR with the PCI configuration register.\r |
| 398 | \r |
| 399 | @return The value written to the PCI configuration register.\r |
| 400 | \r |
| 401 | **/\r |
| 402 | UINT16\r |
| 403 | EFIAPI\r |
| 404 | PciSegmentOr16 (\r |
| 405 | IN UINT64 Address,\r |
| 406 | IN UINT16 OrData\r |
| ed66e1bc |
407 | );\r |
| fb3df220 |
408 | \r |
| 409 | /**\r |
| 410 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r |
| 411 | \r |
| 412 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 413 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 414 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 415 | The value written to the PCI configuration register is returned.\r |
| 416 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
417 | \r |
| fb3df220 |
418 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
419 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 420 | \r |
| fb3df220 |
421 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 7d9333a9 |
422 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
423 | \r |
| 424 | @return The value written to the PCI configuration register.\r |
| 425 | \r |
| 426 | **/\r |
| 427 | UINT16\r |
| 428 | EFIAPI\r |
| 429 | PciSegmentAnd16 (\r |
| 430 | IN UINT64 Address,\r |
| 431 | IN UINT16 AndData\r |
| ed66e1bc |
432 | );\r |
| fb3df220 |
433 | \r |
| 434 | /**\r |
| 435 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r |
| 436 | followed a bitwise inclusive OR with another 16-bit value.\r |
| 437 | \r |
| 438 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 439 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 440 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r |
| 441 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 442 | The value written to the PCI configuration register is returned.\r |
| 443 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
444 | \r |
| fb3df220 |
445 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
446 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
447 | \r |
| 448 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 42eedea9 |
449 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
450 | @param OrData The value to OR with the PCI configuration register.\r |
| 451 | \r |
| 452 | @return The value written to the PCI configuration register.\r |
| 453 | \r |
| 454 | **/\r |
| 455 | UINT16\r |
| 456 | EFIAPI\r |
| 457 | PciSegmentAndThenOr16 (\r |
| 458 | IN UINT64 Address,\r |
| 459 | IN UINT16 AndData,\r |
| 460 | IN UINT16 OrData\r |
| ed66e1bc |
461 | );\r |
| fb3df220 |
462 | \r |
| 463 | /**\r |
| 464 | Reads a bit field of a PCI configuration register.\r |
| 465 | \r |
| 466 | Reads the bit field in a 16-bit PCI configuration register.\r |
| 467 | The bit field is specified by the StartBit and the EndBit.\r |
| 468 | The value of the bit field is returned.\r |
| badcbfb2 |
469 | \r |
| fb3df220 |
470 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
471 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
472 | If StartBit is greater than 7, then ASSERT().\r |
| 473 | If EndBit is greater than 7, then ASSERT().\r |
| 474 | If EndBit is less than StartBit, then ASSERT().\r |
| 475 | \r |
| 476 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 477 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 478 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 479 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 480 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 481 | \r |
| 482 | @return The value of the bit field.\r |
| 483 | \r |
| 484 | **/\r |
| 485 | UINT16\r |
| 486 | EFIAPI\r |
| 487 | PciSegmentBitFieldRead16 (\r |
| 488 | IN UINT64 Address,\r |
| 489 | IN UINTN StartBit,\r |
| 490 | IN UINTN EndBit\r |
| ed66e1bc |
491 | );\r |
| fb3df220 |
492 | \r |
| 493 | /**\r |
| 494 | Writes a bit field to a PCI configuration register.\r |
| 495 | \r |
| 496 | Writes Value to the bit field of the PCI configuration register.\r |
| 497 | The bit field is specified by the StartBit and the EndBit.\r |
| 498 | All other bits in the destination PCI configuration register are preserved.\r |
| 499 | The new value of the 16-bit register is returned.\r |
| badcbfb2 |
500 | \r |
| fb3df220 |
501 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
502 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
503 | If StartBit is greater than 7, then ASSERT().\r |
| 504 | If EndBit is greater than 7, then ASSERT().\r |
| 505 | If EndBit is less than StartBit, then ASSERT().\r |
| 506 | \r |
| 507 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 508 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 509 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 510 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 511 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 512 | @param Value New value of the bit field.\r |
| 513 | \r |
| 514 | @return The new value of the 16-bit register.\r |
| 515 | \r |
| 516 | **/\r |
| 517 | UINT16\r |
| 518 | EFIAPI\r |
| 519 | PciSegmentBitFieldWrite16 (\r |
| 520 | IN UINT64 Address,\r |
| 521 | IN UINTN StartBit,\r |
| 522 | IN UINTN EndBit,\r |
| 523 | IN UINT16 Value\r |
| ed66e1bc |
524 | );\r |
| fb3df220 |
525 | \r |
| 526 | /**\r |
| 527 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 528 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 529 | and writes the result to the 16-bit PCI configuration register specified by Address. \r |
| 530 | \r |
| badcbfb2 |
531 | If any reserved bits in Address are set, then ASSERT().\r |
| 532 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 533 | If StartBit is greater than 15, then ASSERT().\r |
| 534 | If EndBit is greater than 15, then ASSERT().\r |
| 535 | If EndBit is less than StartBit, then ASSERT().\r |
| 536 | \r |
| fb3df220 |
537 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 538 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 539 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 540 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 541 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 542 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 543 | \r |
| 544 | @return The value written to the PCI configuration register.\r |
| 545 | \r |
| 546 | **/\r |
| 547 | UINT16\r |
| 548 | EFIAPI\r |
| 549 | PciSegmentBitFieldOr16 (\r |
| 550 | IN UINT64 Address,\r |
| 551 | IN UINTN StartBit,\r |
| 552 | IN UINTN EndBit,\r |
| 553 | IN UINT16 OrData\r |
| ed66e1bc |
554 | );\r |
| fb3df220 |
555 | \r |
| 556 | /**\r |
| 557 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r |
| 558 | and writes the result back to the bit field in the 16-bit port.\r |
| 559 | \r |
| 560 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 561 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 562 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 563 | The value written to the PCI configuration register is returned.\r |
| 564 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 565 | Extra left bits in OrData are stripped.\r |
| badcbfb2 |
566 | \r |
| fb3df220 |
567 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
568 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| fb3df220 |
569 | If StartBit is greater than 7, then ASSERT().\r |
| 570 | If EndBit is greater than 7, then ASSERT().\r |
| 571 | If EndBit is less than StartBit, then ASSERT().\r |
| 572 | \r |
| 573 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 574 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 575 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 576 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 577 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 578 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 579 | \r |
| 580 | @return The value written to the PCI configuration register.\r |
| 581 | \r |
| 582 | **/\r |
| 583 | UINT16\r |
| 584 | EFIAPI\r |
| 585 | PciSegmentBitFieldAnd16 (\r |
| 586 | IN UINT64 Address,\r |
| 587 | IN UINTN StartBit,\r |
| 588 | IN UINTN EndBit,\r |
| 589 | IN UINT16 AndData\r |
| ed66e1bc |
590 | );\r |
| fb3df220 |
591 | \r |
| 592 | /**\r |
| 593 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,\r |
| 594 | and writes the result back to the bit field in the 16-bit register.\r |
| 595 | \r |
| 596 | Reads the 16-bit PCI configuration register specified by Address,\r |
| 597 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 598 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
| 599 | The value written to the PCI configuration register is returned.\r |
| 600 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 601 | Extra left bits in AndData are stripped.\r |
| badcbfb2 |
602 | \r |
| fb3df220 |
603 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
604 | If Address is not aligned on a 16-bit boundary, then ASSERT()..\r |
| fb3df220 |
605 | If StartBit is greater than 7, then ASSERT().\r |
| 606 | If EndBit is greater than 7, then ASSERT().\r |
| 607 | If EndBit is less than StartBit, then ASSERT().\r |
| 608 | \r |
| 609 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 610 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 611 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 612 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 613 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 614 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 615 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 616 | \r |
| 617 | @return The value written to the PCI configuration register.\r |
| 618 | \r |
| 619 | **/\r |
| 620 | UINT16\r |
| 621 | EFIAPI\r |
| 622 | PciSegmentBitFieldAndThenOr16 (\r |
| 623 | IN UINT64 Address,\r |
| 624 | IN UINTN StartBit,\r |
| 625 | IN UINTN EndBit,\r |
| 626 | IN UINT16 AndData,\r |
| 627 | IN UINT16 OrData\r |
| ed66e1bc |
628 | );\r |
| fb3df220 |
629 | \r |
| 630 | /**\r |
| 631 | Reads a 32-bit PCI configuration register.\r |
| 632 | \r |
| 633 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 634 | This function must guarantee that all PCI read and write operations are serialized.\r |
| fb3df220 |
635 | \r |
| badcbfb2 |
636 | If any reserved bits in Address are set, then ASSERT().\r |
| 637 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 638 | \r |
| fb3df220 |
639 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 640 | \r |
| 641 | @return The 32-bit PCI configuration register specified by Address.\r |
| 642 | \r |
| 643 | **/\r |
| 644 | UINT32\r |
| 645 | EFIAPI\r |
| 646 | PciSegmentRead32 (\r |
| 647 | IN UINT64 Address\r |
| ed66e1bc |
648 | );\r |
| fb3df220 |
649 | \r |
| 650 | /**\r |
| 651 | Writes a 32-bit PCI configuration register.\r |
| 652 | \r |
| 653 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r |
| 654 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
655 | \r |
| 656 | If any reserved bits in Address are set, then ASSERT().\r |
| 657 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
658 | \r |
| 659 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 660 | @param Value The value to write.\r |
| 661 | \r |
| 662 | @return The parameter of Value.\r |
| 663 | \r |
| 664 | **/\r |
| 665 | UINT32\r |
| 666 | EFIAPI\r |
| 667 | PciSegmentWrite32 (\r |
| 668 | IN UINT64 Address,\r |
| 669 | IN UINT32 Value\r |
| ed66e1bc |
670 | );\r |
| fb3df220 |
671 | \r |
| 672 | /**\r |
| 673 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.\r |
| 674 | \r |
| 675 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 676 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 677 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 678 | The value written to the PCI configuration register is returned.\r |
| 679 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
680 | \r |
| fb3df220 |
681 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
682 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
683 | \r |
| 684 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 685 | @param OrData The value to OR with the PCI configuration register.\r |
| 686 | \r |
| 687 | @return The value written to the PCI configuration register.\r |
| 688 | \r |
| 689 | **/\r |
| 690 | UINT32\r |
| 691 | EFIAPI\r |
| 692 | PciSegmentOr32 (\r |
| 693 | IN UINT64 Address,\r |
| 694 | IN UINT32 OrData\r |
| ed66e1bc |
695 | );\r |
| fb3df220 |
696 | \r |
| 697 | /**\r |
| 698 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r |
| 699 | \r |
| 700 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 701 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 702 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 703 | The value written to the PCI configuration register is returned.\r |
| 704 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
705 | \r |
| fb3df220 |
706 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
707 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
708 | \r |
| 709 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 7d9333a9 |
710 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
711 | \r |
| 712 | @return The value written to the PCI configuration register.\r |
| 713 | \r |
| 714 | **/\r |
| 715 | UINT32\r |
| 716 | EFIAPI\r |
| 717 | PciSegmentAnd32 (\r |
| 718 | IN UINT64 Address,\r |
| 719 | IN UINT32 AndData\r |
| ed66e1bc |
720 | );\r |
| fb3df220 |
721 | \r |
| 722 | /**\r |
| 723 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r |
| 724 | followed a bitwise inclusive OR with another 32-bit value.\r |
| 725 | \r |
| 726 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 727 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 728 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r |
| 729 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 730 | The value written to the PCI configuration register is returned.\r |
| 731 | This function must guarantee that all PCI read and write operations are serialized.\r |
| badcbfb2 |
732 | \r |
| fb3df220 |
733 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
734 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
735 | \r |
| 736 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 7d9333a9 |
737 | @param AndData The value to AND with the PCI configuration register.\r |
| fb3df220 |
738 | @param OrData The value to OR with the PCI configuration register.\r |
| 739 | \r |
| 740 | @return The value written to the PCI configuration register.\r |
| 741 | \r |
| 742 | **/\r |
| 743 | UINT32\r |
| 744 | EFIAPI\r |
| 745 | PciSegmentAndThenOr32 (\r |
| 746 | IN UINT64 Address,\r |
| 747 | IN UINT32 AndData,\r |
| 748 | IN UINT32 OrData\r |
| ed66e1bc |
749 | );\r |
| fb3df220 |
750 | \r |
| 751 | /**\r |
| 752 | Reads a bit field of a PCI configuration register.\r |
| 753 | \r |
| 754 | Reads the bit field in a 32-bit PCI configuration register.\r |
| 755 | The bit field is specified by the StartBit and the EndBit.\r |
| 756 | The value of the bit field is returned.\r |
| badcbfb2 |
757 | \r |
| fb3df220 |
758 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
759 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
760 | If StartBit is greater than 7, then ASSERT().\r |
| 761 | If EndBit is greater than 7, then ASSERT().\r |
| 762 | If EndBit is less than StartBit, then ASSERT().\r |
| 763 | \r |
| 764 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 765 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 766 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 767 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 768 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 769 | \r |
| 770 | @return The value of the bit field.\r |
| 771 | \r |
| 772 | **/\r |
| 773 | UINT32\r |
| 774 | EFIAPI\r |
| 775 | PciSegmentBitFieldRead32 (\r |
| 776 | IN UINT64 Address,\r |
| 777 | IN UINTN StartBit,\r |
| 778 | IN UINTN EndBit\r |
| ed66e1bc |
779 | );\r |
| fb3df220 |
780 | \r |
| 781 | /**\r |
| 782 | Writes a bit field to a PCI configuration register.\r |
| 783 | \r |
| 784 | Writes Value to the bit field of the PCI configuration register.\r |
| 785 | The bit field is specified by the StartBit and the EndBit.\r |
| 786 | All other bits in the destination PCI configuration register are preserved.\r |
| 787 | The new value of the 32-bit register is returned.\r |
| badcbfb2 |
788 | \r |
| fb3df220 |
789 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
790 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
791 | If StartBit is greater than 7, then ASSERT().\r |
| 792 | If EndBit is greater than 7, then ASSERT().\r |
| 793 | If EndBit is less than StartBit, then ASSERT().\r |
| 794 | \r |
| 795 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 796 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 797 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 798 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 799 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 800 | @param Value New value of the bit field.\r |
| 801 | \r |
| 802 | @return The new value of the 32-bit register.\r |
| 803 | \r |
| 804 | **/\r |
| 805 | UINT32\r |
| 806 | EFIAPI\r |
| 807 | PciSegmentBitFieldWrite32 (\r |
| 808 | IN UINT64 Address,\r |
| 809 | IN UINTN StartBit,\r |
| 810 | IN UINTN EndBit,\r |
| 811 | IN UINT32 Value\r |
| ed66e1bc |
812 | );\r |
| fb3df220 |
813 | \r |
| 814 | /**\r |
| 815 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 816 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 817 | and writes the result to the 32-bit PCI configuration register specified by Address. \r |
| badcbfb2 |
818 | \r |
| 819 | If any reserved bits in Address are set, then ASSERT().\r |
| 820 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 821 | If StartBit is greater than 7, then ASSERT().\r |
| 822 | If EndBit is greater than 7, then ASSERT().\r |
| 823 | If EndBit is less than StartBit, then ASSERT().\r |
| 824 | \r |
| fb3df220 |
825 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 826 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 827 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 828 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 829 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 830 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 831 | \r |
| 832 | @return The value written to the PCI configuration register.\r |
| 833 | \r |
| 834 | **/\r |
| 835 | UINT32\r |
| 836 | EFIAPI\r |
| 837 | PciSegmentBitFieldOr32 (\r |
| 838 | IN UINT64 Address,\r |
| 839 | IN UINTN StartBit,\r |
| 840 | IN UINTN EndBit,\r |
| 841 | IN UINT32 OrData\r |
| ed66e1bc |
842 | );\r |
| fb3df220 |
843 | \r |
| 844 | /**\r |
| 845 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,\r |
| 846 | and writes the result back to the bit field in the 32-bit port.\r |
| 847 | \r |
| 848 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 849 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r |
| 850 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 851 | The value written to the PCI configuration register is returned.\r |
| 852 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 853 | Extra left bits in OrData are stripped.\r |
| badcbfb2 |
854 | \r |
| fb3df220 |
855 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
856 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
857 | If StartBit is greater than 7, then ASSERT().\r |
| 858 | If EndBit is greater than 7, then ASSERT().\r |
| 859 | If EndBit is less than StartBit, then ASSERT().\r |
| 860 | \r |
| 861 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 862 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 863 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 864 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 865 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 866 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 867 | \r |
| 868 | @return The value written to the PCI configuration register.\r |
| 869 | \r |
| 870 | **/\r |
| 871 | UINT32\r |
| 872 | EFIAPI\r |
| 873 | PciSegmentBitFieldAnd32 (\r |
| 874 | IN UINT64 Address,\r |
| 875 | IN UINTN StartBit,\r |
| 876 | IN UINTN EndBit,\r |
| 877 | IN UINT32 AndData\r |
| ed66e1bc |
878 | );\r |
| fb3df220 |
879 | \r |
| 880 | /**\r |
| 881 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,\r |
| 882 | and writes the result back to the bit field in the 32-bit register.\r |
| 883 | \r |
| 884 | Reads the 32-bit PCI configuration register specified by Address,\r |
| 885 | performs a bitwise AND between the read result and the value specified by AndData,\r |
| 886 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
| 887 | The value written to the PCI configuration register is returned.\r |
| 888 | This function must guarantee that all PCI read and write operations are serialized.\r |
| 889 | Extra left bits in AndData are stripped.\r |
| badcbfb2 |
890 | \r |
| fb3df220 |
891 | If any reserved bits in Address are set, then ASSERT().\r |
| badcbfb2 |
892 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| fb3df220 |
893 | If StartBit is greater than 7, then ASSERT().\r |
| 894 | If EndBit is greater than 7, then ASSERT().\r |
| 895 | If EndBit is less than StartBit, then ASSERT().\r |
| 896 | \r |
| 897 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 898 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 899 | The ordinal of the least significant bit in a byte is bit 0.\r |
| 900 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 901 | The ordinal of the most significant bit in a byte is bit 7.\r |
| 902 | @param AndData The value to AND with the read value from the PCI configuration register.\r |
| 903 | @param OrData The value to OR with the read value from the PCI configuration register.\r |
| 904 | \r |
| 905 | @return The value written to the PCI configuration register.\r |
| 906 | \r |
| 907 | **/\r |
| 908 | UINT32\r |
| 909 | EFIAPI\r |
| 910 | PciSegmentBitFieldAndThenOr32 (\r |
| 911 | IN UINT64 Address,\r |
| 912 | IN UINTN StartBit,\r |
| 913 | IN UINTN EndBit,\r |
| 914 | IN UINT32 AndData,\r |
| 915 | IN UINT32 OrData\r |
| ed66e1bc |
916 | );\r |
| fb3df220 |
917 | \r |
| 918 | /**\r |
| 919 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 920 | \r |
| 921 | Reads the range of PCI configuration registers specified by StartAddress\r |
| 922 | and Size into the buffer specified by Buffer.\r |
| 923 | This function only allows the PCI configuration registers from a single PCI function to be read.\r |
| 924 | Size is returned.\r |
| badcbfb2 |
925 | \r |
| fb3df220 |
926 | If any reserved bits in StartAddress are set, then ASSERT().\r |
| 927 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 928 | If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r |
| badcbfb2 |
929 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| fb3df220 |
930 | \r |
| 931 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 932 | @param Size Size in bytes of the transfer.\r |
| 933 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 934 | \r |
| badcbfb2 |
935 | @return The parameter of Size.\r |
| fb3df220 |
936 | \r |
| 937 | **/\r |
| 938 | UINTN\r |
| 939 | EFIAPI\r |
| 940 | PciSegmentReadBuffer (\r |
| 941 | IN UINT64 StartAddress,\r |
| 942 | IN UINTN Size,\r |
| 943 | OUT VOID *Buffer\r |
| ed66e1bc |
944 | );\r |
| fb3df220 |
945 | \r |
| 946 | /**\r |
| 947 | Copies the data in a caller supplied buffer to a specified range of PCI configuration space.\r |
| 948 | \r |
| 949 | Writes the range of PCI configuration registers specified by StartAddress\r |
| 950 | and Size from the buffer specified by Buffer.\r |
| 951 | This function only allows the PCI configuration registers from a single PCI function to be written.\r |
| 952 | Size is returned.\r |
| badcbfb2 |
953 | \r |
| fb3df220 |
954 | If any reserved bits in StartAddress are set, then ASSERT().\r |
| 955 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 956 | If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r |
| 957 | If Buffer is NULL, then ASSERT().\r |
| 958 | \r |
| 959 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
| 960 | @param Size Size in bytes of the transfer.\r |
| 961 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 962 | \r |
| badcbfb2 |
963 | @return The parameter of Size.\r |
| fb3df220 |
964 | \r |
| 965 | **/\r |
| 966 | UINTN\r |
| 967 | EFIAPI\r |
| 968 | PciSegmentWriteBuffer (\r |
| 969 | IN UINT64 StartAddress,\r |
| 970 | IN UINTN Size,\r |
| 971 | IN VOID *Buffer\r |
| ed66e1bc |
972 | );\r |
| fb3df220 |
973 | \r |
| 974 | #endif\r |
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