MdePkg/PciSegmentLib: Fix typo in function header comments
[mirror_edk2.git] / MdePkg / Include / Library / PciSegmentLib.h
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fb3df220 1/** @file\r
50a64e5b 2 Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r
badcbfb2 3 \r
4 The PCI Segment Library function provide services to read, write, and modify the PCI configuration\r
5 registers on PCI root bridges on any supported PCI segment. These library services take a single \r
6 address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register. \r
7 The layout of this address parameter is as follows:\r
8 \r
40731047 9 PCI Register: Bits 0..11\r
10 PCI Function Bits 12..14\r
11 PCI Device Bits 15..19\r
12 PCI Bus Bits 20..27\r
13 Reserved Bits 28..31. Must be 0.\r
14 PCI Segment Bits 32..47\r
15 Reserved Bits 48..63. Must be 0.\r
badcbfb2 16 \r
17 | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r
18 63 48 47 32 31 28 27 20 19 15 14 12 11 0\r
19\r
20 These functions perform PCI configuration cycles using the default PCI configuration access \r
21 method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it \r
22 may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate \r
23 access method. Modules will typically use the PCI Segment Library for its PCI configuration \r
24 accesses when PCI Segments other than Segment #0 must be accessed. \r
fb3df220 25\r
ebdde8ff 26Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
9df063a0 27This program and the accompanying materials\r
50a64e5b 28are licensed and made available under the terms and conditions of the BSD License\r
29which accompanies this distribution. The full text of the license may be found at\r
30http://opensource.org/licenses/bsd-license.php\r
fb3df220 31\r
50a64e5b 32THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
33WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
fb3df220 34\r
fb3df220 35**/\r
36\r
37#ifndef __PCI_SEGMENT_LIB__\r
38#define __PCI_SEGMENT_LIB__\r
39\r
40\r
41/**\r
42 Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r
43 and PCI Register to an address that can be passed to the PCI Segment Library functions.\r
44\r
45 Computes an address that is compatible with the PCI Segment Library functions.\r
46 The unused upper bits of Segment, Bus, Device, Function,\r
47 and Register are stripped prior to the generation of the address.\r
48\r
49 @param Segment PCI Segment number. Range 0..65535.\r
50 @param Bus PCI Bus number. Range 0..255.\r
51 @param Device PCI Device number. Range 0..31.\r
52 @param Function PCI Function number. Range 0..7.\r
53 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r
54\r
55 @return The address that is compatible with the PCI Segment Library functions.\r
56\r
57**/\r
58#define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r
2b27b557
MK
59 ((Segment != 0) ? \\r
60 ( ((Register) & 0xfff) | \\r
61 (((Function) & 0x07) << 12) | \\r
62 (((Device) & 0x1f) << 15) | \\r
63 (((Bus) & 0xff) << 20) | \\r
64 (LShiftU64 ((Segment) & 0xffff, 32)) \\r
65 ) : \\r
66 ( ((Register) & 0xfff) | \\r
67 (((Function) & 0x07) << 12) | \\r
68 (((Device) & 0x1f) << 15) | \\r
69 (((Bus) & 0xff) << 20) \\r
70 ) \\r
fb3df220 71 )\r
72\r
f926e538 73/**\r
74 Register a PCI device so PCI configuration registers may be accessed after \r
75 SetVirtualAddressMap().\r
76 \r
59ceeabe 77 If any reserved bits in Address are set, then ASSERT().\r
f926e538 78\r
79 @param Address Address that encodes the PCI Bus, Device, Function and\r
80 Register.\r
81 \r
82 @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
83 @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
84 after ExitBootServices().\r
85 @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
86 at runtime could not be mapped.\r
87 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r
88 complete the registration.\r
89\r
90**/\r
91RETURN_STATUS\r
92EFIAPI\r
93PciSegmentRegisterForRuntimeAccess (\r
94 IN UINTN Address\r
95 );\r
96\r
fb3df220 97/**\r
98 Reads an 8-bit PCI configuration register.\r
99\r
100 Reads and returns the 8-bit PCI configuration register specified by Address.\r
101 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 102\r
fb3df220 103 If any reserved bits in Address are set, then ASSERT().\r
ebdde8ff 104\r
fb3df220 105 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
106\r
107 @return The 8-bit PCI configuration register specified by Address.\r
108\r
109**/\r
110UINT8\r
111EFIAPI\r
112PciSegmentRead8 (\r
113 IN UINT64 Address\r
ed66e1bc 114 );\r
fb3df220 115\r
116/**\r
117 Writes an 8-bit PCI configuration register.\r
118\r
119 Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
120 Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 121\r
59ceeabe 122 If any reserved bits in Address are set, then ASSERT().\r
fb3df220 123\r
124 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
125 @param Value The value to write.\r
126\r
d5979dc0 127 @return The value written to the PCI configuration register.\r
fb3df220 128\r
129**/\r
130UINT8\r
131EFIAPI\r
132PciSegmentWrite8 (\r
133 IN UINT64 Address,\r
134 IN UINT8 Value\r
ed66e1bc 135 );\r
fb3df220 136\r
137/**\r
62991af2 138 Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r
fb3df220 139\r
140 Reads the 8-bit PCI configuration register specified by Address,\r
62991af2 141 performs a bitwise OR between the read result and the value specified by OrData,\r
fb3df220 142 and writes the result to the 8-bit PCI configuration register specified by Address.\r
143 The value written to the PCI configuration register is returned.\r
144 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 145\r
fb3df220 146 If any reserved bits in Address are set, then ASSERT().\r
147\r
148 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
149 @param OrData The value to OR with the PCI configuration register.\r
150\r
151 @return The value written to the PCI configuration register.\r
152\r
153**/\r
154UINT8\r
155EFIAPI\r
156PciSegmentOr8 (\r
157 IN UINT64 Address,\r
158 IN UINT8 OrData\r
ed66e1bc 159 );\r
fb3df220 160\r
161/**\r
162 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r
163\r
164 Reads the 8-bit PCI configuration register specified by Address,\r
165 performs a bitwise AND between the read result and the value specified by AndData,\r
166 and writes the result to the 8-bit PCI configuration register specified by Address.\r
167 The value written to the PCI configuration register is returned.\r
168 This function must guarantee that all PCI read and write operations are serialized.\r
169 If any reserved bits in Address are set, then ASSERT().\r
170\r
171 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
7d9333a9 172 @param AndData The value to AND with the PCI configuration register.\r
fb3df220 173\r
174 @return The value written to the PCI configuration register.\r
175\r
176**/\r
177UINT8\r
178EFIAPI\r
179PciSegmentAnd8 (\r
180 IN UINT64 Address,\r
181 IN UINT8 AndData\r
ed66e1bc 182 );\r
fb3df220 183\r
184/**\r
185 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
62991af2 186 followed a bitwise OR with another 8-bit value.\r
ebdde8ff 187\r
fb3df220 188 Reads the 8-bit PCI configuration register specified by Address,\r
189 performs a bitwise AND between the read result and the value specified by AndData,\r
62991af2 190 performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
fb3df220 191 and writes the result to the 8-bit PCI configuration register specified by Address.\r
192 The value written to the PCI configuration register is returned.\r
193 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 194\r
fb3df220 195 If any reserved bits in Address are set, then ASSERT().\r
196\r
197 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
ebdde8ff 198 @param AndData The value to AND with the PCI configuration register.\r
fb3df220 199 @param OrData The value to OR with the PCI configuration register.\r
200\r
201 @return The value written to the PCI configuration register.\r
202\r
203**/\r
204UINT8\r
205EFIAPI\r
206PciSegmentAndThenOr8 (\r
207 IN UINT64 Address,\r
208 IN UINT8 AndData,\r
209 IN UINT8 OrData\r
ed66e1bc 210 );\r
fb3df220 211\r
212/**\r
213 Reads a bit field of a PCI configuration register.\r
214\r
d5979dc0 215 Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
216 specified by the StartBit and the EndBit. The value of the bit field is\r
217 returned.\r
218\r
fb3df220 219 If any reserved bits in Address are set, then ASSERT().\r
220 If StartBit is greater than 7, then ASSERT().\r
221 If EndBit is greater than 7, then ASSERT().\r
222 If EndBit is less than StartBit, then ASSERT().\r
223\r
d5979dc0 224 @param Address PCI configuration register to read.\r
fb3df220 225 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 226 Range 0..7.\r
fb3df220 227 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 228 Range 0..7.\r
fb3df220 229\r
d5979dc0 230 @return The value of the bit field read from the PCI configuration register.\r
fb3df220 231\r
232**/\r
233UINT8\r
234EFIAPI\r
235PciSegmentBitFieldRead8 (\r
236 IN UINT64 Address,\r
237 IN UINTN StartBit,\r
238 IN UINTN EndBit\r
ed66e1bc 239 );\r
fb3df220 240\r
241/**\r
242 Writes a bit field to a PCI configuration register.\r
243\r
d5979dc0 244 Writes Value to the bit field of the PCI configuration register. The bit\r
245 field is specified by the StartBit and the EndBit. All other bits in the\r
246 destination PCI configuration register are preserved. The new value of the\r
247 8-bit register is returned.\r
248\r
fb3df220 249 If any reserved bits in Address are set, then ASSERT().\r
250 If StartBit is greater than 7, then ASSERT().\r
251 If EndBit is greater than 7, then ASSERT().\r
252 If EndBit is less than StartBit, then ASSERT().\r
94952554 253 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
fb3df220 254\r
d5979dc0 255 @param Address PCI configuration register to write.\r
fb3df220 256 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 257 Range 0..7.\r
fb3df220 258 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 259 Range 0..7.\r
fb3df220 260 @param Value New value of the bit field.\r
261\r
d5979dc0 262 @return The value written back to the PCI configuration register.\r
fb3df220 263\r
264**/\r
265UINT8\r
266EFIAPI\r
267PciSegmentBitFieldWrite8 (\r
268 IN UINT64 Address,\r
269 IN UINTN StartBit,\r
270 IN UINTN EndBit,\r
271 IN UINT8 Value\r
ed66e1bc 272 );\r
fb3df220 273\r
274/**\r
d5979dc0 275 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
276 writes the result back to the bit field in the 8-bit port.\r
277\r
278 Reads the 8-bit PCI configuration register specified by Address, performs a\r
62991af2 279 bitwise OR between the read result and the value specified by\r
d5979dc0 280 OrData, and writes the result to the 8-bit PCI configuration register\r
281 specified by Address. The value written to the PCI configuration register is\r
282 returned. This function must guarantee that all PCI read and write operations\r
283 are serialized. Extra left bits in OrData are stripped.\r
284\r
badcbfb2 285 If any reserved bits in Address are set, then ASSERT().\r
286 If StartBit is greater than 7, then ASSERT().\r
287 If EndBit is greater than 7, then ASSERT().\r
288 If EndBit is less than StartBit, then ASSERT().\r
94952554 289 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
fb3df220 290\r
d5979dc0 291 @param Address PCI configuration register to write.\r
fb3df220 292 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 293 Range 0..7.\r
fb3df220 294 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 295 Range 0..7.\r
296 @param OrData The value to OR with the PCI configuration register.\r
fb3df220 297\r
d5979dc0 298 @return The value written back to the PCI configuration register.\r
fb3df220 299\r
300**/\r
301UINT8\r
302EFIAPI\r
303PciSegmentBitFieldOr8 (\r
304 IN UINT64 Address,\r
305 IN UINTN StartBit,\r
306 IN UINTN EndBit,\r
307 IN UINT8 OrData\r
ed66e1bc 308 );\r
fb3df220 309\r
310/**\r
d5979dc0 311 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
312 AND, and writes the result back to the bit field in the 8-bit register.\r
313\r
314 Reads the 8-bit PCI configuration register specified by Address, performs a\r
315 bitwise AND between the read result and the value specified by AndData, and\r
316 writes the result to the 8-bit PCI configuration register specified by\r
317 Address. The value written to the PCI configuration register is returned.\r
318 This function must guarantee that all PCI read and write operations are\r
319 serialized. Extra left bits in AndData are stripped.\r
fb3df220 320\r
fb3df220 321 If any reserved bits in Address are set, then ASSERT().\r
322 If StartBit is greater than 7, then ASSERT().\r
323 If EndBit is greater than 7, then ASSERT().\r
324 If EndBit is less than StartBit, then ASSERT().\r
94952554 325 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
fb3df220 326\r
d5979dc0 327 @param Address PCI configuration register to write.\r
fb3df220 328 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 329 Range 0..7.\r
fb3df220 330 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 331 Range 0..7.\r
332 @param AndData The value to AND with the PCI configuration register.\r
fb3df220 333\r
d5979dc0 334 @return The value written back to the PCI configuration register.\r
fb3df220 335\r
336**/\r
337UINT8\r
338EFIAPI\r
339PciSegmentBitFieldAnd8 (\r
340 IN UINT64 Address,\r
341 IN UINTN StartBit,\r
342 IN UINTN EndBit,\r
343 IN UINT8 AndData\r
ed66e1bc 344 );\r
fb3df220 345\r
346/**\r
d5979dc0 347 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
ebdde8ff 348 bitwise OR, and writes the result back to the bit field in the 8-bit port.\r
d5979dc0 349\r
350 Reads the 8-bit PCI configuration register specified by Address, performs a\r
62991af2 351 bitwise AND followed by a bitwise OR between the read result and\r
d5979dc0 352 the value specified by AndData, and writes the result to the 8-bit PCI\r
353 configuration register specified by Address. The value written to the PCI\r
354 configuration register is returned. This function must guarantee that all PCI\r
355 read and write operations are serialized. Extra left bits in both AndData and\r
356 OrData are stripped.\r
357\r
fb3df220 358 If any reserved bits in Address are set, then ASSERT().\r
359 If StartBit is greater than 7, then ASSERT().\r
360 If EndBit is greater than 7, then ASSERT().\r
361 If EndBit is less than StartBit, then ASSERT().\r
94952554
LG
362 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
363 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
fb3df220 364\r
d5979dc0 365 @param Address PCI configuration register to write.\r
fb3df220 366 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 367 Range 0..7.\r
fb3df220 368 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 369 Range 0..7.\r
370 @param AndData The value to AND with the PCI configuration register.\r
371 @param OrData The value to OR with the result of the AND operation.\r
fb3df220 372\r
d5979dc0 373 @return The value written back to the PCI configuration register.\r
fb3df220 374\r
375**/\r
376UINT8\r
377EFIAPI\r
378PciSegmentBitFieldAndThenOr8 (\r
379 IN UINT64 Address,\r
380 IN UINTN StartBit,\r
381 IN UINTN EndBit,\r
382 IN UINT8 AndData,\r
383 IN UINT8 OrData\r
ed66e1bc 384 );\r
fb3df220 385\r
386/**\r
387 Reads a 16-bit PCI configuration register.\r
388\r
389 Reads and returns the 16-bit PCI configuration register specified by Address.\r
390 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 391\r
fb3df220 392 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 393 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
ebdde8ff 394\r
fb3df220 395 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
396\r
397 @return The 16-bit PCI configuration register specified by Address.\r
398\r
399**/\r
400UINT16\r
401EFIAPI\r
402PciSegmentRead16 (\r
403 IN UINT64 Address\r
ed66e1bc 404 );\r
fb3df220 405\r
406/**\r
407 Writes a 16-bit PCI configuration register.\r
408\r
409 Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r
410 Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 411\r
badcbfb2 412 If any reserved bits in Address are set, then ASSERT().\r
413 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
fb3df220 414\r
415 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
416 @param Value The value to write.\r
417\r
418 @return The parameter of Value.\r
419\r
420**/\r
421UINT16\r
422EFIAPI\r
423PciSegmentWrite16 (\r
424 IN UINT64 Address,\r
425 IN UINT16 Value\r
ed66e1bc 426 );\r
fb3df220 427\r
428/**\r
62991af2 429 Performs a bitwise OR of a 16-bit PCI configuration register with\r
d5979dc0 430 a 16-bit value.\r
431\r
432 Reads the 16-bit PCI configuration register specified by Address, performs a\r
ebdde8ff
RN
433 bitwise OR between the read result and the value specified by OrData, and\r
434 writes the result to the 16-bit PCI configuration register specified by Address.\r
435 The value written to the PCI configuration register is returned. This function\r
436 must guarantee that all PCI read and write operations are serialized.\r
fb3df220 437\r
fb3df220 438 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 439 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
fb3df220 440\r
d5979dc0 441 @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
442 Register.\r
443 @param OrData The value to OR with the PCI configuration register.\r
fb3df220 444\r
d5979dc0 445 @return The value written back to the PCI configuration register.\r
fb3df220 446\r
447**/\r
448UINT16\r
449EFIAPI\r
450PciSegmentOr16 (\r
451 IN UINT64 Address,\r
452 IN UINT16 OrData\r
ed66e1bc 453 );\r
fb3df220 454\r
455/**\r
456 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r
457\r
458 Reads the 16-bit PCI configuration register specified by Address,\r
459 performs a bitwise AND between the read result and the value specified by AndData,\r
460 and writes the result to the 16-bit PCI configuration register specified by Address.\r
461 The value written to the PCI configuration register is returned.\r
462 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 463\r
fb3df220 464 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 465 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
ebdde8ff 466\r
fb3df220 467 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
7d9333a9 468 @param AndData The value to AND with the PCI configuration register.\r
fb3df220 469\r
470 @return The value written to the PCI configuration register.\r
471\r
472**/\r
473UINT16\r
474EFIAPI\r
475PciSegmentAnd16 (\r
476 IN UINT64 Address,\r
477 IN UINT16 AndData\r
ed66e1bc 478 );\r
fb3df220 479\r
480/**\r
481 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
62991af2 482 followed a bitwise OR with another 16-bit value.\r
ebdde8ff 483\r
fb3df220 484 Reads the 16-bit PCI configuration register specified by Address,\r
485 performs a bitwise AND between the read result and the value specified by AndData,\r
62991af2 486 performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
fb3df220 487 and writes the result to the 16-bit PCI configuration register specified by Address.\r
488 The value written to the PCI configuration register is returned.\r
489 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 490\r
fb3df220 491 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 492 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
fb3df220 493\r
494 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
ebdde8ff 495 @param AndData The value to AND with the PCI configuration register.\r
fb3df220 496 @param OrData The value to OR with the PCI configuration register.\r
497\r
498 @return The value written to the PCI configuration register.\r
499\r
500**/\r
501UINT16\r
502EFIAPI\r
503PciSegmentAndThenOr16 (\r
504 IN UINT64 Address,\r
505 IN UINT16 AndData,\r
506 IN UINT16 OrData\r
ed66e1bc 507 );\r
fb3df220 508\r
509/**\r
510 Reads a bit field of a PCI configuration register.\r
511\r
d5979dc0 512 Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
513 specified by the StartBit and the EndBit. The value of the bit field is\r
514 returned.\r
515\r
fb3df220 516 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 517 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
d5979dc0 518 If StartBit is greater than 15, then ASSERT().\r
519 If EndBit is greater than 15, then ASSERT().\r
fb3df220 520 If EndBit is less than StartBit, then ASSERT().\r
521\r
d5979dc0 522 @param Address PCI configuration register to read.\r
fb3df220 523 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 524 Range 0..15.\r
fb3df220 525 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 526 Range 0..15.\r
fb3df220 527\r
d5979dc0 528 @return The value of the bit field read from the PCI configuration register.\r
fb3df220 529\r
530**/\r
531UINT16\r
532EFIAPI\r
533PciSegmentBitFieldRead16 (\r
534 IN UINT64 Address,\r
535 IN UINTN StartBit,\r
536 IN UINTN EndBit\r
ed66e1bc 537 );\r
fb3df220 538\r
539/**\r
540 Writes a bit field to a PCI configuration register.\r
541\r
d5979dc0 542 Writes Value to the bit field of the PCI configuration register. The bit\r
543 field is specified by the StartBit and the EndBit. All other bits in the\r
544 destination PCI configuration register are preserved. The new value of the\r
545 16-bit register is returned.\r
546\r
fb3df220 547 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 548 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
d5979dc0 549 If StartBit is greater than 15, then ASSERT().\r
550 If EndBit is greater than 15, then ASSERT().\r
fb3df220 551 If EndBit is less than StartBit, then ASSERT().\r
94952554 552 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
fb3df220 553\r
d5979dc0 554 @param Address PCI configuration register to write.\r
fb3df220 555 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 556 Range 0..15.\r
fb3df220 557 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 558 Range 0..15.\r
fb3df220 559 @param Value New value of the bit field.\r
560\r
d5979dc0 561 @return The value written back to the PCI configuration register.\r
fb3df220 562\r
563**/\r
564UINT16\r
565EFIAPI\r
566PciSegmentBitFieldWrite16 (\r
567 IN UINT64 Address,\r
568 IN UINTN StartBit,\r
569 IN UINTN EndBit,\r
570 IN UINT16 Value\r
ed66e1bc 571 );\r
fb3df220 572\r
573/**\r
ebdde8ff
RN
574 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r
575 the result back to the bit field in the 16-bit port.\r
576\r
577 Reads the 16-bit PCI configuration register specified by Address, performs a\r
578 bitwise OR between the read result and the value specified by\r
579 OrData, and writes the result to the 16-bit PCI configuration register\r
580 specified by Address. The value written to the PCI configuration register is\r
581 returned. This function must guarantee that all PCI read and write operations\r
582 are serialized. Extra left bits in OrData are stripped.\r
fb3df220 583\r
badcbfb2 584 If any reserved bits in Address are set, then ASSERT().\r
585 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
586 If StartBit is greater than 15, then ASSERT().\r
587 If EndBit is greater than 15, then ASSERT().\r
588 If EndBit is less than StartBit, then ASSERT().\r
94952554 589 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
badcbfb2 590\r
d5979dc0 591 @param Address PCI configuration register to write.\r
fb3df220 592 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 593 Range 0..15.\r
fb3df220 594 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 595 Range 0..15.\r
596 @param OrData The value to OR with the PCI configuration register.\r
fb3df220 597\r
d5979dc0 598 @return The value written back to the PCI configuration register.\r
fb3df220 599\r
600**/\r
601UINT16\r
602EFIAPI\r
603PciSegmentBitFieldOr16 (\r
604 IN UINT64 Address,\r
605 IN UINTN StartBit,\r
606 IN UINTN EndBit,\r
607 IN UINT16 OrData\r
ed66e1bc 608 );\r
fb3df220 609\r
610/**\r
ebdde8ff
RN
611 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
612 AND, writes the result back to the bit field in the 16-bit register.\r
613\r
614 Reads the 16-bit PCI configuration register specified by Address, performs a\r
615 bitwise AND between the read result and the value specified by AndData, and\r
616 writes the result to the 16-bit PCI configuration register specified by\r
617 Address. The value written to the PCI configuration register is returned.\r
618 This function must guarantee that all PCI read and write operations are\r
619 serialized. Extra left bits in AndData are stripped.\r
fb3df220 620\r
fb3df220 621 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 622 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
ebdde8ff
RN
623 If StartBit is greater than 15, then ASSERT().\r
624 If EndBit is greater than 15, then ASSERT().\r
fb3df220 625 If EndBit is less than StartBit, then ASSERT().\r
94952554 626 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
fb3df220 627\r
628 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
629 @param StartBit The ordinal of the least significant bit in the bit field.\r
ebdde8ff 630 Range 0..15.\r
fb3df220 631 @param EndBit The ordinal of the most significant bit in the bit field.\r
ebdde8ff
RN
632 Range 0..15.\r
633 @param AndData The value to AND with the PCI configuration register.\r
fb3df220 634\r
ebdde8ff 635 @return The value written back to the PCI configuration register.\r
fb3df220 636\r
637**/\r
638UINT16\r
639EFIAPI\r
640PciSegmentBitFieldAnd16 (\r
641 IN UINT64 Address,\r
642 IN UINTN StartBit,\r
643 IN UINTN EndBit,\r
644 IN UINT16 AndData\r
ed66e1bc 645 );\r
fb3df220 646\r
647/**\r
d5979dc0 648 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
62991af2 649 bitwise OR, and writes the result back to the bit field in the\r
d5979dc0 650 16-bit port.\r
651\r
652 Reads the 16-bit PCI configuration register specified by Address, performs a\r
62991af2 653 bitwise AND followed by a bitwise OR between the read result and\r
d5979dc0 654 the value specified by AndData, and writes the result to the 16-bit PCI\r
655 configuration register specified by Address. The value written to the PCI\r
656 configuration register is returned. This function must guarantee that all PCI\r
657 read and write operations are serialized. Extra left bits in both AndData and\r
658 OrData are stripped.\r
659\r
fb3df220 660 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 661 If StartBit is greater than 15, then ASSERT().\r
662 If EndBit is greater than 15, then ASSERT().\r
fb3df220 663 If EndBit is less than StartBit, then ASSERT().\r
94952554
LG
664 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
665 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
fb3df220 666\r
d5979dc0 667 @param Address PCI configuration register to write.\r
fb3df220 668 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 669 Range 0..15.\r
fb3df220 670 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 671 Range 0..15.\r
672 @param AndData The value to AND with the PCI configuration register.\r
673 @param OrData The value to OR with the result of the AND operation.\r
fb3df220 674\r
d5979dc0 675 @return The value written back to the PCI configuration register.\r
fb3df220 676\r
677**/\r
678UINT16\r
679EFIAPI\r
680PciSegmentBitFieldAndThenOr16 (\r
681 IN UINT64 Address,\r
682 IN UINTN StartBit,\r
683 IN UINTN EndBit,\r
684 IN UINT16 AndData,\r
685 IN UINT16 OrData\r
ed66e1bc 686 );\r
fb3df220 687\r
688/**\r
689 Reads a 32-bit PCI configuration register.\r
690\r
691 Reads and returns the 32-bit PCI configuration register specified by Address.\r
692 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 693\r
badcbfb2 694 If any reserved bits in Address are set, then ASSERT().\r
695 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
696\r
fb3df220 697 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
698\r
699 @return The 32-bit PCI configuration register specified by Address.\r
700\r
701**/\r
702UINT32\r
703EFIAPI\r
704PciSegmentRead32 (\r
705 IN UINT64 Address\r
ed66e1bc 706 );\r
fb3df220 707\r
708/**\r
709 Writes a 32-bit PCI configuration register.\r
710\r
711 Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r
712 Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 713\r
badcbfb2 714 If any reserved bits in Address are set, then ASSERT().\r
715 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
fb3df220 716\r
717 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
718 @param Value The value to write.\r
719\r
720 @return The parameter of Value.\r
721\r
722**/\r
723UINT32\r
724EFIAPI\r
725PciSegmentWrite32 (\r
726 IN UINT64 Address,\r
727 IN UINT32 Value\r
ed66e1bc 728 );\r
fb3df220 729\r
730/**\r
62991af2 731 Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r
fb3df220 732\r
733 Reads the 32-bit PCI configuration register specified by Address,\r
62991af2 734 performs a bitwise OR between the read result and the value specified by OrData,\r
fb3df220 735 and writes the result to the 32-bit PCI configuration register specified by Address.\r
736 The value written to the PCI configuration register is returned.\r
737 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 738\r
fb3df220 739 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 740 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
fb3df220 741\r
742 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
743 @param OrData The value to OR with the PCI configuration register.\r
744\r
745 @return The value written to the PCI configuration register.\r
746\r
747**/\r
748UINT32\r
749EFIAPI\r
750PciSegmentOr32 (\r
751 IN UINT64 Address,\r
752 IN UINT32 OrData\r
ed66e1bc 753 );\r
fb3df220 754\r
755/**\r
756 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r
757\r
758 Reads the 32-bit PCI configuration register specified by Address,\r
759 performs a bitwise AND between the read result and the value specified by AndData,\r
760 and writes the result to the 32-bit PCI configuration register specified by Address.\r
761 The value written to the PCI configuration register is returned.\r
762 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 763\r
fb3df220 764 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 765 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
fb3df220 766\r
767 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
7d9333a9 768 @param AndData The value to AND with the PCI configuration register.\r
fb3df220 769\r
770 @return The value written to the PCI configuration register.\r
771\r
772**/\r
773UINT32\r
774EFIAPI\r
775PciSegmentAnd32 (\r
776 IN UINT64 Address,\r
777 IN UINT32 AndData\r
ed66e1bc 778 );\r
fb3df220 779\r
780/**\r
781 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
62991af2 782 followed a bitwise OR with another 32-bit value.\r
ebdde8ff 783\r
fb3df220 784 Reads the 32-bit PCI configuration register specified by Address,\r
785 performs a bitwise AND between the read result and the value specified by AndData,\r
62991af2 786 performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
fb3df220 787 and writes the result to the 32-bit PCI configuration register specified by Address.\r
788 The value written to the PCI configuration register is returned.\r
789 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 790\r
fb3df220 791 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 792 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
fb3df220 793\r
794 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
7d9333a9 795 @param AndData The value to AND with the PCI configuration register.\r
fb3df220 796 @param OrData The value to OR with the PCI configuration register.\r
797\r
798 @return The value written to the PCI configuration register.\r
799\r
800**/\r
801UINT32\r
802EFIAPI\r
803PciSegmentAndThenOr32 (\r
804 IN UINT64 Address,\r
805 IN UINT32 AndData,\r
806 IN UINT32 OrData\r
ed66e1bc 807 );\r
fb3df220 808\r
809/**\r
810 Reads a bit field of a PCI configuration register.\r
811\r
d5979dc0 812 Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
813 specified by the StartBit and the EndBit. The value of the bit field is\r
814 returned.\r
815\r
fb3df220 816 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 817 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
d5979dc0 818 If StartBit is greater than 31, then ASSERT().\r
819 If EndBit is greater than 31, then ASSERT().\r
fb3df220 820 If EndBit is less than StartBit, then ASSERT().\r
821\r
d5979dc0 822 @param Address PCI configuration register to read.\r
fb3df220 823 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 824 Range 0..31.\r
fb3df220 825 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 826 Range 0..31.\r
fb3df220 827\r
d5979dc0 828 @return The value of the bit field read from the PCI configuration register.\r
fb3df220 829\r
830**/\r
831UINT32\r
832EFIAPI\r
833PciSegmentBitFieldRead32 (\r
834 IN UINT64 Address,\r
835 IN UINTN StartBit,\r
836 IN UINTN EndBit\r
ed66e1bc 837 );\r
fb3df220 838\r
839/**\r
840 Writes a bit field to a PCI configuration register.\r
841\r
d5979dc0 842 Writes Value to the bit field of the PCI configuration register. The bit\r
843 field is specified by the StartBit and the EndBit. All other bits in the\r
844 destination PCI configuration register are preserved. The new value of the\r
845 32-bit register is returned.\r
846\r
fb3df220 847 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 848 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
d5979dc0 849 If StartBit is greater than 31, then ASSERT().\r
850 If EndBit is greater than 31, then ASSERT().\r
fb3df220 851 If EndBit is less than StartBit, then ASSERT().\r
94952554 852 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
fb3df220 853\r
d5979dc0 854 @param Address PCI configuration register to write.\r
fb3df220 855 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 856 Range 0..31.\r
fb3df220 857 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 858 Range 0..31.\r
fb3df220 859 @param Value New value of the bit field.\r
860\r
d5979dc0 861 @return The value written back to the PCI configuration register.\r
fb3df220 862\r
863**/\r
864UINT32\r
865EFIAPI\r
866PciSegmentBitFieldWrite32 (\r
867 IN UINT64 Address,\r
868 IN UINTN StartBit,\r
869 IN UINTN EndBit,\r
870 IN UINT32 Value\r
ed66e1bc 871 );\r
fb3df220 872\r
873/**\r
d5979dc0 874 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
875 writes the result back to the bit field in the 32-bit port.\r
876\r
877 Reads the 32-bit PCI configuration register specified by Address, performs a\r
62991af2 878 bitwise OR between the read result and the value specified by\r
d5979dc0 879 OrData, and writes the result to the 32-bit PCI configuration register\r
880 specified by Address. The value written to the PCI configuration register is\r
881 returned. This function must guarantee that all PCI read and write operations\r
882 are serialized. Extra left bits in OrData are stripped.\r
883\r
badcbfb2 884 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 885 If StartBit is greater than 31, then ASSERT().\r
886 If EndBit is greater than 31, then ASSERT().\r
badcbfb2 887 If EndBit is less than StartBit, then ASSERT().\r
94952554 888 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
d5979dc0 889\r
890 @param Address PCI configuration register to write.\r
fb3df220 891 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 892 Range 0..31.\r
fb3df220 893 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 894 Range 0..31.\r
895 @param OrData The value to OR with the PCI configuration register.\r
fb3df220 896\r
d5979dc0 897 @return The value written back to the PCI configuration register.\r
fb3df220 898\r
899**/\r
900UINT32\r
901EFIAPI\r
902PciSegmentBitFieldOr32 (\r
903 IN UINT64 Address,\r
904 IN UINTN StartBit,\r
905 IN UINTN EndBit,\r
906 IN UINT32 OrData\r
ed66e1bc 907 );\r
fb3df220 908\r
909/**\r
d5979dc0 910 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
911 AND, and writes the result back to the bit field in the 32-bit register.\r
fb3df220 912\r
ebdde8ff 913\r
d5979dc0 914 Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r
915 AND between the read result and the value specified by AndData, and writes the result\r
916 to the 32-bit PCI configuration register specified by Address. The value written to\r
917 the PCI configuration register is returned. This function must guarantee that all PCI\r
918 read and write operations are serialized. Extra left bits in AndData are stripped.\r
fb3df220 919 If any reserved bits in Address are set, then ASSERT().\r
badcbfb2 920 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
d5979dc0 921 If StartBit is greater than 31, then ASSERT().\r
922 If EndBit is greater than 31, then ASSERT().\r
fb3df220 923 If EndBit is less than StartBit, then ASSERT().\r
94952554 924 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
fb3df220 925\r
ebdde8ff 926 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
fb3df220 927 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 928 Range 0..31.\r
fb3df220 929 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 930 Range 0..31.\r
931 @param AndData The value to AND with the PCI configuration register.\r
fb3df220 932\r
d5979dc0 933 @return The value written back to the PCI configuration register.\r
fb3df220 934\r
935**/\r
936UINT32\r
937EFIAPI\r
938PciSegmentBitFieldAnd32 (\r
939 IN UINT64 Address,\r
940 IN UINTN StartBit,\r
941 IN UINTN EndBit,\r
942 IN UINT32 AndData\r
ed66e1bc 943 );\r
fb3df220 944\r
945/**\r
d5979dc0 946 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
62991af2 947 bitwise OR, and writes the result back to the bit field in the\r
d5979dc0 948 32-bit port.\r
949\r
950 Reads the 32-bit PCI configuration register specified by Address, performs a\r
62991af2 951 bitwise AND followed by a bitwise OR between the read result and\r
d5979dc0 952 the value specified by AndData, and writes the result to the 32-bit PCI\r
953 configuration register specified by Address. The value written to the PCI\r
954 configuration register is returned. This function must guarantee that all PCI\r
955 read and write operations are serialized. Extra left bits in both AndData and\r
956 OrData are stripped.\r
957\r
fb3df220 958 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 959 If StartBit is greater than 31, then ASSERT().\r
960 If EndBit is greater than 31, then ASSERT().\r
fb3df220 961 If EndBit is less than StartBit, then ASSERT().\r
94952554
LG
962 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
963 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
fb3df220 964\r
d5979dc0 965 @param Address PCI configuration register to write.\r
fb3df220 966 @param StartBit The ordinal of the least significant bit in the bit field.\r
d5979dc0 967 Range 0..31.\r
fb3df220 968 @param EndBit The ordinal of the most significant bit in the bit field.\r
d5979dc0 969 Range 0..31.\r
970 @param AndData The value to AND with the PCI configuration register.\r
971 @param OrData The value to OR with the result of the AND operation.\r
fb3df220 972\r
d5979dc0 973 @return The value written back to the PCI configuration register.\r
fb3df220 974\r
975**/\r
976UINT32\r
977EFIAPI\r
978PciSegmentBitFieldAndThenOr32 (\r
979 IN UINT64 Address,\r
980 IN UINTN StartBit,\r
981 IN UINTN EndBit,\r
982 IN UINT32 AndData,\r
983 IN UINT32 OrData\r
ed66e1bc 984 );\r
fb3df220 985\r
986/**\r
987 Reads a range of PCI configuration registers into a caller supplied buffer.\r
988\r
d5979dc0 989 Reads the range of PCI configuration registers specified by StartAddress and\r
990 Size into the buffer specified by Buffer. This function only allows the PCI\r
991 configuration registers from a single PCI function to be read. Size is\r
992 returned. When possible 32-bit PCI configuration read cycles are used to read\r
993 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
994 and 16-bit PCI configuration read cycles may be used at the beginning and the\r
995 end of the range.\r
996\r
59ceeabe 997 If any reserved bits in StartAddress are set, then ASSERT().\r
fb3df220 998 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
badcbfb2 999 If Size > 0 and Buffer is NULL, then ASSERT().\r
fb3df220 1000\r
d5979dc0 1001 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
1002 Function and Register.\r
fb3df220 1003 @param Size Size in bytes of the transfer.\r
1004 @param Buffer Pointer to a buffer receiving the data read.\r
1005\r
d5979dc0 1006 @return Size\r
fb3df220 1007\r
1008**/\r
1009UINTN\r
1010EFIAPI\r
1011PciSegmentReadBuffer (\r
1012 IN UINT64 StartAddress,\r
1013 IN UINTN Size,\r
1014 OUT VOID *Buffer\r
ed66e1bc 1015 );\r
fb3df220 1016\r
1017/**\r
d5979dc0 1018 Copies the data in a caller supplied buffer to a specified range of PCI\r
1019 configuration space.\r
1020\r
1021 Writes the range of PCI configuration registers specified by StartAddress and\r
1022 Size from the buffer specified by Buffer. This function only allows the PCI\r
1023 configuration registers from a single PCI function to be written. Size is\r
1024 returned. When possible 32-bit PCI configuration write cycles are used to\r
1025 write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
1026 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
1027 and the end of the range.\r
1028\r
59ceeabe 1029 If any reserved bits in StartAddress are set, then ASSERT().\r
fb3df220 1030 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
d5979dc0 1031 If Size > 0 and Buffer is NULL, then ASSERT().\r
fb3df220 1032\r
d5979dc0 1033 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
1034 Function and Register.\r
fb3df220 1035 @param Size Size in bytes of the transfer.\r
1036 @param Buffer Pointer to a buffer containing the data to write.\r
1037\r
badcbfb2 1038 @return The parameter of Size.\r
fb3df220 1039\r
1040**/\r
1041UINTN\r
1042EFIAPI\r
1043PciSegmentWriteBuffer (\r
1044 IN UINT64 StartAddress,\r
1045 IN UINTN Size,\r
1046 IN VOID *Buffer\r
ed66e1bc 1047 );\r
fb3df220 1048\r
1049#endif\r