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1 | /** @file\r |
2 | The multiple segments PCI configuration Library Services that carry out\r | |
3 | PCI configuration and enable the PCI operations to be replayed during an\r | |
4 | S3 resume. This library class maps directly on top of the PciSegmentLib class.\r | |
5 | \r | |
6 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
7 | This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #ifndef __S3_PCI_SEGMENT_LIB__\r | |
18 | #define __S3_PCI_SEGMENT_LIB__\r | |
19 | \r | |
20 | \r | |
21 | /**\r | |
22 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r | |
23 | and PCI Register to an address that can be passed to the S3 PCI Segment Library functions.\r | |
24 | \r | |
25 | Computes an address that is compatible with the PCI Segment Library functions.\r | |
26 | The unused upper bits of Segment, Bus, Device, Function,\r | |
27 | and Register are stripped prior to the generation of the address.\r | |
28 | \r | |
29 | @param Segment PCI Segment number. Range 0..65535.\r | |
30 | @param Bus PCI Bus number. Range 0..255.\r | |
31 | @param Device PCI Device number. Range 0..31.\r | |
32 | @param Function PCI Function number. Range 0..7.\r | |
33 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r | |
34 | \r | |
35 | @return The address that is compatible with the PCI Segment Library functions.\r | |
36 | \r | |
37 | **/\r | |
38 | #define S3_PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r | |
39 | ((Segment != 0) ? \\r | |
40 | ( ((Register) & 0xfff) | \\r | |
41 | (((Function) & 0x07) << 12) | \\r | |
42 | (((Device) & 0x1f) << 15) | \\r | |
43 | (((Bus) & 0xff) << 20) | \\r | |
44 | (LShiftU64 ((Segment) & 0xffff, 32)) \\r | |
45 | ) : \\r | |
46 | ( ((Register) & 0xfff) | \\r | |
47 | (((Function) & 0x07) << 12) | \\r | |
48 | (((Device) & 0x1f) << 15) | \\r | |
49 | (((Bus) & 0xff) << 20) \\r | |
50 | ) \\r | |
51 | )\r | |
52 | \r | |
53 | /**\r | |
54 | Reads an 8-bit PCI configuration register, and saves the value in the S3 script to\r | |
55 | be replayed on S3 resume.\r | |
56 | \r | |
57 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
58 | This function must guarantee that all PCI read and write operations are serialized.\r | |
59 | \r | |
60 | If any reserved bits in Address are set, then ASSERT().\r | |
61 | \r | |
62 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
63 | \r | |
64 | @return The 8-bit PCI configuration register specified by Address.\r | |
65 | \r | |
66 | **/\r | |
67 | UINT8\r | |
68 | EFIAPI\r | |
69 | S3PciSegmentRead8 (\r | |
70 | IN UINT64 Address\r | |
71 | );\r | |
72 | \r | |
73 | /**\r | |
74 | Writes an 8-bit PCI configuration register, and saves the value in the S3 script to\r | |
75 | be replayed on S3 resume.\r | |
76 | \r | |
77 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r | |
78 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
79 | \r | |
80 | If any reserved bits in Address are set, then ASSERT().\r | |
81 | \r | |
82 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
83 | @param Value The value to write.\r | |
84 | \r | |
85 | @return The value written to the PCI configuration register.\r | |
86 | \r | |
87 | **/\r | |
88 | UINT8\r | |
89 | EFIAPI\r | |
90 | S3PciSegmentWrite8 (\r | |
91 | IN UINT64 Address,\r | |
92 | IN UINT8 Value\r | |
93 | );\r | |
94 | \r | |
95 | /**\r | |
96 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves\r | |
97 | the value in the S3 script to be replayed on S3 resume.\r | |
98 | \r | |
99 | Reads the 8-bit PCI configuration register specified by Address,\r | |
100 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
101 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
102 | The value written to the PCI configuration register is returned.\r | |
103 | This function must guarantee that all PCI read and write operations are serialized.\r | |
104 | \r | |
105 | If any reserved bits in Address are set, then ASSERT().\r | |
106 | \r | |
107 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
108 | @param OrData The value to OR with the PCI configuration register.\r | |
109 | \r | |
110 | @return The value written to the PCI configuration register.\r | |
111 | \r | |
112 | **/\r | |
113 | UINT8\r | |
114 | EFIAPI\r | |
115 | S3PciSegmentOr8 (\r | |
116 | IN UINT64 Address,\r | |
117 | IN UINT8 OrData\r | |
118 | );\r | |
119 | \r | |
120 | /**\r | |
121 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and\r | |
122 | saves the value in the S3 script to be replayed on S3 resume.\r | |
123 | \r | |
124 | Reads the 8-bit PCI configuration register specified by Address,\r | |
125 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
126 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
127 | The value written to the PCI configuration register is returned.\r | |
128 | This function must guarantee that all PCI read and write operations are serialized.\r | |
129 | If any reserved bits in Address are set, then ASSERT().\r | |
130 | \r | |
131 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
132 | @param AndData The value to AND with the PCI configuration register.\r | |
133 | \r | |
134 | @return The value written to the PCI configuration register.\r | |
135 | \r | |
136 | **/\r | |
137 | UINT8\r | |
138 | EFIAPI\r | |
139 | S3PciSegmentAnd8 (\r | |
140 | IN UINT64 Address,\r | |
141 | IN UINT8 AndData\r | |
142 | );\r | |
143 | \r | |
144 | /**\r | |
145 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r | |
146 | followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to\r | |
147 | be replayed on S3 resume.\r | |
148 | \r | |
149 | Reads the 8-bit PCI configuration register specified by Address,\r | |
150 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
151 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
152 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
153 | The value written to the PCI configuration register is returned.\r | |
154 | This function must guarantee that all PCI read and write operations are serialized.\r | |
155 | \r | |
156 | If any reserved bits in Address are set, then ASSERT().\r | |
157 | \r | |
158 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
159 | @param AndData The value to AND with the PCI configuration register.\r | |
160 | @param OrData The value to OR with the PCI configuration register.\r | |
161 | \r | |
162 | @return The value written to the PCI configuration register.\r | |
163 | \r | |
164 | **/\r | |
165 | UINT8\r | |
166 | EFIAPI\r | |
167 | S3PciSegmentAndThenOr8 (\r | |
168 | IN UINT64 Address,\r | |
169 | IN UINT8 AndData,\r | |
170 | IN UINT8 OrData\r | |
171 | );\r | |
172 | \r | |
173 | /**\r | |
174 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
175 | S3 script to be replayed on S3 resume.\r | |
176 | \r | |
177 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
178 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
179 | returned.\r | |
180 | \r | |
181 | If any reserved bits in Address are set, then ASSERT().\r | |
182 | If StartBit is greater than 7, then ASSERT().\r | |
183 | If EndBit is greater than 7, then ASSERT().\r | |
184 | If EndBit is less than StartBit, then ASSERT().\r | |
185 | \r | |
186 | @param Address PCI configuration register to read.\r | |
187 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
188 | Range 0..7.\r | |
189 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
190 | Range 0..7.\r | |
191 | \r | |
192 | @return The value of the bit field read from the PCI configuration register.\r | |
193 | \r | |
194 | **/\r | |
195 | UINT8\r | |
196 | EFIAPI\r | |
197 | S3PciSegmentBitFieldRead8 (\r | |
198 | IN UINT64 Address,\r | |
199 | IN UINTN StartBit,\r | |
200 | IN UINTN EndBit\r | |
201 | );\r | |
202 | \r | |
203 | /**\r | |
204 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
205 | the S3 script to be replayed on S3 resume.\r | |
206 | \r | |
207 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
208 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
209 | destination PCI configuration register are preserved. The new value of the\r | |
210 | 8-bit register is returned.\r | |
211 | \r | |
212 | If any reserved bits in Address are set, then ASSERT().\r | |
213 | If StartBit is greater than 7, then ASSERT().\r | |
214 | If EndBit is greater than 7, then ASSERT().\r | |
215 | If EndBit is less than StartBit, then ASSERT().\r | |
216 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
217 | \r | |
218 | @param Address PCI configuration register to write.\r | |
219 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
220 | Range 0..7.\r | |
221 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
222 | Range 0..7.\r | |
223 | @param Value New value of the bit field.\r | |
224 | \r | |
225 | @return The value written back to the PCI configuration register.\r | |
226 | \r | |
227 | **/\r | |
228 | UINT8\r | |
229 | EFIAPI\r | |
230 | S3PciSegmentBitFieldWrite8 (\r | |
231 | IN UINT64 Address,\r | |
232 | IN UINTN StartBit,\r | |
233 | IN UINTN EndBit,\r | |
234 | IN UINT8 Value\r | |
235 | );\r | |
236 | \r | |
237 | /**\r | |
238 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes\r | |
239 | the result back to the bit field in the 8-bit port, and saves the value in the\r | |
240 | S3 script to be replayed on S3 resume.\r | |
241 | \r | |
242 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
243 | bitwise OR between the read result and the value specified by\r | |
244 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
245 | specified by Address. The value written to the PCI configuration register is\r | |
246 | returned. This function must guarantee that all PCI read and write operations\r | |
247 | are serialized. Extra left bits in OrData are stripped.\r | |
248 | \r | |
249 | If any reserved bits in Address are set, then ASSERT().\r | |
250 | If StartBit is greater than 7, then ASSERT().\r | |
251 | If EndBit is greater than 7, then ASSERT().\r | |
252 | If EndBit is less than StartBit, then ASSERT().\r | |
253 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
254 | \r | |
255 | @param Address PCI configuration register to write.\r | |
256 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
257 | Range 0..7.\r | |
258 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
259 | Range 0..7.\r | |
260 | @param OrData The value to OR with the PCI configuration register.\r | |
261 | \r | |
262 | @return The value written back to the PCI configuration register.\r | |
263 | \r | |
264 | **/\r | |
265 | UINT8\r | |
266 | EFIAPI\r | |
267 | S3PciSegmentBitFieldOr8 (\r | |
268 | IN UINT64 Address,\r | |
269 | IN UINTN StartBit,\r | |
270 | IN UINTN EndBit,\r | |
271 | IN UINT8 OrData\r | |
272 | );\r | |
273 | \r | |
274 | /**\r | |
275 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
276 | AND, writes the result back to the bit field in the 8-bit register, and\r | |
277 | saves the value in the S3 script to be replayed on S3 resume.\r | |
278 | \r | |
279 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
280 | bitwise AND between the read result and the value specified by AndData, and\r | |
281 | writes the result to the 8-bit PCI configuration register specified by\r | |
282 | Address. The value written to the PCI configuration register is returned.\r | |
283 | This function must guarantee that all PCI read and write operations are\r | |
284 | serialized. Extra left bits in AndData are stripped.\r | |
285 | \r | |
286 | If any reserved bits in Address are set, then ASSERT().\r | |
287 | If StartBit is greater than 7, then ASSERT().\r | |
288 | If EndBit is greater than 7, then ASSERT().\r | |
289 | If EndBit is less than StartBit, then ASSERT().\r | |
290 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
291 | \r | |
292 | @param Address PCI configuration register to write.\r | |
293 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
294 | Range 0..7.\r | |
295 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
296 | Range 0..7.\r | |
297 | @param AndData The value to AND with the PCI configuration register.\r | |
298 | \r | |
299 | @return The value written back to the PCI configuration register.\r | |
300 | \r | |
301 | **/\r | |
302 | UINT8\r | |
303 | EFIAPI\r | |
304 | S3PciSegmentBitFieldAnd8 (\r | |
305 | IN UINT64 Address,\r | |
306 | IN UINTN StartBit,\r | |
307 | IN UINTN EndBit,\r | |
308 | IN UINT8 AndData\r | |
309 | );\r | |
310 | \r | |
311 | /**\r | |
312 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
313 | bitwise OR, writes the result back to the bit field in the 8-bit port,\r | |
314 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
315 | \r | |
316 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
317 | bitwise AND followed by a bitwise OR between the read result and\r | |
318 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
319 | configuration register specified by Address. The value written to the PCI\r | |
320 | configuration register is returned. This function must guarantee that all PCI\r | |
321 | read and write operations are serialized. Extra left bits in both AndData and\r | |
322 | OrData are stripped.\r | |
323 | \r | |
324 | If any reserved bits in Address are set, then ASSERT().\r | |
325 | If StartBit is greater than 7, then ASSERT().\r | |
326 | If EndBit is greater than 7, then ASSERT().\r | |
327 | If EndBit is less than StartBit, then ASSERT().\r | |
328 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
329 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
330 | \r | |
331 | @param Address PCI configuration register to write.\r | |
332 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
333 | Range 0..7.\r | |
334 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
335 | Range 0..7.\r | |
336 | @param AndData The value to AND with the PCI configuration register.\r | |
337 | @param OrData The value to OR with the result of the AND operation.\r | |
338 | \r | |
339 | @return The value written back to the PCI configuration register.\r | |
340 | \r | |
341 | **/\r | |
342 | UINT8\r | |
343 | EFIAPI\r | |
344 | S3PciSegmentBitFieldAndThenOr8 (\r | |
345 | IN UINT64 Address,\r | |
346 | IN UINTN StartBit,\r | |
347 | IN UINTN EndBit,\r | |
348 | IN UINT8 AndData,\r | |
349 | IN UINT8 OrData\r | |
350 | );\r | |
351 | \r | |
352 | /**\r | |
353 | Reads a 16-bit PCI configuration register, and saves the value in the S3 script\r | |
354 | to be replayed on S3 resume.\r | |
355 | \r | |
356 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
357 | This function must guarantee that all PCI read and write operations are serialized.\r | |
358 | \r | |
359 | If any reserved bits in Address are set, then ASSERT().\r | |
360 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
361 | \r | |
362 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
363 | \r | |
364 | @return The 16-bit PCI configuration register specified by Address.\r | |
365 | \r | |
366 | **/\r | |
367 | UINT16\r | |
368 | EFIAPI\r | |
369 | S3PciSegmentRead16 (\r | |
370 | IN UINT64 Address\r | |
371 | );\r | |
372 | \r | |
373 | /**\r | |
374 | Writes a 16-bit PCI configuration register, and saves the value in the S3 script to\r | |
375 | be replayed on S3 resume.\r | |
376 | \r | |
377 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r | |
378 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
379 | \r | |
380 | If any reserved bits in Address are set, then ASSERT().\r | |
381 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
382 | \r | |
383 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
384 | @param Value The value to write.\r | |
385 | \r | |
386 | @return The parameter of Value.\r | |
387 | \r | |
388 | **/\r | |
389 | UINT16\r | |
390 | EFIAPI\r | |
391 | S3PciSegmentWrite16 (\r | |
392 | IN UINT64 Address,\r | |
393 | IN UINT16 Value\r | |
394 | );\r | |
395 | \r | |
396 | /**\r | |
397 | Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit\r | |
398 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
399 | \r | |
400 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
401 | bitwise OR between the read result and the value specified by OrData, and\r | |
402 | writes the result to the 16-bit PCI configuration register specified by Address.\r | |
403 | The value written to the PCI configuration register is returned. This function\r | |
404 | must guarantee that all PCI read and write operations are serialized.\r | |
405 | \r | |
406 | If any reserved bits in Address are set, then ASSERT().\r | |
407 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
408 | \r | |
409 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
410 | Register.\r | |
411 | @param OrData The value to OR with the PCI configuration register.\r | |
412 | \r | |
413 | @return The value written back to the PCI configuration register.\r | |
414 | \r | |
415 | **/\r | |
416 | UINT16\r | |
417 | EFIAPI\r | |
418 | S3PciSegmentOr16 (\r | |
419 | IN UINT64 Address,\r | |
420 | IN UINT16 OrData\r | |
421 | );\r | |
422 | \r | |
423 | /**\r | |
424 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and\r | |
425 | saves the value in the S3 script to be replayed on S3 resume.\r | |
426 | \r | |
427 | Reads the 16-bit PCI configuration register specified by Address,\r | |
428 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
429 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
430 | The value written to the PCI configuration register is returned.\r | |
431 | This function must guarantee that all PCI read and write operations are serialized.\r | |
432 | \r | |
433 | If any reserved bits in Address are set, then ASSERT().\r | |
434 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
435 | \r | |
436 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
437 | @param AndData The value to AND with the PCI configuration register.\r | |
438 | \r | |
439 | @return The value written to the PCI configuration register.\r | |
440 | \r | |
441 | **/\r | |
442 | UINT16\r | |
443 | EFIAPI\r | |
444 | S3PciSegmentAnd16 (\r | |
445 | IN UINT64 Address,\r | |
446 | IN UINT16 AndData\r | |
447 | );\r | |
448 | \r | |
449 | /**\r | |
450 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r | |
451 | followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to\r | |
452 | be replayed on S3 resume.\r | |
453 | \r | |
454 | Reads the 16-bit PCI configuration register specified by Address,\r | |
455 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
456 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
457 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
458 | The value written to the PCI configuration register is returned.\r | |
459 | This function must guarantee that all PCI read and write operations are serialized.\r | |
460 | \r | |
461 | If any reserved bits in Address are set, then ASSERT().\r | |
462 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
463 | \r | |
464 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
465 | @param AndData The value to AND with the PCI configuration register.\r | |
466 | @param OrData The value to OR with the PCI configuration register.\r | |
467 | \r | |
468 | @return The value written to the PCI configuration register.\r | |
469 | \r | |
470 | **/\r | |
471 | UINT16\r | |
472 | EFIAPI\r | |
473 | S3PciSegmentAndThenOr16 (\r | |
474 | IN UINT64 Address,\r | |
475 | IN UINT16 AndData,\r | |
476 | IN UINT16 OrData\r | |
477 | );\r | |
478 | \r | |
479 | /**\r | |
480 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
481 | S3 script to be replayed on S3 resume.\r | |
482 | \r | |
483 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
484 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
485 | returned.\r | |
486 | \r | |
487 | If any reserved bits in Address are set, then ASSERT().\r | |
488 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
489 | If StartBit is greater than 15, then ASSERT().\r | |
490 | If EndBit is greater than 15, then ASSERT().\r | |
491 | If EndBit is less than StartBit, then ASSERT().\r | |
492 | \r | |
493 | @param Address PCI configuration register to read.\r | |
494 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
495 | Range 0..15.\r | |
496 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
497 | Range 0..15.\r | |
498 | \r | |
499 | @return The value of the bit field read from the PCI configuration register.\r | |
500 | \r | |
501 | **/\r | |
502 | UINT16\r | |
503 | EFIAPI\r | |
504 | S3PciSegmentBitFieldRead16 (\r | |
505 | IN UINT64 Address,\r | |
506 | IN UINTN StartBit,\r | |
507 | IN UINTN EndBit\r | |
508 | );\r | |
509 | \r | |
510 | /**\r | |
511 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
512 | the S3 script to be replayed on S3 resume.\r | |
513 | \r | |
514 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
515 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
516 | destination PCI configuration register are preserved. The new value of the\r | |
517 | 16-bit register is returned.\r | |
518 | \r | |
519 | If any reserved bits in Address are set, then ASSERT().\r | |
520 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
521 | If StartBit is greater than 15, then ASSERT().\r | |
522 | If EndBit is greater than 15, then ASSERT().\r | |
523 | If EndBit is less than StartBit, then ASSERT().\r | |
524 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
525 | \r | |
526 | @param Address PCI configuration register to write.\r | |
527 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
528 | Range 0..15.\r | |
529 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
530 | Range 0..15.\r | |
531 | @param Value New value of the bit field.\r | |
532 | \r | |
533 | @return The value written back to the PCI configuration register.\r | |
534 | \r | |
535 | **/\r | |
536 | UINT16\r | |
537 | EFIAPI\r | |
538 | S3PciSegmentBitFieldWrite16 (\r | |
539 | IN UINT64 Address,\r | |
540 | IN UINTN StartBit,\r | |
541 | IN UINTN EndBit,\r | |
542 | IN UINT16 Value\r | |
543 | );\r | |
544 | \r | |
545 | /**\r | |
546 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r | |
547 | the result back to the bit field in the 16-bit port, and saves the value in the\r | |
548 | S3 script to be replayed on S3 resume.\r | |
549 | \r | |
550 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
551 | bitwise OR between the read result and the value specified by\r | |
552 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
553 | specified by Address. The value written to the PCI configuration register is\r | |
554 | returned. This function must guarantee that all PCI read and write operations\r | |
555 | are serialized. Extra left bits in OrData are stripped.\r | |
556 | \r | |
557 | If any reserved bits in Address are set, then ASSERT().\r | |
558 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
559 | If StartBit is greater than 15, then ASSERT().\r | |
560 | If EndBit is greater than 15, then ASSERT().\r | |
561 | If EndBit is less than StartBit, then ASSERT().\r | |
562 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
563 | \r | |
564 | @param Address PCI configuration register to write.\r | |
565 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
566 | Range 0..15.\r | |
567 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
568 | Range 0..15.\r | |
569 | @param OrData The value to OR with the PCI configuration register.\r | |
570 | \r | |
571 | @return The value written back to the PCI configuration register.\r | |
572 | \r | |
573 | **/\r | |
574 | UINT16\r | |
575 | EFIAPI\r | |
576 | S3PciSegmentBitFieldOr16 (\r | |
577 | IN UINT64 Address,\r | |
578 | IN UINTN StartBit,\r | |
579 | IN UINTN EndBit,\r | |
580 | IN UINT16 OrData\r | |
581 | );\r | |
582 | \r | |
583 | /**\r | |
584 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
585 | AND, writes the result back to the bit field in the 16-bit register, and\r | |
586 | saves the value in the S3 script to be replayed on S3 resume.\r | |
587 | \r | |
588 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
589 | bitwise AND between the read result and the value specified by AndData, and\r | |
590 | writes the result to the 16-bit PCI configuration register specified by\r | |
591 | Address. The value written to the PCI configuration register is returned.\r | |
592 | This function must guarantee that all PCI read and write operations are\r | |
593 | serialized. Extra left bits in AndData are stripped.\r | |
594 | \r | |
595 | If any reserved bits in Address are set, then ASSERT().\r | |
596 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
597 | If StartBit is greater than 15, then ASSERT().\r | |
598 | If EndBit is greater than 15, then ASSERT().\r | |
599 | If EndBit is less than StartBit, then ASSERT().\r | |
600 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
601 | \r | |
602 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
603 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
604 | Range 0..15.\r | |
605 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
606 | Range 0..15.\r | |
607 | @param AndData The value to AND with the PCI configuration register.\r | |
608 | \r | |
609 | @return The value written back to the PCI configuration register.\r | |
610 | \r | |
611 | **/\r | |
612 | UINT16\r | |
613 | EFIAPI\r | |
614 | S3PciSegmentBitFieldAnd16 (\r | |
615 | IN UINT64 Address,\r | |
616 | IN UINTN StartBit,\r | |
617 | IN UINTN EndBit,\r | |
618 | IN UINT16 AndData\r | |
619 | );\r | |
620 | \r | |
621 | /**\r | |
622 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
623 | bitwise OR, writes the result back to the bit field in the 16-bit port,\r | |
624 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
625 | \r | |
626 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
627 | bitwise AND followed by a bitwise OR between the read result and\r | |
628 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
629 | configuration register specified by Address. The value written to the PCI\r | |
630 | configuration register is returned. This function must guarantee that all PCI\r | |
631 | read and write operations are serialized. Extra left bits in both AndData and\r | |
632 | OrData are stripped.\r | |
633 | \r | |
634 | If any reserved bits in Address are set, then ASSERT().\r | |
635 | If StartBit is greater than 15, then ASSERT().\r | |
636 | If EndBit is greater than 15, then ASSERT().\r | |
637 | If EndBit is less than StartBit, then ASSERT().\r | |
638 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
639 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
640 | \r | |
641 | @param Address PCI configuration register to write.\r | |
642 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
643 | Range 0..15.\r | |
644 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
645 | Range 0..15.\r | |
646 | @param AndData The value to AND with the PCI configuration register.\r | |
647 | @param OrData The value to OR with the result of the AND operation.\r | |
648 | \r | |
649 | @return The value written back to the PCI configuration register.\r | |
650 | \r | |
651 | **/\r | |
652 | UINT16\r | |
653 | EFIAPI\r | |
654 | S3PciSegmentBitFieldAndThenOr16 (\r | |
655 | IN UINT64 Address,\r | |
656 | IN UINTN StartBit,\r | |
657 | IN UINTN EndBit,\r | |
658 | IN UINT16 AndData,\r | |
659 | IN UINT16 OrData\r | |
660 | );\r | |
661 | \r | |
662 | /**\r | |
663 | Reads a 32-bit PCI configuration register, and saves the value in the S3 script\r | |
664 | to be replayed on S3 resume.\r | |
665 | \r | |
666 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
667 | This function must guarantee that all PCI read and write operations are serialized.\r | |
668 | \r | |
669 | If any reserved bits in Address are set, then ASSERT().\r | |
670 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
671 | \r | |
672 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
673 | \r | |
674 | @return The 32-bit PCI configuration register specified by Address.\r | |
675 | \r | |
676 | **/\r | |
677 | UINT32\r | |
678 | EFIAPI\r | |
679 | S3PciSegmentRead32 (\r | |
680 | IN UINT64 Address\r | |
681 | );\r | |
682 | \r | |
683 | /**\r | |
684 | Writes a 32-bit PCI configuration register, and saves the value in the S3 script to\r | |
685 | be replayed on S3 resume.\r | |
686 | \r | |
687 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r | |
688 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
689 | \r | |
690 | If any reserved bits in Address are set, then ASSERT().\r | |
691 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
692 | \r | |
693 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
694 | @param Value The value to write.\r | |
695 | \r | |
696 | @return The parameter of Value.\r | |
697 | \r | |
698 | **/\r | |
699 | UINT32\r | |
700 | EFIAPI\r | |
701 | S3PciSegmentWrite32 (\r | |
702 | IN UINT64 Address,\r | |
703 | IN UINT32 Value\r | |
704 | );\r | |
705 | \r | |
706 | /**\r | |
707 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit\r | |
708 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
709 | \r | |
710 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
711 | bitwise OR between the read result and the value specified by OrData, and\r | |
712 | writes the result to the 32-bit PCI configuration register specified by Address.\r | |
713 | The value written to the PCI configuration register is returned. This function\r | |
714 | must guarantee that all PCI read and write operations are serialized.\r | |
715 | \r | |
716 | If any reserved bits in Address are set, then ASSERT().\r | |
717 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
718 | \r | |
719 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and\r | |
720 | Register.\r | |
721 | @param OrData The value to OR with the PCI configuration register.\r | |
722 | \r | |
723 | @return The value written back to the PCI configuration register.\r | |
724 | \r | |
725 | **/\r | |
726 | UINT32\r | |
727 | EFIAPI\r | |
728 | S3PciSegmentOr32 (\r | |
729 | IN UINT64 Address,\r | |
730 | IN UINT32 OrData\r | |
731 | );\r | |
732 | \r | |
733 | /**\r | |
734 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and\r | |
735 | saves the value in the S3 script to be replayed on S3 resume.\r | |
736 | \r | |
737 | Reads the 32-bit PCI configuration register specified by Address,\r | |
738 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
739 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
740 | The value written to the PCI configuration register is returned.\r | |
741 | This function must guarantee that all PCI read and write operations are serialized.\r | |
742 | \r | |
743 | If any reserved bits in Address are set, then ASSERT().\r | |
744 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
745 | \r | |
746 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
747 | @param AndData The value to AND with the PCI configuration register.\r | |
748 | \r | |
749 | @return The value written to the PCI configuration register.\r | |
750 | \r | |
751 | **/\r | |
752 | UINT32\r | |
753 | EFIAPI\r | |
754 | S3PciSegmentAnd32 (\r | |
755 | IN UINT64 Address,\r | |
756 | IN UINT32 AndData\r | |
757 | );\r | |
758 | \r | |
759 | /**\r | |
760 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r | |
761 | followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to\r | |
762 | be replayed on S3 resume.\r | |
763 | \r | |
764 | Reads the 32-bit PCI configuration register specified by Address,\r | |
765 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
766 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
767 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
768 | The value written to the PCI configuration register is returned.\r | |
769 | This function must guarantee that all PCI read and write operations are serialized.\r | |
770 | \r | |
771 | If any reserved bits in Address are set, then ASSERT().\r | |
772 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
773 | \r | |
774 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
775 | @param AndData The value to AND with the PCI configuration register.\r | |
776 | @param OrData The value to OR with the PCI configuration register.\r | |
777 | \r | |
778 | @return The value written to the PCI configuration register.\r | |
779 | \r | |
780 | **/\r | |
781 | UINT32\r | |
782 | EFIAPI\r | |
783 | S3PciSegmentAndThenOr32 (\r | |
784 | IN UINT64 Address,\r | |
785 | IN UINT32 AndData,\r | |
786 | IN UINT32 OrData\r | |
787 | );\r | |
788 | \r | |
789 | /**\r | |
790 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
791 | S3 script to be replayed on S3 resume.\r | |
792 | \r | |
793 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
794 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
795 | returned.\r | |
796 | \r | |
797 | If any reserved bits in Address are set, then ASSERT().\r | |
798 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
799 | If StartBit is greater than 31, then ASSERT().\r | |
800 | If EndBit is greater than 31, then ASSERT().\r | |
801 | If EndBit is less than StartBit, then ASSERT().\r | |
802 | \r | |
803 | @param Address PCI configuration register to read.\r | |
804 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
805 | Range 0..31.\r | |
806 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
807 | Range 0..31.\r | |
808 | \r | |
809 | @return The value of the bit field read from the PCI configuration register.\r | |
810 | \r | |
811 | **/\r | |
812 | UINT32\r | |
813 | EFIAPI\r | |
814 | S3PciSegmentBitFieldRead32 (\r | |
815 | IN UINT64 Address,\r | |
816 | IN UINTN StartBit,\r | |
817 | IN UINTN EndBit\r | |
818 | );\r | |
819 | \r | |
820 | /**\r | |
821 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
822 | the S3 script to be replayed on S3 resume.\r | |
823 | \r | |
824 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
825 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
826 | destination PCI configuration register are preserved. The new value of the\r | |
827 | 32-bit register is returned.\r | |
828 | \r | |
829 | If any reserved bits in Address are set, then ASSERT().\r | |
830 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
831 | If StartBit is greater than 31, then ASSERT().\r | |
832 | If EndBit is greater than 31, then ASSERT().\r | |
833 | If EndBit is less than StartBit, then ASSERT().\r | |
834 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
835 | \r | |
836 | @param Address PCI configuration register to write.\r | |
837 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
838 | Range 0..31.\r | |
839 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
840 | Range 0..31.\r | |
841 | @param Value New value of the bit field.\r | |
842 | \r | |
843 | @return The value written back to the PCI configuration register.\r | |
844 | \r | |
845 | **/\r | |
846 | UINT32\r | |
847 | EFIAPI\r | |
848 | S3PciSegmentBitFieldWrite32 (\r | |
849 | IN UINT64 Address,\r | |
850 | IN UINTN StartBit,\r | |
851 | IN UINTN EndBit,\r | |
852 | IN UINT32 Value\r | |
853 | );\r | |
854 | \r | |
855 | /**\r | |
856 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes\r | |
857 | the result back to the bit field in the 32-bit port, and saves the value in the\r | |
858 | S3 script to be replayed on S3 resume.\r | |
859 | \r | |
860 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
861 | bitwise OR between the read result and the value specified by\r | |
862 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
863 | specified by Address. The value written to the PCI configuration register is\r | |
864 | returned. This function must guarantee that all PCI read and write operations\r | |
865 | are serialized. Extra left bits in OrData are stripped.\r | |
866 | \r | |
867 | If any reserved bits in Address are set, then ASSERT().\r | |
868 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
869 | If StartBit is greater than 31, then ASSERT().\r | |
870 | If EndBit is greater than 31, then ASSERT().\r | |
871 | If EndBit is less than StartBit, then ASSERT().\r | |
872 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
873 | \r | |
874 | @param Address PCI configuration register to write.\r | |
875 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
876 | Range 0..31.\r | |
877 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
878 | Range 0..31.\r | |
879 | @param OrData The value to OR with the PCI configuration register.\r | |
880 | \r | |
881 | @return The value written back to the PCI configuration register.\r | |
882 | \r | |
883 | **/\r | |
884 | UINT32\r | |
885 | EFIAPI\r | |
886 | S3PciSegmentBitFieldOr32 (\r | |
887 | IN UINT64 Address,\r | |
888 | IN UINTN StartBit,\r | |
889 | IN UINTN EndBit,\r | |
890 | IN UINT32 OrData\r | |
891 | );\r | |
892 | \r | |
893 | /**\r | |
894 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
895 | AND, and writes the result back to the bit field in the 32-bit register, and\r | |
896 | saves the value in the S3 script to be replayed on S3 resume.\r | |
897 | \r | |
898 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
899 | bitwise AND between the read result and the value specified by AndData, and\r | |
900 | writes the result to the 32-bit PCI configuration register specified by\r | |
901 | Address. The value written to the PCI configuration register is returned.\r | |
902 | This function must guarantee that all PCI read and write operations are\r | |
903 | serialized. Extra left bits in AndData are stripped.\r | |
904 | \r | |
905 | If any reserved bits in Address are set, then ASSERT().\r | |
906 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
907 | If StartBit is greater than 31, then ASSERT().\r | |
908 | If EndBit is greater than 31, then ASSERT().\r | |
909 | If EndBit is less than StartBit, then ASSERT().\r | |
910 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
911 | \r | |
912 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
913 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
914 | Range 0..31.\r | |
915 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
916 | Range 0..31.\r | |
917 | @param AndData The value to AND with the PCI configuration register.\r | |
918 | \r | |
919 | @return The value written back to the PCI configuration register.\r | |
920 | \r | |
921 | **/\r | |
922 | UINT32\r | |
923 | EFIAPI\r | |
924 | S3PciSegmentBitFieldAnd32 (\r | |
925 | IN UINT64 Address,\r | |
926 | IN UINTN StartBit,\r | |
927 | IN UINTN EndBit,\r | |
928 | IN UINT32 AndData\r | |
929 | );\r | |
930 | \r | |
931 | /**\r | |
932 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
933 | bitwise OR, writes the result back to the bit field in the 32-bit port,\r | |
934 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
935 | \r | |
936 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
937 | bitwise AND followed by a bitwise OR between the read result and\r | |
938 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
939 | configuration register specified by Address. The value written to the PCI\r | |
940 | configuration register is returned. This function must guarantee that all PCI\r | |
941 | read and write operations are serialized. Extra left bits in both AndData and\r | |
942 | OrData are stripped.\r | |
943 | \r | |
944 | If any reserved bits in Address are set, then ASSERT().\r | |
945 | If StartBit is greater than 31, then ASSERT().\r | |
946 | If EndBit is greater than 31, then ASSERT().\r | |
947 | If EndBit is less than StartBit, then ASSERT().\r | |
948 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
949 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
950 | \r | |
951 | @param Address PCI configuration register to write.\r | |
952 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
953 | Range 0..31.\r | |
954 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
955 | Range 0..31.\r | |
956 | @param AndData The value to AND with the PCI configuration register.\r | |
957 | @param OrData The value to OR with the result of the AND operation.\r | |
958 | \r | |
959 | @return The value written back to the PCI configuration register.\r | |
960 | \r | |
961 | **/\r | |
962 | UINT32\r | |
963 | EFIAPI\r | |
964 | S3PciSegmentBitFieldAndThenOr32 (\r | |
965 | IN UINT64 Address,\r | |
966 | IN UINTN StartBit,\r | |
967 | IN UINTN EndBit,\r | |
968 | IN UINT32 AndData,\r | |
969 | IN UINT32 OrData\r | |
970 | );\r | |
971 | \r | |
972 | /**\r | |
973 | Reads a range of PCI configuration registers into a caller supplied buffer,\r | |
974 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
975 | \r | |
976 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
977 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
978 | configuration registers from a single PCI function to be read. Size is\r | |
979 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
980 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
981 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
982 | end of the range.\r | |
983 | \r | |
984 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
985 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
986 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
987 | \r | |
988 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
989 | Function and Register.\r | |
990 | @param Size Size in bytes of the transfer.\r | |
991 | @param Buffer Pointer to a buffer receiving the data read.\r | |
992 | \r | |
993 | @return Size\r | |
994 | \r | |
995 | **/\r | |
996 | UINTN\r | |
997 | EFIAPI\r | |
998 | S3PciSegmentReadBuffer (\r | |
999 | IN UINT64 StartAddress,\r | |
1000 | IN UINTN Size,\r | |
1001 | OUT VOID *Buffer\r | |
1002 | );\r | |
1003 | \r | |
1004 | /**\r | |
1005 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1006 | configuration space, and saves the value in the S3 script to be replayed on S3\r | |
1007 | resume.\r | |
1008 | \r | |
1009 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1010 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1011 | configuration registers from a single PCI function to be written. Size is\r | |
1012 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1013 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1014 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1015 | and the end of the range.\r | |
1016 | \r | |
1017 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1018 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1019 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1020 | \r | |
1021 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1022 | Function and Register.\r | |
1023 | @param Size Size in bytes of the transfer.\r | |
1024 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1025 | \r | |
1026 | @return The parameter of Size.\r | |
1027 | \r | |
1028 | **/\r | |
1029 | UINTN\r | |
1030 | EFIAPI\r | |
1031 | S3PciSegmentWriteBuffer (\r | |
1032 | IN UINT64 StartAddress,\r | |
1033 | IN UINTN Size,\r | |
1034 | IN VOID *Buffer\r | |
1035 | );\r | |
1036 | \r | |
1037 | #endif\r |