[mirror_edk2.git] / MdePkg / Include / Pi / PiI2c.h

/** @file\r
  Include file matches things in PI.\r
\r
Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials are licensed and made available under \r
the terms and conditions of the BSD License that accompanies this distribution.  \r
The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php.                                            \r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
  @par Revision Reference:\r
  PI Version 1.3\r
\r
**/\r
\r
#ifndef __PI_I2C_H__\r
#define __PI_I2C_H__\r
\r
///\r
/// A 10-bit slave address is or'ed with the following value enabling the\r
/// I2C protocol stack to address the duplicated address space between 0\r
//  and 127 in 10-bit mode.\r
///\r
#define I2C_ADDRESSING_10_BIT     0x80000000\r
\r
///\r
/// I2C controller capabilities\r
///\r
/// The EFI_I2C_CONTROLLER_CAPABILITIES specifies the capabilities of the\r
/// I2C host controller.  The StructureSizeInBytes enables variations of\r
/// this structure to be identified if there is need to extend this\r
/// structure in the future.\r
///\r
typedef struct {\r
  ///\r
  /// Length of this data structure in bytes\r
  ///\r
  UINT32 StructureSizeInBytes;\r
\r
  ///\r
  /// The maximum number of bytes the I2C host controller is able to\r
  /// receive from the I2C bus.\r
  ///\r
  UINT32 MaximumReceiveBytes;\r
\r
  ///\r
  /// The maximum number of bytes the I2C host controller is able to send\r
  /// on the I2C  bus.\r
  ///\r
  UINT32 MaximumTransmitBytes;\r
\r
  ///\r
  /// The maximum number of bytes in the I2C bus transaction.\r
  ///\r
  UINT32 MaximumTotalBytes;\r
} EFI_I2C_CONTROLLER_CAPABILITIES;\r
\r
///\r
/// I2C device description\r
///\r
/// The EFI_I2C_ENUMERATE_PROTOCOL uses the EFI_I2C_DEVICE to describe\r
/// the platform specific details associated with an I2C device.  This\r
/// description is passed to the I2C bus driver during enumeration where\r
/// it is made available to the third party I2C device driver via the\r
/// EFI_I2C_IO_PROTOCOL.\r
///\r
typedef struct {\r
  ///\r
  /// Unique value assigned by the silicon manufacture or the third\r
  /// party I2C driver writer for the I2C part.  This value logically\r
  /// combines both the manufacture name and the I2C part number into\r
  /// a single value specified as a GUID.\r
  ///\r
  CONST EFI_GUID *DeviceGuid;\r
\r
  ///\r
  /// Unique ID of the I2C part within the system\r
  ///\r
  UINT32 DeviceIndex;\r
\r
  ///\r
  /// Hardware revision - ACPI _HRV value.  See the Advanced\r
  /// Configuration and Power Interface Specification, Revision 5.0\r
  /// for the field format and the Plug and play support for I2C\r
  /// web-page for restriction on values.\r
  ///\r
  /// http://www.acpi.info/spec.htm\r
  /// http://msdn.microsoft.com/en-us/library/windows/hardware/jj131711(v=vs.85).aspx\r
  ///\r
  UINT32 HardwareRevision;\r
\r
  ///\r
  /// I2C bus configuration for the I2C device\r
  ///\r
  UINT32 I2cBusConfiguration;\r
\r
  ///\r
  /// Number of slave addresses for the I2C device.\r
  ///\r
  UINT32 SlaveAddressCount;\r
\r
  ///\r
  /// Pointer to the array of slave addresses for the I2C device.\r
  ///\r
  CONST UINT32 *SlaveAddressArray;\r
} EFI_I2C_DEVICE;\r
\r
///\r
/// Define the I2C flags\r
///\r
/// I2C read operation when set\r
#define I2C_FLAG_READ               0x00000001\r
\r
///\r
/// Define the flags for SMBus operation\r
///\r
/// The following flags are also present in only the first I2C operation\r
/// and are ignored when present in other operations.  These flags\r
/// describe a particular SMB transaction as shown in the following table.\r
///\r
\r
/// SMBus operation\r
#define I2C_FLAG_SMBUS_OPERATION    0x00010000\r
\r
/// SMBus block operation\r
///   The flag I2C_FLAG_SMBUS_BLOCK causes the I2C master protocol to update\r
///   the LengthInBytes field of the operation in the request packet with\r
///   the actual number of bytes read or written.  These values are only\r
///   valid when the entire I2C transaction is successful.\r
///   This flag also changes the LengthInBytes meaning to be: A maximum\r
///   of LengthInBytes is to be read from the device.  The first byte\r
///   read contains the number of bytes remaining to be read, plus an\r
///   optional PEC value.\r
#define I2C_FLAG_SMBUS_BLOCK        0x00020000\r
\r
/// SMBus process call operation\r
#define I2C_FLAG_SMBUS_PROCESS_CALL 0x00040000\r
\r
/// SMBus use packet error code (PEC)\r
///   Note that the I2C master protocol may clear the I2C_FLAG_SMBUS_PEC bit\r
///   to indicate that the PEC value was checked by the hardware and is\r
///   not appended to the returned read data.\r
///\r
#define I2C_FLAG_SMBUS_PEC          0x00080000\r
\r
//----------------------------------------------------------------------\r
///\r
/// QuickRead:          OperationCount=1,\r
///                     LengthInBytes=0,   Flags=I2C_FLAG_READ\r
/// QuickWrite:         OperationCount=1,\r
///                     LengthInBytes=0,   Flags=0\r
///\r
///\r
/// ReceiveByte:        OperationCount=1,\r
///                     LengthInBytes=1,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_READ\r
/// ReceiveByte+PEC:    OperationCount=1,\r
///                     LengthInBytes=2,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_READ\r
///                                            | I2C_FLAG_SMBUS_PEC\r
///\r
///\r
/// SendByte:           OperationCount=1,\r
///                     LengthInBytes=1,   Flags=I2C_FLAG_SMBUS_OPERATION\r
/// SendByte+PEC:       OperationCount=1,\r
///                     LengthInBytes=2,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_PEC\r
///\r
///\r
/// ReadDataByte:       OperationCount=2,\r
///                     LengthInBytes=1,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                     LengthInBytes=1,   Flags=I2C_FLAG_READ\r
/// ReadDataByte+PEC:   OperationCount=2,\r
///                     LengthInBytes=1,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_PEC\r
///                     LengthInBytes=2,   Flags=I2C_FLAG_READ\r
///\r
///\r
/// WriteDataByte:      OperationCount=1,\r
///                     LengthInBytes=2,   Flags=I2C_FLAG_SMBUS_OPERATION\r
/// WriteDataByte+PEC:  OperationCount=1,\r
///                     LengthInBytes=3,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_PEC\r
///\r
///\r
/// ReadDataWord:       OperationCount=2,\r
///                     LengthInBytes=1,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                     LengthInBytes=2,   Flags=I2C_FLAG_READ\r
/// ReadDataWord+PEC:   OperationCount=2,\r
///                     LengthInBytes=1,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_PEC\r
///                     LengthInBytes=3,   Flags=I2C_FLAG_READ\r
///\r
///\r
/// WriteDataWord:      OperationCount=1,\r
///                     LengthInBytes=3,   Flags=I2C_FLAG_SMBUS_OPERATION\r
/// WriteDataWord+PEC:  OperationCount=1,\r
///                     LengthInBytes=4,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_PEC\r
///\r
///\r
/// ReadBlock:          OperationCount=2,\r
///                     LengthInBytes=1,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_BLOCK\r
///                     LengthInBytes=33,  Flags=I2C_FLAG_READ\r
/// ReadBlock+PEC:      OperationCount=2,\r
///                     LengthInBytes=1,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_BLOCK\r
///                                            | I2C_FLAG_SMBUS_PEC\r
///                     LengthInBytes=34,  Flags=I2C_FLAG_READ\r
///\r
///\r
/// WriteBlock:         OperationCount=1,\r
///                     LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_BLOCK\r
/// WriteBlock+PEC:     OperationCount=1,\r
///                     LengthInBytes=N+3, Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_BLOCK\r
///                                            | I2C_FLAG_SMBUS_PEC\r
///\r
///\r
/// ProcessCall:        OperationCount=2,\r
///                     LengthInBytes=3,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_PROCESS_CALL\r
///                     LengthInBytes=2,   Flags=I2C_FLAG_READ\r
/// ProcessCall+PEC:    OperationCount=2,\r
///                     LengthInBytes=3,   Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_PROCESS_CALL\r
///                                            | I2C_FLAG_SMBUS_PEC\r
///                     LengthInBytes=3,   Flags=I2C_FLAG_READ\r
///\r
///\r
/// BlkProcessCall:     OperationCount=2,\r
///                     LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_PROCESS_CALL\r
///                                            | I2C_FLAG_SMBUS_BLOCK\r
///                     LengthInBytes=33,  Flags=I2C_FLAG_READ\r
/// BlkProcessCall+PEC: OperationCount=2,\r
///                     LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION\r
///                                            | I2C_FLAG_SMBUS_PROCESS_CALL\r
///                                            | I2C_FLAG_SMBUS_BLOCK\r
///                                            | I2C_FLAG_SMBUS_PEC\r
///                     LengthInBytes=34,  Flags=I2C_FLAG_READ\r
///\r
//----------------------------------------------------------------------\r
\r
///\r
/// I2C device operation\r
///\r
/// The EFI_I2C_OPERATION describes a subset of an I2C transaction in which\r
/// the I2C controller is either sending or receiving bytes from the bus.\r
/// Some transactions will consist of a single operation while others will\r
/// be two or more.\r
///\r
/// Note: Some I2C controllers do not support read or write ping (address\r
/// only) operation and will return EFI_UNSUPPORTED status when these\r
/// operations are requested.\r
///\r
/// Note: I2C controllers which do not support complex transactions requiring\r
/// multiple repeated start bits return EFI_UNSUPPORTED without processing\r
/// any of the transaction.\r
///\r
typedef struct {\r
  ///\r
  /// Flags to qualify the I2C operation.\r
  ///\r
  UINT32 Flags;\r
\r
  ///\r
  /// Number of bytes to send to or receive from the I2C device.  A ping\r
  /// (address only byte/bytes)  is indicated by setting the LengthInBytes\r
  /// to zero.\r
  ///\r
  UINT32 LengthInBytes;\r
\r
  ///\r
  /// Pointer to a buffer containing the data to send or to receive from\r
  /// the I2C device.  The Buffer must be at least LengthInBytes in size.\r
  ///\r
  UINT8 *Buffer;\r
} EFI_I2C_OPERATION;\r
\r
///\r
/// I2C device request\r
///\r
/// The EFI_I2C_REQUEST_PACKET describes a single I2C transaction.  The\r
/// transaction starts with a start bit followed by the first operation\r
/// in the operation array.  Subsequent operations are separated with\r
/// repeated start bits and the last operation is followed by a stop bit\r
/// which concludes the transaction.  Each operation is described by one\r
/// of the elements in the Operation array.\r
///\r
typedef struct {\r
  ///\r
  /// Number of elements in the operation array\r
  ///\r
  UINTN OperationCount;\r
\r
  ///\r
  /// Description of the I2C operation\r
  ///\r
  EFI_I2C_OPERATION Operation [1];\r
} EFI_I2C_REQUEST_PACKET;\r
\r
#endif  //  __PI_I2C_H__\r
Commit	Line	Data
4006b0b5 EL	1	/** @file\r
	2	Include file matches things in PI.\r
	3	\r
	4	Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
	5	This program and the accompanying materials are licensed and made available under \r
	6	the terms and conditions of the BSD License that accompanies this distribution. \r
	7	The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php. \r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	\r
	13	@par Revision Reference:\r
	14	PI Version 1.3\r
	15	\r
	16	**/\r
	17	\r
	18	#ifndef __PI_I2C_H__\r
	19	#define __PI_I2C_H__\r
	20	\r
	21	///\r
	22	/// A 10-bit slave address is or'ed with the following value enabling the\r
	23	/// I2C protocol stack to address the duplicated address space between 0\r
	24	// and 127 in 10-bit mode.\r
	25	///\r
	26	#define I2C_ADDRESSING_10_BIT 0x80000000\r
	27	\r
	28	///\r
	29	/// I2C controller capabilities\r
	30	///\r
	31	/// The EFI_I2C_CONTROLLER_CAPABILITIES specifies the capabilities of the\r
	32	/// I2C host controller. The StructureSizeInBytes enables variations of\r
	33	/// this structure to be identified if there is need to extend this\r
	34	/// structure in the future.\r
	35	///\r
	36	typedef struct {\r
	37	///\r
	38	/// Length of this data structure in bytes\r
	39	///\r
	40	UINT32 StructureSizeInBytes;\r
	41	\r
	42	///\r
	43	/// The maximum number of bytes the I2C host controller is able to\r
	44	/// receive from the I2C bus.\r
	45	///\r
	46	UINT32 MaximumReceiveBytes;\r
	47	\r
	48	///\r
	49	/// The maximum number of bytes the I2C host controller is able to send\r
	50	/// on the I2C bus.\r
	51	///\r
	52	UINT32 MaximumTransmitBytes;\r
	53	\r
	54	///\r
	55	/// The maximum number of bytes in the I2C bus transaction.\r
	56	///\r
	57	UINT32 MaximumTotalBytes;\r
	58	} EFI_I2C_CONTROLLER_CAPABILITIES;\r
	59	\r
	60	///\r
	61	/// I2C device description\r
	62	///\r
	63	/// The EFI_I2C_ENUMERATE_PROTOCOL uses the EFI_I2C_DEVICE to describe\r
	64	/// the platform specific details associated with an I2C device. This\r
65	/// description is passed to the I2C bus driver during enumeration where\r
66	/// it is made available to the third party I2C device driver via the\r
67	/// EFI_I2C_IO_PROTOCOL.\r
68	///\r
69	typedef struct {\r
70	///\r
71	/// Unique value assigned by the silicon manufacture or the third\r
72	/// party I2C driver writer for the I2C part. This value logically\r
73	/// combines both the manufacture name and the I2C part number into\r
74	/// a single value specified as a GUID.\r
75	///\r
76	CONST EFI_GUID *DeviceGuid;\r
77	\r
78	///\r
79	/// Unique ID of the I2C part within the system\r
80	///\r
81	UINT32 DeviceIndex;\r
82	\r
83	///\r
84	/// Hardware revision - ACPI _HRV value. See the Advanced\r
85	/// Configuration and Power Interface Specification, Revision 5.0\r
86	/// for the field format and the Plug and play support for I2C\r
87	/// web-page for restriction on values.\r
88	///\r
89	/// http://www.acpi.info/spec.htm\r
90	/// http://msdn.microsoft.com/en-us/library/windows/hardware/jj131711(v=vs.85).aspx\r
91	///\r
92	UINT32 HardwareRevision;\r
93	\r
94	///\r
95	/// I2C bus configuration for the I2C device\r
96	///\r
97	UINT32 I2cBusConfiguration;\r
98	\r
99	///\r
100	/// Number of slave addresses for the I2C device.\r
101	///\r
102	UINT32 SlaveAddressCount;\r
103	\r
104	///\r
105	/// Pointer to the array of slave addresses for the I2C device.\r
106	///\r
107	CONST UINT32 *SlaveAddressArray;\r
108	} EFI_I2C_DEVICE;\r
109	\r
110	///\r
111	/// Define the I2C flags\r
112	///\r
113	/// I2C read operation when set\r
114	#define I2C_FLAG_READ 0x00000001\r
115	\r
116	///\r
117	/// Define the flags for SMBus operation\r
118	///\r
119	/// The following flags are also present in only the first I2C operation\r
120	/// and are ignored when present in other operations. These flags\r
121	/// describe a particular SMB transaction as shown in the following table.\r
122	///\r
123	\r
124	/// SMBus operation\r
125	#define I2C_FLAG_SMBUS_OPERATION 0x00010000\r
126	\r
127	/// SMBus block operation\r
128	/// The flag I2C_FLAG_SMBUS_BLOCK causes the I2C master protocol to update\r
129	/// the LengthInBytes field of the operation in the request packet with\r
130	/// the actual number of bytes read or written. These values are only\r
131	/// valid when the entire I2C transaction is successful.\r
132	/// This flag also changes the LengthInBytes meaning to be: A maximum\r
133	/// of LengthInBytes is to be read from the device. The first byte\r
134	/// read contains the number of bytes remaining to be read, plus an\r
135	/// optional PEC value.\r
136	#define I2C_FLAG_SMBUS_BLOCK 0x00020000\r
137	\r
138	/// SMBus process call operation\r
139	#define I2C_FLAG_SMBUS_PROCESS_CALL 0x00040000\r
140	\r
141	/// SMBus use packet error code (PEC)\r
142	/// Note that the I2C master protocol may clear the I2C_FLAG_SMBUS_PEC bit\r
143	/// to indicate that the PEC value was checked by the hardware and is\r
144	/// not appended to the returned read data.\r
145	///\r
146	#define I2C_FLAG_SMBUS_PEC 0x00080000\r
147	\r
148	//----------------------------------------------------------------------\r
149	///\r
150	/// QuickRead: OperationCount=1,\r
151	/// LengthInBytes=0, Flags=I2C_FLAG_READ\r
152	/// QuickWrite: OperationCount=1,\r
153	/// LengthInBytes=0, Flags=0\r
154	///\r
155	///\r
156	/// ReceiveByte: OperationCount=1,\r
157	/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r
158	/// \| I2C_FLAG_READ\r
159	/// ReceiveByte+PEC: OperationCount=1,\r
160	/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION\r
161	/// \| I2C_FLAG_READ\r
162	/// \| I2C_FLAG_SMBUS_PEC\r
163	///\r
164	///\r
165	/// SendByte: OperationCount=1,\r
166	/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r
167	/// SendByte+PEC: OperationCount=1,\r
168	/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION\r
169	/// \| I2C_FLAG_SMBUS_PEC\r
170	///\r
171	///\r
172	/// ReadDataByte: OperationCount=2,\r
173	/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r
174	/// LengthInBytes=1, Flags=I2C_FLAG_READ\r
175	/// ReadDataByte+PEC: OperationCount=2,\r
176	/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r
177	/// \| I2C_FLAG_SMBUS_PEC\r
178	/// LengthInBytes=2, Flags=I2C_FLAG_READ\r
179	///\r
180	///\r
181	/// WriteDataByte: OperationCount=1,\r
182	/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION\r
183	/// WriteDataByte+PEC: OperationCount=1,\r
184	/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION\r
185	/// \| I2C_FLAG_SMBUS_PEC\r
186	///\r
187	///\r
188	/// ReadDataWord: OperationCount=2,\r
189	/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r
190	/// LengthInBytes=2, Flags=I2C_FLAG_READ\r
191	/// ReadDataWord+PEC: OperationCount=2,\r
192	/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r
193	/// \| I2C_FLAG_SMBUS_PEC\r
194	/// LengthInBytes=3, Flags=I2C_FLAG_READ\r
195	///\r
196	///\r
197	/// WriteDataWord: OperationCount=1,\r
198	/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION\r
199	/// WriteDataWord+PEC: OperationCount=1,\r
200	/// LengthInBytes=4, Flags=I2C_FLAG_SMBUS_OPERATION\r
201	/// \| I2C_FLAG_SMBUS_PEC\r
202	///\r
203	///\r
204	/// ReadBlock: OperationCount=2,\r
205	/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r
206	/// \| I2C_FLAG_SMBUS_BLOCK\r
207	/// LengthInBytes=33, Flags=I2C_FLAG_READ\r
208	/// ReadBlock+PEC: OperationCount=2,\r
209	/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION\r
210	/// \| I2C_FLAG_SMBUS_BLOCK\r
211	/// \| I2C_FLAG_SMBUS_PEC\r
212	/// LengthInBytes=34, Flags=I2C_FLAG_READ\r
213	///\r
214	///\r
215	/// WriteBlock: OperationCount=1,\r
216	/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION\r
217	/// \| I2C_FLAG_SMBUS_BLOCK\r
218	/// WriteBlock+PEC: OperationCount=1,\r
219	/// LengthInBytes=N+3, Flags=I2C_FLAG_SMBUS_OPERATION\r
220	/// \| I2C_FLAG_SMBUS_BLOCK\r
221	/// \| I2C_FLAG_SMBUS_PEC\r
222	///\r
223	///\r
224	/// ProcessCall: OperationCount=2,\r
225	/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION\r
226	/// \| I2C_FLAG_SMBUS_PROCESS_CALL\r
227	/// LengthInBytes=2, Flags=I2C_FLAG_READ\r
228	/// ProcessCall+PEC: OperationCount=2,\r
229	/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION\r
230	/// \| I2C_FLAG_SMBUS_PROCESS_CALL\r
231	/// \| I2C_FLAG_SMBUS_PEC\r
232	/// LengthInBytes=3, Flags=I2C_FLAG_READ\r
233	///\r
234	///\r
235	/// BlkProcessCall: OperationCount=2,\r
236	/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION\r
237	/// \| I2C_FLAG_SMBUS_PROCESS_CALL\r
238	/// \| I2C_FLAG_SMBUS_BLOCK\r
239	/// LengthInBytes=33, Flags=I2C_FLAG_READ\r
240	/// BlkProcessCall+PEC: OperationCount=2,\r
241	/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION\r
242	/// \| I2C_FLAG_SMBUS_PROCESS_CALL\r
243	/// \| I2C_FLAG_SMBUS_BLOCK\r
244	/// \| I2C_FLAG_SMBUS_PEC\r
245	/// LengthInBytes=34, Flags=I2C_FLAG_READ\r
246	///\r
247	//----------------------------------------------------------------------\r
248	\r
249	///\r
250	/// I2C device operation\r
251	///\r
252	/// The EFI_I2C_OPERATION describes a subset of an I2C transaction in which\r
253	/// the I2C controller is either sending or receiving bytes from the bus.\r
254	/// Some transactions will consist of a single operation while others will\r
255	/// be two or more.\r
256	///\r
257	/// Note: Some I2C controllers do not support read or write ping (address\r
258	/// only) operation and will return EFI_UNSUPPORTED status when these\r
259	/// operations are requested.\r
260	///\r
261	/// Note: I2C controllers which do not support complex transactions requiring\r
262	/// multiple repeated start bits return EFI_UNSUPPORTED without processing\r
263	/// any of the transaction.\r
264	///\r
265	typedef struct {\r
266	///\r
267	/// Flags to qualify the I2C operation.\r
268	///\r
269	UINT32 Flags;\r
270	\r
271	///\r
272	/// Number of bytes to send to or receive from the I2C device. A ping\r
273	/// (address only byte/bytes) is indicated by setting the LengthInBytes\r
274	/// to zero.\r
275	///\r
276	UINT32 LengthInBytes;\r
277	\r
278	///\r
279	/// Pointer to a buffer containing the data to send or to receive from\r
280	/// the I2C device. The Buffer must be at least LengthInBytes in size.\r
281	///\r
282	UINT8 *Buffer;\r
283	} EFI_I2C_OPERATION;\r
284	\r
285	///\r
286	/// I2C device request\r
287	///\r
288	/// The EFI_I2C_REQUEST_PACKET describes a single I2C transaction. The\r
289	/// transaction starts with a start bit followed by the first operation\r
290	/// in the operation array. Subsequent operations are separated with\r
291	/// repeated start bits and the last operation is followed by a stop bit\r
292	/// which concludes the transaction. Each operation is described by one\r
293	/// of the elements in the Operation array.\r
294	///\r
295	typedef struct {\r
296	///\r
297	/// Number of elements in the operation array\r
298	///\r
299	UINTN OperationCount;\r
300	\r
301	///\r
302	/// Description of the I2C operation\r
303	///\r
304	EFI_I2C_OPERATION Operation [1];\r
305	} EFI_I2C_REQUEST_PACKET;\r
306	\r
307	#endif // __PI_I2C_H__\r