Add PPI definitions introduced in PI1.0.
[mirror_edk2.git] / MdePkg / Include / Ppi / PciCfg2.h
CommitLineData
5879b875 1/** @file\r
2 This file declares PciCfg PPI used to access PCI configuration space in PEI\r
3\r
4 Copyright (c) 2006 - 2007, Intel Corporation \r
5 All rights reserved. This program and the accompanying materials \r
6 are licensed and made available under the terms and conditions of the BSD License \r
7 which accompanies this distribution. The full text of the license may be found at \r
8 http://opensource.org/licenses/bsd-license.php \r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12\r
13 Module Name: PciCfg.h\r
14\r
15 @par Revision Reference:\r
16 This PPI is defined in PI\r
17 Version 1.00.\r
18\r
19**/\r
20\r
21#ifndef __PEI_PCI_CFG2_H__\r
22#define __PEI_PCI_CFG2_H__\r
23\r
24\r
25#define EFI_PEI_PCI_CFG2_PPI_GUID \\r
26 { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }\r
27\r
28\r
29typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;\r
30\r
31#define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \\r
32 (((bus) << 24) | \\r
33 ((dev) << 16) | \\r
34 ((func) << 8) | \\r
35 ((reg) < 256 ? (reg) : ((UINT64) (reg) << 32)));\r
36\r
37//\r
38// EFI_PEI_PCI_CFG_PPI_WIDTH\r
39//\r
40typedef enum {\r
41 EfiPeiPciCfgWidthUint8 = 0,\r
42 EfiPeiPciCfgWidthUint16 = 1,\r
43 EfiPeiPciCfgWidthUint32 = 2,\r
44 EfiPeiPciCfgWidthUint64 = 3,\r
45 EfiPeiPciCfgWidthMaximum\r
46} EFI_PEI_PCI_CFG_PPI_WIDTH;\r
47\r
48//\r
49// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS\r
50//\r
51typedef struct {\r
52 UINT8 Register;\r
53 UINT8 Function;\r
54 UINT8 Device;\r
55 UINT8 Bus;\r
56 UINT32 ExtendedRegister;\r
57} EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;\r
58\r
59/**\r
60 Reads from or write to a given location in the PCI configuration space.\r
61\r
62 @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r
63\r
64 @param This Pointer to local data for the interface.\r
65\r
66 @param Width The width of the access. Enumerated in bytes. \r
67 See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r
68\r
69 @param Address The physical address of the access. The format of \r
70 the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r
71\r
72 @param Buffer A pointer to the buffer of data..\r
73\r
74\r
75 @retval EFI_SUCCESS The function completed successfully.\r
76\r
77 @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
78\r
79 @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r
80 time.\r
81\r
82**/\r
83typedef\r
84EFI_STATUS\r
85(EFIAPI *EFI_PEI_PCI_CFG_PPI_IO) (\r
86 IN CONST EFI_PEI_SERVICES **PeiServices,\r
87 IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
88 IN CONST EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
89 IN CONST UINT64 Address,\r
90 IN OUT VOID *Buffer\r
91);\r
92\r
93\r
94/**\r
95 PCI read-modify-write operation.\r
96\r
97 @param PeiServices An indirect pointer to the PEI Services Table \r
98 published by the PEI Foundation.\r
99\r
100 @param This Pointer to local data for the interface.\r
101\r
102 @param Width The width of the access. Enumerated in bytes. Type\r
103 EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().\r
104\r
105 @param Address The physical address of the access.\r
106\r
107 @param SetBits Points to value to bitwise-OR with the read configuration value. \r
108\r
109 The size of the value is determined by Width.\r
110\r
111 @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value. \r
112 The size of the value is determined by Width.\r
113\r
114\r
115 @retval EFI_SUCCESS The function completed successfully.\r
116\r
117 @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
118\r
119 @retval EFI_DEVICE_NOT_READY The device is not capable of supporting \r
120 the operation at this time.\r
121\r
122**/\r
123typedef\r
124EFI_STATUS\r
125(EFIAPI *EFI_PEI_PCI_CFG_PPI_RW) (\r
126 IN CONST EFI_PEI_SERVICES **PeiServices,\r
127 IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
128 IN CONST EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
129 IN CONST UINT64 Address,\r
130 IN CONST VOID *SetBits,\r
131 IN CONST VOID *ClearBits\r
132);\r
133\r
134/**\r
135 @par Ppi Description:\r
136 The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI \r
137 controllers behind a PCI root bridge controller.\r
138\r
139 @param Read PCI read services. See the Read() function description.\r
140\r
141 @param Write PCI write services. See the Write() function description.\r
142\r
143 @param Modify PCI read-modify-write services. See the Modify() function description.\r
144\r
145 @param Segment The PCI bus segment which the specified functions will access.\r
146\r
147**/\r
148struct _EFI_PEI_PCI_CFG2_PPI {\r
149 EFI_PEI_PCI_CFG_PPI_IO Read;\r
150 EFI_PEI_PCI_CFG_PPI_IO Write;\r
151 EFI_PEI_PCI_CFG_PPI_RW Modify;\r
152 UINT16 Segment;\r
153};\r
154\r
155\r
156extern EFI_GUID gEfiPciCfg2PpiGuid;\r
157\r
158#endif\r