Formalize comments for Protocols and PPIs.

[mirror_edk2.git] / MdePkg / Include / Ppi / SecPlatformInformation.h

/** @file\r
  This file declares Sec Platform Information PPI.\r
\r
  This service is the primary handoff state into the PEI Foundation. \r
  The Security (SEC) component creates the early, transitory memory \r
  environment and also encapsulates knowledge of at least the \r
  location of the Boot Firmware Volume (BFV).\r
\r
  Copyright (c) 2006 - 2008, Intel Corporation                                                         \r
  All rights reserved. This program and the accompanying materials                          \r
  are licensed and made available under the terms and conditions of the BSD License         \r
  which accompanies this distribution.  The full text of the license may be found at        \r
  http://opensource.org/licenses/bsd-license.php                                            \r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
  @par Revision Reference:\r
  This PPI is defined in PI.\r
  Version 1.00.\r
\r
**/\r
\r
#ifndef __SEC_PLATFORM_INFORMATION_PPI_H__\r
#define __SEC_PLATFORM_INFORMATION_PPI_H__\r
\r
#define EFI_SEC_PLATFORM_INFORMATION_GUID \\r
  { \\r
    0x6f8c2b35, 0xfef4, 0x448d, {0x82, 0x56, 0xe1, 0x1b, 0x19, 0xd6, 0x10, 0x77 } \\r
  }\r
\r
typedef struct _EFI_SEC_PLATFORM_INFORMATION_PPI EFI_SEC_PLATFORM_INFORMATION_PPI;\r
\r
\r
///\r
/// EFI_HEALTH_FLAGS\r
/// Contains information generated by microcode, hardware, and/or the Itanium\r
/// processor PAL code about the state of the processor upon reset.\r
///\r
typedef union {\r
  struct {\r
    ///\r
    /// A 2-bit field indicating self-test state after reset.\r
    ///\r
    UINT32   Status                   : 2;\r
    ///\r
    /// A 1-bit field indicating whether testing has occurred.\r
    /// If this field is zero, the processor has not been tested,\r
    /// and no further fields in the self-test State parameter are valid.\r
    ///\r
    UINT32   Tested                   : 1;\r
    ///\r
    /// Reserved 13 bits.\r
    ///\r
    UINT32   Reserved1                :13;\r
    ///\r
    /// A 1-bit field. If set to 1, indicates that virtual\r
    /// memory features are not available.\r
    ///\r
    UINT32   VirtualMemoryUnavailable : 1;\r
    ///\r
    /// A 1-bit field. If set to 1, indicates that IA-32 execution\r
    /// is not available.\r
    ///\r
    UINT32   Ia32ExecutionUnavailable : 1;\r
    ///\r
    /// A 1-bit field. If set to 1, indicates that the floating\r
    /// point unit is not available.\r
    ///\r
    UINT32   FloatingPointUnavailable : 1;\r
    ///\r
    /// A 1-bit field. If set to 1, indicates miscellaneous\r
    /// functional failure other than vm, ia, or fp.\r
    /// The test status field provides additional information on\r
    /// test failures when the State field returns a value of\r
    /// performance restricted or functionally restricted.\r
    /// The value returned is implementation dependent.\r
    ///\r
    UINT32   MiscFeaturesUnavailable  : 1;\r
    ///\r
    /// Reserved 12 bits.\r
    ///\r
    UINT32   Reserved2                :12;\r
  } Bits;\r
  UINT32     Uint32;\r
} EFI_HEALTH_FLAGS;\r
\r
#define NORMAL_BOOT_CALL    0x0\r
#define RECOVERY_CHECK_CALL 0x3\r
\r
typedef struct {\r
  UINT8 BootPhase;\r
  UINT8 FWStatus;\r
  UINT16 Reserved1;\r
  UINT32 Reserved2;\r
\r
  UINT16 ProcId;\r
  UINT16 Reserved3;\r
  UINT8  IdMask;\r
  UINT8  EidMask;\r
  UINT16 Reserved4;\r
\r
  UINT64 PalCallAddress;\r
  UINT64 PalSpecialAddress;\r
  UINT64 SelfTestStatus;\r
  UINT64 SelfTestControl;\r
  UINT64 MemoryBufferRequired;\r
\r
} IPF_HANDOFF_STATUS;\r
\r
///\r
/// EFI_SEC_PLATFORM_INFORMATION_RECORD\r
///\r
typedef struct {\r
  ///\r
  /// Contains information generated by microcode, hardware,\r
  /// and/or the Itanium processor PAL code about the state\r
  /// of the processor upon reset.\r
  ///\r
  EFI_HEALTH_FLAGS HealthFlags;\r
} EFI_SEC_PLATFORM_INFORMATION_RECORD;\r
\r
\r
\r
/**\r
  This interface conveys state information out of the Security (SEC) phase into PEI.\r
\r
  This service is published by the SEC phase. The SEC phase handoff has an optional\r
  EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the\r
  PEI Foundation. As such, if the platform supports the built-in self test (BIST) on IA-32 Intel\r
  architecture or the PAL-A handoff state for Itanium architecture, this information is encapsulated\r
  into the data structure abstracted by this service. This information is collected for the boot-strap\r
  processor (BSP) on IA-32, and for Itanium architecture, it is available on all processors that execute\r
  the PEI Foundation.\r
\r
  @param  PeiServices               Pointer to the PEI Services Table.\r
  @param  StructureSize             Pointer to the variable describing size of the input buffer.\r
  @param  PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.\r
\r
  @retval EFI_SUCCESS               The data was successfully returned.\r
  @retval EFI_BUFFER_TOO_SMALL      The buffer was too small.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SEC_PLATFORM_INFORMATION)(\r
  IN CONST  EFI_PEI_SERVICES                    **PeiServices,\r
  IN OUT    UINT64                              *StructureSize,\r
  OUT       EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord\r
);\r
\r
\r
///\r
/// This service abstracts platform-specific information. It is necessary \r
/// to convey this information to the PEI Foundation so that it can \r
/// discover where to begin dispatching PEIMs.\r
///\r
struct _EFI_SEC_PLATFORM_INFORMATION_PPI {\r
  EFI_SEC_PLATFORM_INFORMATION  PlatformInformation;\r
};\r
\r
\r
extern EFI_GUID gEfiSecPlatformInformationPpiGuid;\r
\r
#endif\r