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[mirror_edk2.git] / MdePkg / Include / Protocol / DebugSupport.h
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d1f95000 1/** @file\r
b4319afb 2 DebugSupport protocol and supporting definitions as defined in the UEFI2.4\r
d1f95000 3 specification.\r
4\r
5 The DebugSupport protocol is used by source level debuggers to abstract the\r
6 processor and handle context save and restore operations.\r
7\r
9095d37b 8Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
b4319afb 9Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
d3abb40d 10Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
b4319afb 11\r
9344f092 12SPDX-License-Identifier: BSD-2-Clause-Patent\r
d1f95000 13\r
d1f95000 14**/\r
15\r
16#ifndef __DEBUG_SUPPORT_H__\r
17#define __DEBUG_SUPPORT_H__\r
18\r
19#include <IndustryStandard/PeImage.h>\r
20\r
21typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r
22\r
99e8ed21 23///\r
af2dc6a7 24/// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}.\r
99e8ed21 25///\r
d1f95000 26#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r
27 { \\r
28 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \\r
29 }\r
30\r
99e8ed21 31///\r
9319d2c2
LG		 32/// Processor exception to be hooked.\r
33/// All exception types for IA32, X64, Itanium and EBC processors are defined.\r
99e8ed21 34///\r
2f88bd3a 35typedef INTN EFI_EXCEPTION_TYPE;\r
d1f95000 36\r
9319d2c2 37///\r
af2dc6a7 38/// IA-32 processor exception types.\r
9319d2c2 39///\r
2f88bd3a
MK		 40#define EXCEPT_IA32_DIVIDE_ERROR 0\r
41#define EXCEPT_IA32_DEBUG 1\r
42#define EXCEPT_IA32_NMI 2\r
43#define EXCEPT_IA32_BREAKPOINT 3\r
44#define EXCEPT_IA32_OVERFLOW 4\r
45#define EXCEPT_IA32_BOUND 5\r
46#define EXCEPT_IA32_INVALID_OPCODE 6\r
47#define EXCEPT_IA32_DOUBLE_FAULT 8\r
48#define EXCEPT_IA32_INVALID_TSS 10\r
49#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
50#define EXCEPT_IA32_STACK_FAULT 12\r
51#define EXCEPT_IA32_GP_FAULT 13\r
52#define EXCEPT_IA32_PAGE_FAULT 14\r
53#define EXCEPT_IA32_FP_ERROR 16\r
54#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
55#define EXCEPT_IA32_MACHINE_CHECK 18\r
56#define EXCEPT_IA32_SIMD 19\r
d1f95000 57\r
8b6c989b 58///\r
af2dc6a7 59/// FXSAVE_STATE.\r
60/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
8b6c989b 61///\r
d1f95000 62typedef struct {\r
2f88bd3a
MK		 63 UINT16 Fcw;\r
64 UINT16 Fsw;\r
65 UINT16 Ftw;\r
66 UINT16 Opcode;\r
67 UINT32 Eip;\r
68 UINT16 Cs;\r
69 UINT16 Reserved1;\r
70 UINT32 DataOffset;\r
71 UINT16 Ds;\r
72 UINT8 Reserved2[10];\r
73 UINT8 St0Mm0[10], Reserved3[6];\r
74 UINT8 St1Mm1[10], Reserved4[6];\r
75 UINT8 St2Mm2[10], Reserved5[6];\r
76 UINT8 St3Mm3[10], Reserved6[6];\r
77 UINT8 St4Mm4[10], Reserved7[6];\r
78 UINT8 St5Mm5[10], Reserved8[6];\r
79 UINT8 St6Mm6[10], Reserved9[6];\r
80 UINT8 St7Mm7[10], Reserved10[6];\r
81 UINT8 Xmm0[16];\r
82 UINT8 Xmm1[16];\r
83 UINT8 Xmm2[16];\r
84 UINT8 Xmm3[16];\r
85 UINT8 Xmm4[16];\r
86 UINT8 Xmm5[16];\r
87 UINT8 Xmm6[16];\r
88 UINT8 Xmm7[16];\r
89 UINT8 Reserved11[14 * 16];\r
d1f95000 90} EFI_FX_SAVE_STATE_IA32;\r
d1f95000 91\r
9319d2c2 92///\r
af2dc6a7 93/// IA-32 processor context definition.\r
9319d2c2 94///\r
d1f95000 95typedef struct {\r
2f88bd3a
MK		 96 UINT32 ExceptionData;\r
97 EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
98 UINT32 Dr0;\r
99 UINT32 Dr1;\r
100 UINT32 Dr2;\r
101 UINT32 Dr3;\r
102 UINT32 Dr6;\r
103 UINT32 Dr7;\r
104 UINT32 Cr0;\r
105 UINT32 Cr1; /* Reserved */\r
106 UINT32 Cr2;\r
107 UINT32 Cr3;\r
108 UINT32 Cr4;\r
109 UINT32 Eflags;\r
110 UINT32 Ldtr;\r
111 UINT32 Tr;\r
112 UINT32 Gdtr[2];\r
113 UINT32 Idtr[2];\r
114 UINT32 Eip;\r
115 UINT32 Gs;\r
116 UINT32 Fs;\r
117 UINT32 Es;\r
118 UINT32 Ds;\r
119 UINT32 Cs;\r
120 UINT32 Ss;\r
121 UINT32 Edi;\r
122 UINT32 Esi;\r
123 UINT32 Ebp;\r
124 UINT32 Esp;\r
125 UINT32 Ebx;\r
126 UINT32 Edx;\r
127 UINT32 Ecx;\r
128 UINT32 Eax;\r
d1f95000 129} EFI_SYSTEM_CONTEXT_IA32;\r
130\r
9319d2c2 131///\r
af2dc6a7 132/// x64 processor exception types.\r
9319d2c2 133///\r
2f88bd3a
MK		 134#define EXCEPT_X64_DIVIDE_ERROR 0\r
135#define EXCEPT_X64_DEBUG 1\r
136#define EXCEPT_X64_NMI 2\r
137#define EXCEPT_X64_BREAKPOINT 3\r
138#define EXCEPT_X64_OVERFLOW 4\r
139#define EXCEPT_X64_BOUND 5\r
140#define EXCEPT_X64_INVALID_OPCODE 6\r
141#define EXCEPT_X64_DOUBLE_FAULT 8\r
142#define EXCEPT_X64_INVALID_TSS 10\r
143#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
144#define EXCEPT_X64_STACK_FAULT 12\r
145#define EXCEPT_X64_GP_FAULT 13\r
146#define EXCEPT_X64_PAGE_FAULT 14\r
147#define EXCEPT_X64_FP_ERROR 16\r
148#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
149#define EXCEPT_X64_MACHINE_CHECK 18\r
150#define EXCEPT_X64_SIMD 19\r
d1f95000 151\r
8b6c989b 152///\r
af2dc6a7 153/// FXSAVE_STATE.\r
154/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
8b6c989b 155///\r
d1f95000 156typedef struct {\r
2f88bd3a
MK		 157 UINT16 Fcw;\r
158 UINT16 Fsw;\r
159 UINT16 Ftw;\r
160 UINT16 Opcode;\r
161 UINT64 Rip;\r
162 UINT64 DataOffset;\r
163 UINT8 Reserved1[8];\r
164 UINT8 St0Mm0[10], Reserved2[6];\r
165 UINT8 St1Mm1[10], Reserved3[6];\r
166 UINT8 St2Mm2[10], Reserved4[6];\r
167 UINT8 St3Mm3[10], Reserved5[6];\r
168 UINT8 St4Mm4[10], Reserved6[6];\r
169 UINT8 St5Mm5[10], Reserved7[6];\r
170 UINT8 St6Mm6[10], Reserved8[6];\r
171 UINT8 St7Mm7[10], Reserved9[6];\r
172 UINT8 Xmm0[16];\r
173 UINT8 Xmm1[16];\r
174 UINT8 Xmm2[16];\r
175 UINT8 Xmm3[16];\r
176 UINT8 Xmm4[16];\r
177 UINT8 Xmm5[16];\r
178 UINT8 Xmm6[16];\r
179 UINT8 Xmm7[16];\r
d1f95000 180 //\r
9095d37b 181 // NOTE: UEFI 2.0 spec definition as follows.\r
d1f95000 182 //\r
2f88bd3a 183 UINT8 Reserved11[14 * 16];\r
d1f95000 184} EFI_FX_SAVE_STATE_X64;\r
185\r
9319d2c2 186///\r
af2dc6a7 187/// x64 processor context definition.\r
9319d2c2 188///\r
d1f95000 189typedef struct {\r
2f88bd3a
MK		 190 UINT64 ExceptionData;\r
191 EFI_FX_SAVE_STATE_X64 FxSaveState;\r
192 UINT64 Dr0;\r
193 UINT64 Dr1;\r
194 UINT64 Dr2;\r
195 UINT64 Dr3;\r
196 UINT64 Dr6;\r
197 UINT64 Dr7;\r
198 UINT64 Cr0;\r
199 UINT64 Cr1; /* Reserved */\r
200 UINT64 Cr2;\r
201 UINT64 Cr3;\r
202 UINT64 Cr4;\r
203 UINT64 Cr8;\r
204 UINT64 Rflags;\r
205 UINT64 Ldtr;\r
206 UINT64 Tr;\r
207 UINT64 Gdtr[2];\r
208 UINT64 Idtr[2];\r
209 UINT64 Rip;\r
210 UINT64 Gs;\r
211 UINT64 Fs;\r
212 UINT64 Es;\r
213 UINT64 Ds;\r
214 UINT64 Cs;\r
215 UINT64 Ss;\r
216 UINT64 Rdi;\r
217 UINT64 Rsi;\r
218 UINT64 Rbp;\r
219 UINT64 Rsp;\r
220 UINT64 Rbx;\r
221 UINT64 Rdx;\r
222 UINT64 Rcx;\r
223 UINT64 Rax;\r
224 UINT64 R8;\r
225 UINT64 R9;\r
226 UINT64 R10;\r
227 UINT64 R11;\r
228 UINT64 R12;\r
229 UINT64 R13;\r
230 UINT64 R14;\r
231 UINT64 R15;\r
d1f95000 232} EFI_SYSTEM_CONTEXT_X64;\r
233\r
9319d2c2 234///\r
af2dc6a7 235/// Itanium Processor Family Exception types.\r
9319d2c2 236///\r
2f88bd3a
MK		 237#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
238#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
239#define EXCEPT_IPF_DATA_TLB 2\r
240#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r
241#define EXCEPT_IPF_ALT_DATA_TLB 4\r
242#define EXCEPT_IPF_DATA_NESTED_TLB 5\r
243#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
244#define EXCEPT_IPF_DATA_KEY_MISSED 7\r
245#define EXCEPT_IPF_DIRTY_BIT 8\r
246#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
247#define EXCEPT_IPF_DATA_ACCESS_BIT 10\r
248#define EXCEPT_IPF_BREAKPOINT 11\r
249#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r
d1f95000 250//\r
251// 13 - 19 reserved\r
252//\r
253#define EXCEPT_IPF_PAGE_NOT_PRESENT 20\r
254#define EXCEPT_IPF_KEY_PERMISSION 21\r
255#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22\r
256#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23\r
257#define EXCEPT_IPF_GENERAL_EXCEPTION 24\r
258#define EXCEPT_IPF_DISABLED_FP_REGISTER 25\r
259#define EXCEPT_IPF_NAT_CONSUMPTION 26\r
260#define EXCEPT_IPF_SPECULATION 27\r
261//\r
262// 28 reserved\r
263//\r
264#define EXCEPT_IPF_DEBUG 29\r
265#define EXCEPT_IPF_UNALIGNED_REFERENCE 30\r
266#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31\r
267#define EXCEPT_IPF_FP_FAULT 32\r
268#define EXCEPT_IPF_FP_TRAP 33\r
269#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34\r
270#define EXCEPT_IPF_TAKEN_BRANCH 35\r
271#define EXCEPT_IPF_SINGLE_STEP 36\r
272//\r
273// 37 - 44 reserved\r
274//\r
2f88bd3a
MK		 275#define EXCEPT_IPF_IA32_EXCEPTION 45\r
276#define EXCEPT_IPF_IA32_INTERCEPT 46\r
277#define EXCEPT_IPF_IA32_INTERRUPT 47\r
d1f95000 278\r
8b6c989b 279///\r
af2dc6a7 280/// IPF processor context definition.\r
8b6c989b 281///\r
d1f95000 282typedef struct {\r
283 //\r
284 // The first reserved field is necessary to preserve alignment for the correct\r
630b4187 285 // bits in UNAT and to insure F2 is 16 byte aligned.\r
d1f95000 286 //\r
2f88bd3a
MK		 287 UINT64 Reserved;\r
288 UINT64 R1;\r
289 UINT64 R2;\r
290 UINT64 R3;\r
291 UINT64 R4;\r
292 UINT64 R5;\r
293 UINT64 R6;\r
294 UINT64 R7;\r
295 UINT64 R8;\r
296 UINT64 R9;\r
297 UINT64 R10;\r
298 UINT64 R11;\r
299 UINT64 R12;\r
300 UINT64 R13;\r
301 UINT64 R14;\r
302 UINT64 R15;\r
303 UINT64 R16;\r
304 UINT64 R17;\r
305 UINT64 R18;\r
306 UINT64 R19;\r
307 UINT64 R20;\r
308 UINT64 R21;\r
309 UINT64 R22;\r
310 UINT64 R23;\r
311 UINT64 R24;\r
312 UINT64 R25;\r
313 UINT64 R26;\r
314 UINT64 R27;\r
315 UINT64 R28;\r
316 UINT64 R29;\r
317 UINT64 R30;\r
318 UINT64 R31;\r
319\r
320 UINT64 F2[2];\r
321 UINT64 F3[2];\r
322 UINT64 F4[2];\r
323 UINT64 F5[2];\r
324 UINT64 F6[2];\r
325 UINT64 F7[2];\r
326 UINT64 F8[2];\r
327 UINT64 F9[2];\r
328 UINT64 F10[2];\r
329 UINT64 F11[2];\r
330 UINT64 F12[2];\r
331 UINT64 F13[2];\r
332 UINT64 F14[2];\r
333 UINT64 F15[2];\r
334 UINT64 F16[2];\r
335 UINT64 F17[2];\r
336 UINT64 F18[2];\r
337 UINT64 F19[2];\r
338 UINT64 F20[2];\r
339 UINT64 F21[2];\r
340 UINT64 F22[2];\r
341 UINT64 F23[2];\r
342 UINT64 F24[2];\r
343 UINT64 F25[2];\r
344 UINT64 F26[2];\r
345 UINT64 F27[2];\r
346 UINT64 F28[2];\r
347 UINT64 F29[2];\r
348 UINT64 F30[2];\r
349 UINT64 F31[2];\r
350\r
351 UINT64 Pr;\r
352\r
353 UINT64 B0;\r
354 UINT64 B1;\r
355 UINT64 B2;\r
356 UINT64 B3;\r
357 UINT64 B4;\r
358 UINT64 B5;\r
359 UINT64 B6;\r
360 UINT64 B7;\r
d1f95000 361\r
362 //\r
363 // application registers\r
364 //\r
2f88bd3a
MK		 365 UINT64 ArRsc;\r
366 UINT64 ArBsp;\r
367 UINT64 ArBspstore;\r
368 UINT64 ArRnat;\r
d1f95000 369\r
2f88bd3a 370 UINT64 ArFcr;\r
d1f95000 371\r
2f88bd3a
MK		 372 UINT64 ArEflag;\r
373 UINT64 ArCsd;\r
374 UINT64 ArSsd;\r
375 UINT64 ArCflg;\r
376 UINT64 ArFsr;\r
377 UINT64 ArFir;\r
378 UINT64 ArFdr;\r
d1f95000 379\r
2f88bd3a 380 UINT64 ArCcv;\r
d1f95000 381\r
2f88bd3a 382 UINT64 ArUnat;\r
d1f95000 383\r
2f88bd3a 384 UINT64 ArFpsr;\r
d1f95000 385\r
2f88bd3a
MK		 386 UINT64 ArPfs;\r
387 UINT64 ArLc;\r
388 UINT64 ArEc;\r
d1f95000 389\r
390 //\r
391 // control registers\r
392 //\r
2f88bd3a
MK		 393 UINT64 CrDcr;\r
394 UINT64 CrItm;\r
395 UINT64 CrIva;\r
396 UINT64 CrPta;\r
397 UINT64 CrIpsr;\r
398 UINT64 CrIsr;\r
399 UINT64 CrIip;\r
400 UINT64 CrIfa;\r
401 UINT64 CrItir;\r
402 UINT64 CrIipa;\r
403 UINT64 CrIfs;\r
404 UINT64 CrIim;\r
405 UINT64 CrIha;\r
d1f95000 406\r
407 //\r
408 // debug registers\r
409 //\r
2f88bd3a
MK		 410 UINT64 Dbr0;\r
411 UINT64 Dbr1;\r
412 UINT64 Dbr2;\r
413 UINT64 Dbr3;\r
414 UINT64 Dbr4;\r
415 UINT64 Dbr5;\r
416 UINT64 Dbr6;\r
417 UINT64 Dbr7;\r
418\r
419 UINT64 Ibr0;\r
420 UINT64 Ibr1;\r
421 UINT64 Ibr2;\r
422 UINT64 Ibr3;\r
423 UINT64 Ibr4;\r
424 UINT64 Ibr5;\r
425 UINT64 Ibr6;\r
426 UINT64 Ibr7;\r
d1f95000 427\r
428 //\r
429 // virtual registers - nat bits for R1-R31\r
430 //\r
2f88bd3a 431 UINT64 IntNat;\r
d1f95000 432} EFI_SYSTEM_CONTEXT_IPF;\r
433\r
9319d2c2 434///\r
af2dc6a7 435/// EBC processor exception types.\r
9319d2c2 436///\r
2f88bd3a
MK		 437#define EXCEPT_EBC_UNDEFINED 0\r
438#define EXCEPT_EBC_DIVIDE_ERROR 1\r
439#define EXCEPT_EBC_DEBUG 2\r
440#define EXCEPT_EBC_BREAKPOINT 3\r
441#define EXCEPT_EBC_OVERFLOW 4\r
442#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.\r
443#define EXCEPT_EBC_STACK_FAULT 6\r
444#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
445#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.\r
446#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.\r
447#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.\r
99e8ed21 448///\r
449/// For coding convenience, define the maximum valid EBC exception.\r
450///\r
2f88bd3a 451#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
d1f95000 452\r
99e8ed21 453///\r
af2dc6a7 454/// EBC processor context definition.\r
99e8ed21 455///\r
d1f95000 456typedef struct {\r
2f88bd3a
MK		 457 UINT64 R0;\r
458 UINT64 R1;\r
459 UINT64 R2;\r
460 UINT64 R3;\r
461 UINT64 R4;\r
462 UINT64 R5;\r
463 UINT64 R6;\r
464 UINT64 R7;\r
465 UINT64 Flags;\r
466 UINT64 ControlFlags;\r
467 UINT64 Ip;\r
d1f95000 468} EFI_SYSTEM_CONTEXT_EBC;\r
469\r
ebd04fc2 470///\r
af2dc6a7 471/// ARM processor exception types.\r
ebd04fc2 472///\r
2f88bd3a
MK		 473#define EXCEPT_ARM_RESET 0\r
474#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1\r
475#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2\r
476#define EXCEPT_ARM_PREFETCH_ABORT 3\r
477#define EXCEPT_ARM_DATA_ABORT 4\r
478#define EXCEPT_ARM_RESERVED 5\r
479#define EXCEPT_ARM_IRQ 6\r
480#define EXCEPT_ARM_FIQ 7\r
ebd04fc2 481\r
482///\r
483/// For coding convenience, define the maximum valid ARM exception.\r
484///\r
2f88bd3a 485#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ\r
ebd04fc2 486\r
487///\r
af2dc6a7 488/// ARM processor context definition.\r
ebd04fc2 489///\r
490typedef struct {\r
2f88bd3a
MK		 491 UINT32 R0;\r
492 UINT32 R1;\r
493 UINT32 R2;\r
494 UINT32 R3;\r
495 UINT32 R4;\r
496 UINT32 R5;\r
497 UINT32 R6;\r
498 UINT32 R7;\r
499 UINT32 R8;\r
500 UINT32 R9;\r
501 UINT32 R10;\r
502 UINT32 R11;\r
503 UINT32 R12;\r
504 UINT32 SP;\r
505 UINT32 LR;\r
506 UINT32 PC;\r
507 UINT32 CPSR;\r
508 UINT32 DFSR;\r
509 UINT32 DFAR;\r
510 UINT32 IFSR;\r
511 UINT32 IFAR;\r
ebd04fc2 512} EFI_SYSTEM_CONTEXT_ARM;\r
513\r
b4319afb
HL		 514///\r
515/// AARCH64 processor exception types.\r
516///\r
2f88bd3a
MK		 517#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0\r
518#define EXCEPT_AARCH64_IRQ 1\r
519#define EXCEPT_AARCH64_FIQ 2\r
520#define EXCEPT_AARCH64_SERROR 3\r
b4319afb
HL		 521\r
522///\r
523/// For coding convenience, define the maximum valid ARM exception.\r
524///\r
2f88bd3a 525#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR\r
b4319afb
HL		 526\r
527typedef struct {\r
528 // General Purpose Registers\r
2f88bd3a
MK		 529 UINT64 X0;\r
530 UINT64 X1;\r
531 UINT64 X2;\r
532 UINT64 X3;\r
533 UINT64 X4;\r
534 UINT64 X5;\r
535 UINT64 X6;\r
536 UINT64 X7;\r
537 UINT64 X8;\r
538 UINT64 X9;\r
539 UINT64 X10;\r
540 UINT64 X11;\r
541 UINT64 X12;\r
542 UINT64 X13;\r
543 UINT64 X14;\r
544 UINT64 X15;\r
545 UINT64 X16;\r
546 UINT64 X17;\r
547 UINT64 X18;\r
548 UINT64 X19;\r
549 UINT64 X20;\r
550 UINT64 X21;\r
551 UINT64 X22;\r
552 UINT64 X23;\r
553 UINT64 X24;\r
554 UINT64 X25;\r
555 UINT64 X26;\r
556 UINT64 X27;\r
557 UINT64 X28;\r
558 UINT64 FP; // x29 - Frame pointer\r
559 UINT64 LR; // x30 - Link Register\r
560 UINT64 SP; // x31 - Stack pointer\r
b4319afb
HL		 561\r
562 // FP/SIMD Registers\r
2f88bd3a
MK		 563 UINT64 V0[2];\r
564 UINT64 V1[2];\r
565 UINT64 V2[2];\r
566 UINT64 V3[2];\r
567 UINT64 V4[2];\r
568 UINT64 V5[2];\r
569 UINT64 V6[2];\r
570 UINT64 V7[2];\r
571 UINT64 V8[2];\r
572 UINT64 V9[2];\r
573 UINT64 V10[2];\r
574 UINT64 V11[2];\r
575 UINT64 V12[2];\r
576 UINT64 V13[2];\r
577 UINT64 V14[2];\r
578 UINT64 V15[2];\r
579 UINT64 V16[2];\r
580 UINT64 V17[2];\r
581 UINT64 V18[2];\r
582 UINT64 V19[2];\r
583 UINT64 V20[2];\r
584 UINT64 V21[2];\r
585 UINT64 V22[2];\r
586 UINT64 V23[2];\r
587 UINT64 V24[2];\r
588 UINT64 V25[2];\r
589 UINT64 V26[2];\r
590 UINT64 V27[2];\r
591 UINT64 V28[2];\r
592 UINT64 V29[2];\r
593 UINT64 V30[2];\r
594 UINT64 V31[2];\r
595\r
596 UINT64 ELR; // Exception Link Register\r
597 UINT64 SPSR; // Saved Processor Status Register\r
598 UINT64 FPSR; // Floating Point Status Register\r
599 UINT64 ESR; // Exception syndrome register\r
600 UINT64 FAR; // Fault Address Register\r
b4319afb
HL		 601} EFI_SYSTEM_CONTEXT_AARCH64;\r
602\r
d3abb40d
AC		 603///\r
604/// RISC-V processor exception types.\r
605///\r
2f88bd3a
MK		 606#define EXCEPT_RISCV_INST_MISALIGNED 0\r
607#define EXCEPT_RISCV_INST_ACCESS_FAULT 1\r
608#define EXCEPT_RISCV_ILLEGAL_INST 2\r
609#define EXCEPT_RISCV_BREAKPOINT 3\r
610#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4\r
611#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5\r
612#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6\r
613#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7\r
614#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8\r
615#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9\r
616#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10\r
617#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11\r
618\r
619#define EXCEPT_RISCV_SOFTWARE_INT 0x0\r
620#define EXCEPT_RISCV_TIMER_INT 0x1\r
d3abb40d
AC		 621\r
622typedef struct {\r
2f88bd3a
MK		 623 UINT64 X0;\r
624 UINT64 X1;\r
625 UINT64 X2;\r
626 UINT64 X3;\r
627 UINT64 X4;\r
628 UINT64 X5;\r
629 UINT64 X6;\r
630 UINT64 X7;\r
631 UINT64 X8;\r
632 UINT64 X9;\r
633 UINT64 X10;\r
634 UINT64 X11;\r
635 UINT64 X12;\r
636 UINT64 X13;\r
637 UINT64 X14;\r
638 UINT64 X15;\r
639 UINT64 X16;\r
640 UINT64 X17;\r
641 UINT64 X18;\r
642 UINT64 X19;\r
643 UINT64 X20;\r
644 UINT64 X21;\r
645 UINT64 X22;\r
646 UINT64 X23;\r
647 UINT64 X24;\r
648 UINT64 X25;\r
649 UINT64 X26;\r
650 UINT64 X27;\r
651 UINT64 X28;\r
652 UINT64 X29;\r
653 UINT64 X30;\r
654 UINT64 X31;\r
d3abb40d 655} EFI_SYSTEM_CONTEXT_RISCV64;\r
b4319afb 656\r
f0a704f9
CL		 657//\r
658// LoongArch processor exception types.\r
659//\r
660#define EXCEPT_LOONGARCH_INT 0\r
661#define EXCEPT_LOONGARCH_PIL 1\r
662#define EXCEPT_LOONGARCH_PIS 2\r
663#define EXCEPT_LOONGARCH_PIF 3\r
664#define EXCEPT_LOONGARCH_PME 4\r
665#define EXCEPT_LOONGARCH_PNR 5\r
666#define EXCEPT_LOONGARCH_PNX 6\r
667#define EXCEPT_LOONGARCH_PPI 7\r
668#define EXCEPT_LOONGARCH_ADE 8\r
669#define EXCEPT_LOONGARCH_ALE 9\r
670#define EXCEPT_LOONGARCH_BCE 10\r
671#define EXCEPT_LOONGARCH_SYS 11\r
672#define EXCEPT_LOONGARCH_BRK 12\r
673#define EXCEPT_LOONGARCH_INE 13\r
674#define EXCEPT_LOONGARCH_IPE 14\r
675#define EXCEPT_LOONGARCH_FPD 15\r
676#define EXCEPT_LOONGARCH_SXD 16\r
677#define EXCEPT_LOONGARCH_ASXD 17\r
678#define EXCEPT_LOONGARCH_FPE 18\r
679#define EXCEPT_LOONGARCH_TBR 64 // For code only, there is no such type in the ISA spec, the TLB refill is defined for an independent exception.\r
680\r
681//\r
682// LoongArch processor Interrupt types.\r
683//\r
684#define EXCEPT_LOONGARCH_INT_SIP0 0\r
685#define EXCEPT_LOONGARCH_INT_SIP1 1\r
686#define EXCEPT_LOONGARCH_INT_IP0 2\r
687#define EXCEPT_LOONGARCH_INT_IP1 3\r
688#define EXCEPT_LOONGARCH_INT_IP2 4\r
689#define EXCEPT_LOONGARCH_INT_IP3 5\r
690#define EXCEPT_LOONGARCH_INT_IP4 6\r
691#define EXCEPT_LOONGARCH_INT_IP5 7\r
692#define EXCEPT_LOONGARCH_INT_IP6 8\r
693#define EXCEPT_LOONGARCH_INT_IP7 9\r
694#define EXCEPT_LOONGARCH_INT_PMC 10\r
695#define EXCEPT_LOONGARCH_INT_TIMER 11\r
696#define EXCEPT_LOONGARCH_INT_IPI 12\r
697\r
698//\r
699// For coding convenience, define the maximum valid\r
700// LoongArch interrupt.\r
701//\r
702#define MAX_LOONGARCH_INTERRUPT 14\r
703\r
704typedef struct {\r
705 UINT64 R0;\r
706 UINT64 R1;\r
707 UINT64 R2;\r
708 UINT64 R3;\r
709 UINT64 R4;\r
710 UINT64 R5;\r
711 UINT64 R6;\r
712 UINT64 R7;\r
713 UINT64 R8;\r
714 UINT64 R9;\r
715 UINT64 R10;\r
716 UINT64 R11;\r
717 UINT64 R12;\r
718 UINT64 R13;\r
719 UINT64 R14;\r
720 UINT64 R15;\r
721 UINT64 R16;\r
722 UINT64 R17;\r
723 UINT64 R18;\r
724 UINT64 R19;\r
725 UINT64 R20;\r
726 UINT64 R21;\r
727 UINT64 R22;\r
728 UINT64 R23;\r
729 UINT64 R24;\r
730 UINT64 R25;\r
731 UINT64 R26;\r
732 UINT64 R27;\r
733 UINT64 R28;\r
734 UINT64 R29;\r
735 UINT64 R30;\r
736 UINT64 R31;\r
737\r
738 UINT64 CRMD; // CuRrent MoDe information\r
739 UINT64 PRMD; // PRe-exception MoDe information\r
740 UINT64 EUEN; // Extended component Unit ENable\r
741 UINT64 MISC; // MISCellaneous controller\r
742 UINT64 ECFG; // Exception ConFiGuration\r
743 UINT64 ESTAT; // Exception STATus\r
744 UINT64 ERA; // Exception Return Address\r
745 UINT64 BADV; // BAD Virtual address\r
746 UINT64 BADI; // BAD Instruction\r
747} EFI_SYSTEM_CONTEXT_LOONGARCH64;\r
748\r
ebd04fc2 749///\r
af2dc6a7 750/// Universal EFI_SYSTEM_CONTEXT definition.\r
ebd04fc2 751///\r
d1f95000 752typedef union {\r
f0a704f9
CL		 753 EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
754 EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
755 EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
756 EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
757 EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;\r
758 EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;\r
759 EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;\r
760 EFI_SYSTEM_CONTEXT_LOONGARCH64 *SystemContextLoongArch64;\r
d1f95000 761} EFI_SYSTEM_CONTEXT;\r
762\r
763//\r
764// DebugSupport callback function prototypes\r
765//\r
766\r
9095d37b 767/**\r
d1f95000 768 Registers and enables an exception callback function for the specified exception.\r
9095d37b 769\r
af2dc6a7 770 @param ExceptionType Exception types in EBC, IA-32, x64, or IPF.\r
d1f95000 771 @param SystemContext Exception content.\r
9095d37b 772\r
d1f95000 773**/\r
774typedef\r
775VOID\r
6d3ea23f 776(EFIAPI *EFI_EXCEPTION_CALLBACK)(\r
d1f95000 777 IN EFI_EXCEPTION_TYPE ExceptionType,\r
778 IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
779 );\r
780\r
9095d37b 781/**\r
d1f95000 782 Registers and enables the on-target debug agent's periodic entry point.\r
9095d37b 783\r
d1f95000 784 @param SystemContext Exception content.\r
9095d37b 785\r
d1f95000 786**/\r
787typedef\r
788VOID\r
6d3ea23f 789(EFIAPI *EFI_PERIODIC_CALLBACK)(\r
d1f95000 790 IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
791 );\r
792\r
8b6c989b 793///\r
794/// Machine type definition\r
795///\r
d1f95000 796typedef enum {\r
2f88bd3a
MK		 797 IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r
798 IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r
799 IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r
800 IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC\r
801 IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2\r
802 IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64\r
d1f95000 803} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
804\r
d1f95000 805//\r
806// DebugSupport member function definitions\r
807//\r
808\r
9095d37b 809/**\r
d1f95000 810 Returns the maximum value that may be used for the ProcessorIndex parameter in\r
9095d37b
LG		 811 RegisterPeriodicCallback() and RegisterExceptionCallback().\r
812\r
d1f95000 813 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
814 @param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported\r
9095d37b
LG		 815 processor index is returned.\r
816\r
817 @retval EFI_SUCCESS The function completed successfully.\r
818\r
d1f95000 819**/\r
820typedef\r
821EFI_STATUS\r
8b13229b 822(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(\r
d1f95000 823 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
824 OUT UINTN *MaxProcessorIndex\r
825 );\r
826\r
9095d37b 827/**\r
d1f95000 828 Registers a function to be called back periodically in interrupt context.\r
9095d37b 829\r
d1f95000 830 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
831 @param ProcessorIndex Specifies which processor the callback function applies to.\r
832 @param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main\r
833 periodic entry point of the debug agent.\r
9095d37b
LG		 834\r
835 @retval EFI_SUCCESS The function completed successfully.\r
d1f95000 836 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
9095d37b
LG		 837 function was previously registered.\r
838 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback\r
839 function.\r
840\r
d1f95000 841**/\r
842typedef\r
843EFI_STATUS\r
8b13229b 844(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(\r
d1f95000 845 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
846 IN UINTN ProcessorIndex,\r
847 IN EFI_PERIODIC_CALLBACK PeriodicCallback\r
848 );\r
849\r
9095d37b 850/**\r
d1f95000 851 Registers a function to be called when a given processor exception occurs.\r
9095d37b 852\r
d1f95000 853 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
854 @param ProcessorIndex Specifies which processor the callback function applies to.\r
89df7f9d 855 @param ExceptionCallback A pointer to a function of type EXCEPTION_CALLBACK that is called\r
9095d37b
LG		 856 when the processor exception specified by ExceptionType occurs.\r
857 @param ExceptionType Specifies which processor exception to hook.\r
858\r
859 @retval EFI_SUCCESS The function completed successfully.\r
d1f95000 860 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
9095d37b
LG		 861 function was previously registered.\r
862 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback\r
863 function.\r
864\r
d1f95000 865**/\r
866typedef\r
867EFI_STATUS\r
8b13229b 868(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(\r
d1f95000 869 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
870 IN UINTN ProcessorIndex,\r
871 IN EFI_EXCEPTION_CALLBACK ExceptionCallback,\r
872 IN EFI_EXCEPTION_TYPE ExceptionType\r
873 );\r
874\r
9095d37b 875/**\r
d1f95000 876 Invalidates processor instruction cache for a memory range. Subsequent execution in this range\r
9095d37b
LG		 877 causes a fresh memory fetch to retrieve code to be executed.\r
878\r
d1f95000 879 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
880 @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.\r
9095d37b 881 @param Start Specifies the physical base of the memory range to be invalidated.\r
d1f95000 882 @param Length Specifies the minimum number of bytes in the processor's instruction\r
9095d37b
LG		 883 cache to invalidate.\r
884\r
885 @retval EFI_SUCCESS The function completed successfully.\r
886\r
d1f95000 887**/\r
888typedef\r
889EFI_STATUS\r
8b13229b 890(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(\r
d1f95000 891 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
892 IN UINTN ProcessorIndex,\r
893 IN VOID *Start,\r
894 IN UINT64 Length\r
895 );\r
896\r
44717a39 897///\r
9095d37b
LG		 898/// This protocol provides the services to allow the debug agent to register\r
899/// callback functions that are called either periodically or when specific\r
44717a39 900/// processor exceptions occur.\r
901///\r
d1f95000 902struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r
44717a39 903 ///\r
904 /// Declares the processor architecture for this instance of the EFI Debug Support protocol.\r
905 ///\r
2f88bd3a
MK		 906 EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
907 EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
908 EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
909 EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r
910 EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r
d1f95000 911};\r
912\r
2f88bd3a 913extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
d1f95000 914\r
9095d37b 915#endif\r
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