[mirror_edk2.git] / MdePkg / Include / Protocol / DebugSupport.h

/** @file\r
  DebugSupport protocol and supporting definitions as defined in the UEFI2.0\r
  specification.\r
\r
  The DebugSupport protocol is used by source level debuggers to abstract the\r
  processor and handle context save and restore operations.\r
\r
  Copyright (c) 2006 - 2008, Intel Corporation                                                         \r
  All rights reserved. This program and the accompanying materials                          \r
  are licensed and made available under the terms and conditions of the BSD License         \r
  which accompanies this distribution.  The full text of the license may be found at        \r
  http://opensource.org/licenses/bsd-license.php                                            \r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
**/\r
\r
#ifndef __DEBUG_SUPPORT_H__\r
#define __DEBUG_SUPPORT_H__\r
\r
#include <ProcessorBind.h>\r
#include <IndustryStandard/PeImage.h>\r
\r
typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r
\r
//\r
// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}\r
//\r
#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r
  { \\r
    0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \\r
  }\r
\r
//\r
// Debug Support definitions\r
//\r
typedef INTN  EFI_EXCEPTION_TYPE;\r
\r
//\r
//  IA-32 processor exception types\r
//\r
#define EXCEPT_IA32_DIVIDE_ERROR    0\r
#define EXCEPT_IA32_DEBUG           1\r
#define EXCEPT_IA32_NMI             2\r
#define EXCEPT_IA32_BREAKPOINT      3\r
#define EXCEPT_IA32_OVERFLOW        4\r
#define EXCEPT_IA32_BOUND           5\r
#define EXCEPT_IA32_INVALID_OPCODE  6\r
#define EXCEPT_IA32_DOUBLE_FAULT    8\r
#define EXCEPT_IA32_INVALID_TSS     10\r
#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
#define EXCEPT_IA32_STACK_FAULT     12\r
#define EXCEPT_IA32_GP_FAULT        13\r
#define EXCEPT_IA32_PAGE_FAULT      14\r
#define EXCEPT_IA32_FP_ERROR        16\r
#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
#define EXCEPT_IA32_MACHINE_CHECK   18\r
#define EXCEPT_IA32_SIMD            19\r
\r
//\r
//  IA-32 processor context definition\r
//\r
//\r
// FXSAVE_STATE\r
// FP / MMX / XMM registers (see fxrstor instruction definition)\r
//\r
typedef struct {\r
  UINT16  Fcw;\r
  UINT16  Fsw;\r
  UINT16  Ftw;\r
  UINT16  Opcode;\r
  UINT32  Eip;\r
  UINT16  Cs;\r
  UINT16  Reserved1;\r
  UINT32  DataOffset;\r
  UINT16  Ds;\r
  UINT8   Reserved2[10];\r
  UINT8   St0Mm0[10], Reserved3[6];\r
  UINT8   St1Mm1[10], Reserved4[6];\r
  UINT8   St2Mm2[10], Reserved5[6];\r
  UINT8   St3Mm3[10], Reserved6[6];\r
  UINT8   St4Mm4[10], Reserved7[6];\r
  UINT8   St5Mm5[10], Reserved8[6];\r
  UINT8   St6Mm6[10], Reserved9[6];\r
  UINT8   St7Mm7[10], Reserved10[6];\r
  UINT8   Xmm0[16];\r
  UINT8   Xmm1[16];\r
  UINT8   Xmm2[16];\r
  UINT8   Xmm3[16];\r
  UINT8   Xmm4[16];\r
  UINT8   Xmm5[16];\r
  UINT8   Xmm6[16];\r
  UINT8   Xmm7[16];\r
  UINT8   Reserved11[14 * 16];\r
} EFI_FX_SAVE_STATE_IA32;\r
\r
typedef struct {\r
  UINT32                 ExceptionData;\r
  EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
  UINT32                 Dr0;\r
  UINT32                 Dr1;\r
  UINT32                 Dr2;\r
  UINT32                 Dr3;\r
  UINT32                 Dr6;\r
  UINT32                 Dr7;\r
  UINT32                 Cr0;\r
  UINT32                 Cr1;  /* Reserved */\r
  UINT32                 Cr2;\r
  UINT32                 Cr3;\r
  UINT32                 Cr4;\r
  UINT32                 Eflags;\r
  UINT32                 Ldtr;\r
  UINT32                 Tr;\r
  UINT32                 Gdtr[2];\r
  UINT32                 Idtr[2];\r
  UINT32                 Eip;\r
  UINT32                 Gs;\r
  UINT32                 Fs;\r
  UINT32                 Es;\r
  UINT32                 Ds;\r
  UINT32                 Cs;\r
  UINT32                 Ss;\r
  UINT32                 Edi;\r
  UINT32                 Esi;\r
  UINT32                 Ebp;\r
  UINT32                 Esp;\r
  UINT32                 Ebx;\r
  UINT32                 Edx;\r
  UINT32                 Ecx;\r
  UINT32                 Eax;\r
} EFI_SYSTEM_CONTEXT_IA32;\r
\r
//\r
//  X64 processor exception types\r
//\r
#define EXCEPT_X64_DIVIDE_ERROR    0\r
#define EXCEPT_X64_DEBUG           1\r
#define EXCEPT_X64_NMI             2\r
#define EXCEPT_X64_BREAKPOINT      3\r
#define EXCEPT_X64_OVERFLOW        4\r
#define EXCEPT_X64_BOUND           5\r
#define EXCEPT_X64_INVALID_OPCODE  6\r
#define EXCEPT_X64_DOUBLE_FAULT    8\r
#define EXCEPT_X64_INVALID_TSS     10\r
#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
#define EXCEPT_X64_STACK_FAULT     12\r
#define EXCEPT_X64_GP_FAULT        13\r
#define EXCEPT_X64_PAGE_FAULT      14\r
#define EXCEPT_X64_FP_ERROR        16\r
#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
#define EXCEPT_X64_MACHINE_CHECK   18\r
#define EXCEPT_X64_SIMD            19\r
\r
//\r
//  X64 processor context definition\r
//\r
// FXSAVE_STATE\r
// FP / MMX / XMM registers (see fxrstor instruction definition)\r
//\r
typedef struct {\r
  UINT16  Fcw;\r
  UINT16  Fsw;\r
  UINT16  Ftw;\r
  UINT16  Opcode;\r
  UINT64  Rip;\r
  UINT64  DataOffset;\r
  UINT8   Reserved1[8];\r
  UINT8   St0Mm0[10], Reserved2[6];\r
  UINT8   St1Mm1[10], Reserved3[6];\r
  UINT8   St2Mm2[10], Reserved4[6];\r
  UINT8   St3Mm3[10], Reserved5[6];\r
  UINT8   St4Mm4[10], Reserved6[6];\r
  UINT8   St5Mm5[10], Reserved7[6];\r
  UINT8   St6Mm6[10], Reserved8[6];\r
  UINT8   St7Mm7[10], Reserved9[6];\r
  UINT8   Xmm0[16];\r
  UINT8   Xmm1[16];\r
  UINT8   Xmm2[16];\r
  UINT8   Xmm3[16];\r
  UINT8   Xmm4[16];\r
  UINT8   Xmm5[16];\r
  UINT8   Xmm6[16];\r
  UINT8   Xmm7[16];\r
  //\r
  // NOTE: UEFI 2.0 spec definition as follows. \r
  //\r
  UINT8   Reserved11[14 * 16];\r
} EFI_FX_SAVE_STATE_X64;\r
\r
typedef struct {\r
  UINT64                ExceptionData;\r
  EFI_FX_SAVE_STATE_X64 FxSaveState;\r
  UINT64                Dr0;\r
  UINT64                Dr1;\r
  UINT64                Dr2;\r
  UINT64                Dr3;\r
  UINT64                Dr6;\r
  UINT64                Dr7;\r
  UINT64                Cr0;\r
  UINT64                Cr1;  /* Reserved */\r
  UINT64                Cr2;\r
  UINT64                Cr3;\r
  UINT64                Cr4;\r
  UINT64                Cr8;\r
  UINT64                Rflags;\r
  UINT64                Ldtr;\r
  UINT64                Tr;\r
  UINT64                Gdtr[2];\r
  UINT64                Idtr[2];\r
  UINT64                Rip;\r
  UINT64                Gs;\r
  UINT64                Fs;\r
  UINT64                Es;\r
  UINT64                Ds;\r
  UINT64                Cs;\r
  UINT64                Ss;\r
  UINT64                Rdi;\r
  UINT64                Rsi;\r
  UINT64                Rbp;\r
  UINT64                Rsp;\r
  UINT64                Rbx;\r
  UINT64                Rdx;\r
  UINT64                Rcx;\r
  UINT64                Rax;\r
  UINT64                R8;\r
  UINT64                R9;\r
  UINT64                R10;\r
  UINT64                R11;\r
  UINT64                R12;\r
  UINT64                R13;\r
  UINT64                R14;\r
  UINT64                R15;\r
} EFI_SYSTEM_CONTEXT_X64;\r
\r
//\r
//  IPF processor exception types\r
//\r
#define EXCEPT_IPF_VHTP_TRANSLATION       0\r
#define EXCEPT_IPF_INSTRUCTION_TLB        1\r
#define EXCEPT_IPF_DATA_TLB               2\r
#define EXCEPT_IPF_ALT_INSTRUCTION_TLB    3\r
#define EXCEPT_IPF_ALT_DATA_TLB           4\r
#define EXCEPT_IPF_DATA_NESTED_TLB        5\r
#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
#define EXCEPT_IPF_DATA_KEY_MISSED        7\r
#define EXCEPT_IPF_DIRTY_BIT              8\r
#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
#define EXCEPT_IPF_DATA_ACCESS_BIT        10\r
#define EXCEPT_IPF_BREAKPOINT             11\r
#define EXCEPT_IPF_EXTERNAL_INTERRUPT     12\r
//\r
// 13 - 19 reserved\r
//\r
#define EXCEPT_IPF_PAGE_NOT_PRESENT           20\r
#define EXCEPT_IPF_KEY_PERMISSION             21\r
#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS  22\r
#define EXCEPT_IPF_DATA_ACCESS_RIGHTS         23\r
#define EXCEPT_IPF_GENERAL_EXCEPTION          24\r
#define EXCEPT_IPF_DISABLED_FP_REGISTER       25\r
#define EXCEPT_IPF_NAT_CONSUMPTION            26\r
#define EXCEPT_IPF_SPECULATION                27\r
//\r
// 28 reserved\r
//\r
#define EXCEPT_IPF_DEBUG                          29\r
#define EXCEPT_IPF_UNALIGNED_REFERENCE            30\r
#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE     31\r
#define EXCEPT_IPF_FP_FAULT                       32\r
#define EXCEPT_IPF_FP_TRAP                        33\r
#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP  34\r
#define EXCEPT_IPF_TAKEN_BRANCH                   35\r
#define EXCEPT_IPF_SINGLE_STEP                    36\r
//\r
// 37 - 44 reserved\r
//\r
#define EXCEPT_IPF_IA32_EXCEPTION 45\r
#define EXCEPT_IPF_IA32_INTERCEPT 46\r
#define EXCEPT_IPF_IA32_INTERRUPT 47\r
\r
//\r
//  IPF processor context definition\r
//\r
typedef struct {\r
  //\r
  // The first reserved field is necessary to preserve alignment for the correct\r
  // bits in UNAT and to insure F2 is 16 byte aligned..\r
  //\r
  UINT64  Reserved;\r
  UINT64  R1;\r
  UINT64  R2;\r
  UINT64  R3;\r
  UINT64  R4;\r
  UINT64  R5;\r
  UINT64  R6;\r
  UINT64  R7;\r
  UINT64  R8;\r
  UINT64  R9;\r
  UINT64  R10;\r
  UINT64  R11;\r
  UINT64  R12;\r
  UINT64  R13;\r
  UINT64  R14;\r
  UINT64  R15;\r
  UINT64  R16;\r
  UINT64  R17;\r
  UINT64  R18;\r
  UINT64  R19;\r
  UINT64  R20;\r
  UINT64  R21;\r
  UINT64  R22;\r
  UINT64  R23;\r
  UINT64  R24;\r
  UINT64  R25;\r
  UINT64  R26;\r
  UINT64  R27;\r
  UINT64  R28;\r
  UINT64  R29;\r
  UINT64  R30;\r
  UINT64  R31;\r
\r
  UINT64  F2[2];\r
  UINT64  F3[2];\r
  UINT64  F4[2];\r
  UINT64  F5[2];\r
  UINT64  F6[2];\r
  UINT64  F7[2];\r
  UINT64  F8[2];\r
  UINT64  F9[2];\r
  UINT64  F10[2];\r
  UINT64  F11[2];\r
  UINT64  F12[2];\r
  UINT64  F13[2];\r
  UINT64  F14[2];\r
  UINT64  F15[2];\r
  UINT64  F16[2];\r
  UINT64  F17[2];\r
  UINT64  F18[2];\r
  UINT64  F19[2];\r
  UINT64  F20[2];\r
  UINT64  F21[2];\r
  UINT64  F22[2];\r
  UINT64  F23[2];\r
  UINT64  F24[2];\r
  UINT64  F25[2];\r
  UINT64  F26[2];\r
  UINT64  F27[2];\r
  UINT64  F28[2];\r
  UINT64  F29[2];\r
  UINT64  F30[2];\r
  UINT64  F31[2];\r
\r
  UINT64  Pr;\r
\r
  UINT64  B0;\r
  UINT64  B1;\r
  UINT64  B2;\r
  UINT64  B3;\r
  UINT64  B4;\r
  UINT64  B5;\r
  UINT64  B6;\r
  UINT64  B7;\r
\r
  //\r
  // application registers\r
  //\r
  UINT64  ArRsc;\r
  UINT64  ArBsp;\r
  UINT64  ArBspstore;\r
  UINT64  ArRnat;\r
\r
  UINT64  ArFcr;\r
\r
  UINT64  ArEflag;\r
  UINT64  ArCsd;\r
  UINT64  ArSsd;\r
  UINT64  ArCflg;\r
  UINT64  ArFsr;\r
  UINT64  ArFir;\r
  UINT64  ArFdr;\r
\r
  UINT64  ArCcv;\r
\r
  UINT64  ArUnat;\r
\r
  UINT64  ArFpsr;\r
\r
  UINT64  ArPfs;\r
  UINT64  ArLc;\r
  UINT64  ArEc;\r
\r
  //\r
  // control registers\r
  //\r
  UINT64  CrDcr;\r
  UINT64  CrItm;\r
  UINT64  CrIva;\r
  UINT64  CrPta;\r
  UINT64  CrIpsr;\r
  UINT64  CrIsr;\r
  UINT64  CrIip;\r
  UINT64  CrIfa;\r
  UINT64  CrItir;\r
  UINT64  CrIipa;\r
  UINT64  CrIfs;\r
  UINT64  CrIim;\r
  UINT64  CrIha;\r
\r
  //\r
  // debug registers\r
  //\r
  UINT64  Dbr0;\r
  UINT64  Dbr1;\r
  UINT64  Dbr2;\r
  UINT64  Dbr3;\r
  UINT64  Dbr4;\r
  UINT64  Dbr5;\r
  UINT64  Dbr6;\r
  UINT64  Dbr7;\r
\r
  UINT64  Ibr0;\r
  UINT64  Ibr1;\r
  UINT64  Ibr2;\r
  UINT64  Ibr3;\r
  UINT64  Ibr4;\r
  UINT64  Ibr5;\r
  UINT64  Ibr6;\r
  UINT64  Ibr7;\r
\r
  //\r
  // virtual registers - nat bits for R1-R31\r
  //\r
  UINT64  IntNat;\r
\r
} EFI_SYSTEM_CONTEXT_IPF;\r
\r
//\r
//  EBC processor exception types\r
//\r
#define EXCEPT_EBC_UNDEFINED            0\r
#define EXCEPT_EBC_DIVIDE_ERROR         1\r
#define EXCEPT_EBC_DEBUG                2\r
#define EXCEPT_EBC_BREAKPOINT           3\r
#define EXCEPT_EBC_OVERFLOW             4\r
#define EXCEPT_EBC_INVALID_OPCODE       5   // opcode out of range\r
#define EXCEPT_EBC_STACK_FAULT          6\r
#define EXCEPT_EBC_ALIGNMENT_CHECK      7\r
#define EXCEPT_EBC_INSTRUCTION_ENCODING 8   // malformed instruction\r
#define EXCEPT_EBC_BAD_BREAK            9   // BREAK 0 or undefined BREAK\r
#define EXCEPT_EBC_STEP                 10  // to support debug stepping\r
//\r
// For coding convenience, define the maximum valid EBC exception.\r
//\r
#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
\r
//\r
//  EBC processor context definition\r
//\r
typedef struct {\r
  UINT64  R0;\r
  UINT64  R1;\r
  UINT64  R2;\r
  UINT64  R3;\r
  UINT64  R4;\r
  UINT64  R5;\r
  UINT64  R6;\r
  UINT64  R7;\r
  UINT64  Flags;\r
  UINT64  ControlFlags;\r
  UINT64  Ip;\r
} EFI_SYSTEM_CONTEXT_EBC;\r
\r
//\r
// Universal EFI_SYSTEM_CONTEXT definition\r
//\r
typedef union {\r
  EFI_SYSTEM_CONTEXT_EBC  *SystemContextEbc;\r
  EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
  EFI_SYSTEM_CONTEXT_X64  *SystemContextX64;\r
  EFI_SYSTEM_CONTEXT_IPF  *SystemContextIpf;\r
} EFI_SYSTEM_CONTEXT;\r
\r
//\r
// DebugSupport callback function prototypes\r
//\r
\r
/**                                                                 \r
  Registers and enables an exception callback function for the specified exception.\r
    \r
  @param  ExceptionType         Exception types in EBC, IA-32, X64, or IPF\r
  @param  SystemContext         Exception content.\r
                                   \r
**/\r
typedef\r
VOID\r
(*EFI_EXCEPTION_CALLBACK)(\r
  IN     EFI_EXCEPTION_TYPE               ExceptionType,\r
  IN OUT EFI_SYSTEM_CONTEXT               SystemContext\r
  );\r
\r
/**                                                                 \r
  Registers and enables the on-target debug agent's periodic entry point.\r
      \r
  @param  SystemContext         Exception content.\r
                                   \r
**/\r
typedef\r
VOID\r
(*EFI_PERIODIC_CALLBACK)(\r
  IN OUT EFI_SYSTEM_CONTEXT               SystemContext\r
  );\r
\r
//\r
// Machine type definition\r
//\r
typedef enum {\r
  IsaIa32 = IMAGE_FILE_MACHINE_I386, // 0x014C\r
  IsaX64  = IMAGE_FILE_MACHINE_X64,   // 0x8664\r
  IsaIpf  = IMAGE_FILE_MACHINE_IA64,  // 0x0200\r
  IsaEbc  = IMAGE_FILE_MACHINE_EBC    // 0x0EBC\r
} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
\r
\r
//\r
// DebugSupport member function definitions\r
//\r
\r
/**                                                                 \r
  Returns the maximum value that may be used for the ProcessorIndex parameter in\r
  RegisterPeriodicCallback() and RegisterExceptionCallback().                   \r
    \r
  @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
  @param  MaxProcessorIndex     Pointer to a caller-allocated UINTN in which the maximum supported\r
                                processor index is returned.                                      \r
                                \r
  @retval EFI_SUCCESS           The function completed successfully.  \r
                                   \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(\r
  IN EFI_DEBUG_SUPPORT_PROTOCOL          *This,\r
  OUT UINTN                              *MaxProcessorIndex\r
  );\r
\r
/**                                                                 \r
  Registers a function to be called back periodically in interrupt context.\r
    \r
  @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
  @param  ProcessorIndex        Specifies which processor the callback function applies to.\r
  @param  PeriodicCallback      A pointer to a function of type PERIODIC_CALLBACK that is the main\r
                                periodic entry point of the debug agent.\r
                                \r
  @retval EFI_SUCCESS           The function completed successfully.  \r
  @retval EFI_ALREADY_STARTED   Non-NULL PeriodicCallback parameter when a callback\r
                                function was previously registered.                \r
  @retval EFI_OUT_OF_RESOURCES  System has insufficient memory resources to register new callback                               \r
                                function.                                                           \r
                                \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(\r
  IN EFI_DEBUG_SUPPORT_PROTOCOL          *This,\r
  IN UINTN                               ProcessorIndex,\r
  IN EFI_PERIODIC_CALLBACK               PeriodicCallback\r
  );\r
\r
/**                                                                 \r
  Registers a function to be called when a given processor exception occurs.\r
    \r
  @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
  @param  ProcessorIndex        Specifies which processor the callback function applies to.\r
  @param  PeriodicCallback      A pointer to a function of type EXCEPTION_CALLBACK that is called\r
                                when the processor exception specified by ExceptionType occurs.  \r
  @param  ExceptionType         Specifies which processor exception to hook.                       \r
                                \r
  @retval EFI_SUCCESS           The function completed successfully.  \r
  @retval EFI_ALREADY_STARTED   Non-NULL PeriodicCallback parameter when a callback\r
                                function was previously registered.                \r
  @retval EFI_OUT_OF_RESOURCES  System has insufficient memory resources to register new callback                               \r
                                function.                                                           \r
                                \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(\r
  IN EFI_DEBUG_SUPPORT_PROTOCOL          *This,\r
  IN UINTN                               ProcessorIndex,\r
  IN EFI_EXCEPTION_CALLBACK              ExceptionCallback,\r
  IN EFI_EXCEPTION_TYPE                  ExceptionType\r
  );\r
\r
/**                                                                 \r
  Invalidates processor instruction cache for a memory range. Subsequent execution in this range\r
  causes a fresh memory fetch to retrieve code to be executed.                                  \r
    \r
  @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
  @param  ProcessorIndex        Specifies which processor's instruction cache is to be invalidated.\r
  @param  Start                 Specifies the physical base of the memory range to be invalidated.                                \r
  @param  Length                Specifies the minimum number of bytes in the processor's instruction\r
                                cache to invalidate.                                                 \r
                                \r
  @retval EFI_SUCCESS           The function completed successfully.  \r
                                \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(\r
  IN EFI_DEBUG_SUPPORT_PROTOCOL          *This,\r
  IN UINTN                               ProcessorIndex,\r
  IN VOID                                *Start,\r
  IN UINT64                              Length\r
  );\r
\r
//\r
// DebugSupport protocol definition\r
//\r
/**\r
  @par Protocol Description:\r
  This protocol provides the services to allow the debug agent to register \r
  callback functions that are called either periodically or when specific \r
  processor exceptions occur.\r
\r
  @param Isa\r
  Declares the processor architecture for this instance of the EFI\r
  Debug Support protocol.\r
\r
  @param GetMaximumProcessorIndex\r
  Returns the maximum processor index value that may be used.\r
\r
  @param RegisterPeriodicCallback\r
  Registers a callback function that will be invoked periodically\r
  and asynchronously to the execution of EFI.\r
\r
  @param RegisterExceptionCallback\r
  Registers a callback function that will be called each time the\r
  specified processor exception occurs.\r
\r
  @param InvalidateInstructionCache\r
  Invalidate the instruction cache of the processor. This is required\r
  by processor architectures where instruction and data caches are\r
  not coherent when instructions in the code under debug has been\r
  modified by the debug agent.\r
**/\r
struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r
  EFI_INSTRUCTION_SET_ARCHITECTURE  Isa;\r
  EFI_GET_MAXIMUM_PROCESSOR_INDEX   GetMaximumProcessorIndex;\r
  EFI_REGISTER_PERIODIC_CALLBACK    RegisterPeriodicCallback;\r
  EFI_REGISTER_EXCEPTION_CALLBACK   RegisterExceptionCallback;\r
  EFI_INVALIDATE_INSTRUCTION_CACHE  InvalidateInstructionCache;\r
};\r
\r
extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
\r
#endif \r
Commit	Line	Data
d1f95000	1	/** @file\r
	2	DebugSupport protocol and supporting definitions as defined in the UEFI2.0\r
	3	specification.\r
	4	\r
	5	The DebugSupport protocol is used by source level debuggers to abstract the\r
	6	processor and handle context save and restore operations.\r
	7	\r
4ca9b6c4	8	Copyright (c) 2006 - 2008, Intel Corporation \r
d1f95000	9	All rights reserved. This program and the accompanying materials \r
	10	are licensed and made available under the terms and conditions of the BSD License \r
	11	which accompanies this distribution. The full text of the license may be found at \r
	12	http://opensource.org/licenses/bsd-license.php \r
	13	\r
	14	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	15	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	16	\r
d1f95000	17	**/\r
	18	\r
	19	#ifndef __DEBUG_SUPPORT_H__\r
	20	#define __DEBUG_SUPPORT_H__\r
	21	\r
3f748e52	22	#include <ProcessorBind.h>\r
d1f95000	23	#include <IndustryStandard/PeImage.h>\r
	24	\r
	25	typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r
	26	\r
	27	//\r
	28	// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}\r
	29	//\r
	30	#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r
	31	{ \\r
	32	0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \\r
	33	}\r
	34	\r
	35	//\r
	36	// Debug Support definitions\r
	37	//\r
	38	typedef INTN EFI_EXCEPTION_TYPE;\r
	39	\r
	40	//\r
	41	// IA-32 processor exception types\r
	42	//\r
	43	#define EXCEPT_IA32_DIVIDE_ERROR 0\r
	44	#define EXCEPT_IA32_DEBUG 1\r
	45	#define EXCEPT_IA32_NMI 2\r
	46	#define EXCEPT_IA32_BREAKPOINT 3\r
	47	#define EXCEPT_IA32_OVERFLOW 4\r
	48	#define EXCEPT_IA32_BOUND 5\r
	49	#define EXCEPT_IA32_INVALID_OPCODE 6\r
	50	#define EXCEPT_IA32_DOUBLE_FAULT 8\r
	51	#define EXCEPT_IA32_INVALID_TSS 10\r
	52	#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
	53	#define EXCEPT_IA32_STACK_FAULT 12\r
	54	#define EXCEPT_IA32_GP_FAULT 13\r
	55	#define EXCEPT_IA32_PAGE_FAULT 14\r
	56	#define EXCEPT_IA32_FP_ERROR 16\r
	57	#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
	58	#define EXCEPT_IA32_MACHINE_CHECK 18\r
	59	#define EXCEPT_IA32_SIMD 19\r
	60	\r
	61	//\r
	62	// IA-32 processor context definition\r
	63	//\r
	64	//\r
	65	// FXSAVE_STATE\r
	66	// FP / MMX / XMM registers (see fxrstor instruction definition)\r
	67	//\r
	68	typedef struct {\r
	69	UINT16 Fcw;\r
	70	UINT16 Fsw;\r
	71	UINT16 Ftw;\r
	72	UINT16 Opcode;\r
	73	UINT32 Eip;\r
	74	UINT16 Cs;\r
	75	UINT16 Reserved1;\r
	76	UINT32 DataOffset;\r
	77	UINT16 Ds;\r
	78	UINT8 Reserved2[10];\r
d1f95000	79	UINT8 St0Mm0[10], Reserved3[6];\r
	80	UINT8 St1Mm1[10], Reserved4[6];\r
	81	UINT8 St2Mm2[10], Reserved5[6];\r
	82	UINT8 St3Mm3[10], Reserved6[6];\r
	83	UINT8 St4Mm4[10], Reserved7[6];\r
	84	UINT8 St5Mm5[10], Reserved8[6];\r
	85	UINT8 St6Mm6[10], Reserved9[6];\r
	86	UINT8 St7Mm7[10], Reserved10[6];\r
	87	UINT8 Xmm0[16];\r
	88	UINT8 Xmm1[16];\r
	89	UINT8 Xmm2[16];\r
	90	UINT8 Xmm3[16];\r
	91	UINT8 Xmm4[16];\r
	92	UINT8 Xmm5[16];\r
	93	UINT8 Xmm6[16];\r
	94	UINT8 Xmm7[16];\r
	95	UINT8 Reserved11[14 * 16];\r
	96	} EFI_FX_SAVE_STATE_IA32;\r
d1f95000	97	\r
	98	typedef struct {\r
	99	UINT32 ExceptionData;\r
d1f95000	100	EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
d1f95000	101	UINT32 Dr0;\r
	102	UINT32 Dr1;\r
	103	UINT32 Dr2;\r
	104	UINT32 Dr3;\r
	105	UINT32 Dr6;\r
	106	UINT32 Dr7;\r
	107	UINT32 Cr0;\r
	108	UINT32 Cr1; /* Reserved */\r
	109	UINT32 Cr2;\r
	110	UINT32 Cr3;\r
	111	UINT32 Cr4;\r
	112	UINT32 Eflags;\r
	113	UINT32 Ldtr;\r
	114	UINT32 Tr;\r
	115	UINT32 Gdtr[2];\r
	116	UINT32 Idtr[2];\r
	117	UINT32 Eip;\r
	118	UINT32 Gs;\r
	119	UINT32 Fs;\r
	120	UINT32 Es;\r
	121	UINT32 Ds;\r
	122	UINT32 Cs;\r
	123	UINT32 Ss;\r
	124	UINT32 Edi;\r
	125	UINT32 Esi;\r
	126	UINT32 Ebp;\r
	127	UINT32 Esp;\r
	128	UINT32 Ebx;\r
	129	UINT32 Edx;\r
	130	UINT32 Ecx;\r
	131	UINT32 Eax;\r
	132	} EFI_SYSTEM_CONTEXT_IA32;\r
	133	\r
	134	//\r
	135	// X64 processor exception types\r
	136	//\r
	137	#define EXCEPT_X64_DIVIDE_ERROR 0\r
	138	#define EXCEPT_X64_DEBUG 1\r
	139	#define EXCEPT_X64_NMI 2\r
	140	#define EXCEPT_X64_BREAKPOINT 3\r
	141	#define EXCEPT_X64_OVERFLOW 4\r
	142	#define EXCEPT_X64_BOUND 5\r
	143	#define EXCEPT_X64_INVALID_OPCODE 6\r
	144	#define EXCEPT_X64_DOUBLE_FAULT 8\r
	145	#define EXCEPT_X64_INVALID_TSS 10\r
	146	#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
	147	#define EXCEPT_X64_STACK_FAULT 12\r
	148	#define EXCEPT_X64_GP_FAULT 13\r
	149	#define EXCEPT_X64_PAGE_FAULT 14\r
	150	#define EXCEPT_X64_FP_ERROR 16\r
	151	#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
	152	#define EXCEPT_X64_MACHINE_CHECK 18\r
	153	#define EXCEPT_X64_SIMD 19\r
	154	\r
	155	//\r
	156	// X64 processor context definition\r
	157	//\r
	158	// FXSAVE_STATE\r
	159	// FP / MMX / XMM registers (see fxrstor instruction definition)\r
	160	//\r
	161	typedef struct {\r
	162	UINT16 Fcw;\r
	163	UINT16 Fsw;\r
	164	UINT16 Ftw;\r
165	UINT16 Opcode;\r
166	UINT64 Rip;\r
167	UINT64 DataOffset;\r
168	UINT8 Reserved1[8];\r
169	UINT8 St0Mm0[10], Reserved2[6];\r
170	UINT8 St1Mm1[10], Reserved3[6];\r
171	UINT8 St2Mm2[10], Reserved4[6];\r
172	UINT8 St3Mm3[10], Reserved5[6];\r
173	UINT8 St4Mm4[10], Reserved6[6];\r
174	UINT8 St5Mm5[10], Reserved7[6];\r
175	UINT8 St6Mm6[10], Reserved8[6];\r
176	UINT8 St7Mm7[10], Reserved9[6];\r
177	UINT8 Xmm0[16];\r
178	UINT8 Xmm1[16];\r
179	UINT8 Xmm2[16];\r
180	UINT8 Xmm3[16];\r
181	UINT8 Xmm4[16];\r
182	UINT8 Xmm5[16];\r
183	UINT8 Xmm6[16];\r
184	UINT8 Xmm7[16];\r
d1f95000	185	//\r
19bee90c	186	// NOTE: UEFI 2.0 spec definition as follows. \r
d1f95000	187	//\r
d1f95000	188	UINT8 Reserved11[14 * 16];\r
d1f95000	189	} EFI_FX_SAVE_STATE_X64;\r
	190	\r
	191	typedef struct {\r
	192	UINT64 ExceptionData;\r
	193	EFI_FX_SAVE_STATE_X64 FxSaveState;\r
	194	UINT64 Dr0;\r
	195	UINT64 Dr1;\r
	196	UINT64 Dr2;\r
	197	UINT64 Dr3;\r
	198	UINT64 Dr6;\r
	199	UINT64 Dr7;\r
	200	UINT64 Cr0;\r
	201	UINT64 Cr1; /* Reserved */\r
	202	UINT64 Cr2;\r
	203	UINT64 Cr3;\r
	204	UINT64 Cr4;\r
	205	UINT64 Cr8;\r
	206	UINT64 Rflags;\r
	207	UINT64 Ldtr;\r
	208	UINT64 Tr;\r
	209	UINT64 Gdtr[2];\r
	210	UINT64 Idtr[2];\r
	211	UINT64 Rip;\r
	212	UINT64 Gs;\r
	213	UINT64 Fs;\r
	214	UINT64 Es;\r
	215	UINT64 Ds;\r
	216	UINT64 Cs;\r
	217	UINT64 Ss;\r
	218	UINT64 Rdi;\r
	219	UINT64 Rsi;\r
	220	UINT64 Rbp;\r
	221	UINT64 Rsp;\r
	222	UINT64 Rbx;\r
	223	UINT64 Rdx;\r
	224	UINT64 Rcx;\r
	225	UINT64 Rax;\r
	226	UINT64 R8;\r
	227	UINT64 R9;\r
	228	UINT64 R10;\r
	229	UINT64 R11;\r
	230	UINT64 R12;\r
	231	UINT64 R13;\r
	232	UINT64 R14;\r
	233	UINT64 R15;\r
	234	} EFI_SYSTEM_CONTEXT_X64;\r
	235	\r
	236	//\r
	237	// IPF processor exception types\r
	238	//\r
	239	#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
	240	#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
	241	#define EXCEPT_IPF_DATA_TLB 2\r
	242	#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r
	243	#define EXCEPT_IPF_ALT_DATA_TLB 4\r
	244	#define EXCEPT_IPF_DATA_NESTED_TLB 5\r
	245	#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
	246	#define EXCEPT_IPF_DATA_KEY_MISSED 7\r
	247	#define EXCEPT_IPF_DIRTY_BIT 8\r
	248	#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
	249	#define EXCEPT_IPF_DATA_ACCESS_BIT 10\r
	250	#define EXCEPT_IPF_BREAKPOINT 11\r
	251	#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r
	252	//\r
253	// 13 - 19 reserved\r
254	//\r
255	#define EXCEPT_IPF_PAGE_NOT_PRESENT 20\r
256	#define EXCEPT_IPF_KEY_PERMISSION 21\r
257	#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22\r
258	#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23\r
259	#define EXCEPT_IPF_GENERAL_EXCEPTION 24\r
260	#define EXCEPT_IPF_DISABLED_FP_REGISTER 25\r
261	#define EXCEPT_IPF_NAT_CONSUMPTION 26\r
262	#define EXCEPT_IPF_SPECULATION 27\r
263	//\r
264	// 28 reserved\r
265	//\r
266	#define EXCEPT_IPF_DEBUG 29\r
267	#define EXCEPT_IPF_UNALIGNED_REFERENCE 30\r
268	#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31\r
269	#define EXCEPT_IPF_FP_FAULT 32\r
270	#define EXCEPT_IPF_FP_TRAP 33\r
271	#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34\r
272	#define EXCEPT_IPF_TAKEN_BRANCH 35\r
273	#define EXCEPT_IPF_SINGLE_STEP 36\r
274	//\r
275	// 37 - 44 reserved\r
276	//\r
277	#define EXCEPT_IPF_IA32_EXCEPTION 45\r
278	#define EXCEPT_IPF_IA32_INTERCEPT 46\r
279	#define EXCEPT_IPF_IA32_INTERRUPT 47\r
280	\r
281	//\r
282	// IPF processor context definition\r
283	//\r
284	typedef struct {\r
285	//\r
286	// The first reserved field is necessary to preserve alignment for the correct\r
287	// bits in UNAT and to insure F2 is 16 byte aligned..\r
288	//\r
289	UINT64 Reserved;\r
290	UINT64 R1;\r
291	UINT64 R2;\r
292	UINT64 R3;\r
293	UINT64 R4;\r
294	UINT64 R5;\r
295	UINT64 R6;\r
296	UINT64 R7;\r
297	UINT64 R8;\r
298	UINT64 R9;\r
299	UINT64 R10;\r
300	UINT64 R11;\r
301	UINT64 R12;\r
302	UINT64 R13;\r
303	UINT64 R14;\r
304	UINT64 R15;\r
305	UINT64 R16;\r
306	UINT64 R17;\r
307	UINT64 R18;\r
308	UINT64 R19;\r
309	UINT64 R20;\r
310	UINT64 R21;\r
311	UINT64 R22;\r
312	UINT64 R23;\r
313	UINT64 R24;\r
314	UINT64 R25;\r
315	UINT64 R26;\r
316	UINT64 R27;\r
317	UINT64 R28;\r
318	UINT64 R29;\r
319	UINT64 R30;\r
320	UINT64 R31;\r
321	\r
322	UINT64 F2[2];\r
323	UINT64 F3[2];\r
324	UINT64 F4[2];\r
325	UINT64 F5[2];\r
326	UINT64 F6[2];\r
327	UINT64 F7[2];\r
328	UINT64 F8[2];\r
329	UINT64 F9[2];\r
330	UINT64 F10[2];\r
331	UINT64 F11[2];\r
332	UINT64 F12[2];\r
333	UINT64 F13[2];\r
334	UINT64 F14[2];\r
335	UINT64 F15[2];\r
336	UINT64 F16[2];\r
337	UINT64 F17[2];\r
338	UINT64 F18[2];\r
339	UINT64 F19[2];\r
340	UINT64 F20[2];\r
341	UINT64 F21[2];\r
342	UINT64 F22[2];\r
343	UINT64 F23[2];\r
344	UINT64 F24[2];\r
345	UINT64 F25[2];\r
346	UINT64 F26[2];\r
347	UINT64 F27[2];\r
348	UINT64 F28[2];\r
349	UINT64 F29[2];\r
350	UINT64 F30[2];\r
351	UINT64 F31[2];\r
352	\r
353	UINT64 Pr;\r
354	\r
355	UINT64 B0;\r
356	UINT64 B1;\r
357	UINT64 B2;\r
358	UINT64 B3;\r
359	UINT64 B4;\r
360	UINT64 B5;\r
361	UINT64 B6;\r
362	UINT64 B7;\r
363	\r
364	//\r
365	// application registers\r
366	//\r
367	UINT64 ArRsc;\r
368	UINT64 ArBsp;\r
369	UINT64 ArBspstore;\r
370	UINT64 ArRnat;\r
371	\r
372	UINT64 ArFcr;\r
373	\r
374	UINT64 ArEflag;\r
375	UINT64 ArCsd;\r
376	UINT64 ArSsd;\r
377	UINT64 ArCflg;\r
378	UINT64 ArFsr;\r
379	UINT64 ArFir;\r
380	UINT64 ArFdr;\r
381	\r
382	UINT64 ArCcv;\r
383	\r
384	UINT64 ArUnat;\r
385	\r
386	UINT64 ArFpsr;\r
387	\r
388	UINT64 ArPfs;\r
389	UINT64 ArLc;\r
390	UINT64 ArEc;\r
391	\r
392	//\r
393	// control registers\r
394	//\r
395	UINT64 CrDcr;\r
396	UINT64 CrItm;\r
397	UINT64 CrIva;\r
398	UINT64 CrPta;\r
399	UINT64 CrIpsr;\r
400	UINT64 CrIsr;\r
401	UINT64 CrIip;\r
402	UINT64 CrIfa;\r
403	UINT64 CrItir;\r
404	UINT64 CrIipa;\r
405	UINT64 CrIfs;\r
406	UINT64 CrIim;\r
407	UINT64 CrIha;\r
408	\r
409	//\r
410	// debug registers\r
411	//\r
412	UINT64 Dbr0;\r
413	UINT64 Dbr1;\r
414	UINT64 Dbr2;\r
415	UINT64 Dbr3;\r
416	UINT64 Dbr4;\r
417	UINT64 Dbr5;\r
418	UINT64 Dbr6;\r
419	UINT64 Dbr7;\r
420	\r
421	UINT64 Ibr0;\r
422	UINT64 Ibr1;\r
423	UINT64 Ibr2;\r
424	UINT64 Ibr3;\r
425	UINT64 Ibr4;\r
426	UINT64 Ibr5;\r
427	UINT64 Ibr6;\r
428	UINT64 Ibr7;\r
429	\r
430	//\r
431	// virtual registers - nat bits for R1-R31\r
432	//\r
433	UINT64 IntNat;\r
434	\r
435	} EFI_SYSTEM_CONTEXT_IPF;\r
436	\r
437	//\r
438	// EBC processor exception types\r
439	//\r
440	#define EXCEPT_EBC_UNDEFINED 0\r
441	#define EXCEPT_EBC_DIVIDE_ERROR 1\r
442	#define EXCEPT_EBC_DEBUG 2\r
443	#define EXCEPT_EBC_BREAKPOINT 3\r
444	#define EXCEPT_EBC_OVERFLOW 4\r
445	#define EXCEPT_EBC_INVALID_OPCODE 5 // opcode out of range\r
446	#define EXCEPT_EBC_STACK_FAULT 6\r
447	#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
448	#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 // malformed instruction\r
449	#define EXCEPT_EBC_BAD_BREAK 9 // BREAK 0 or undefined BREAK\r
450	#define EXCEPT_EBC_STEP 10 // to support debug stepping\r
451	//\r
452	// For coding convenience, define the maximum valid EBC exception.\r
453	//\r
454	#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
455	\r
456	//\r
457	// EBC processor context definition\r
458	//\r
459	typedef struct {\r
460	UINT64 R0;\r
461	UINT64 R1;\r
462	UINT64 R2;\r
463	UINT64 R3;\r
464	UINT64 R4;\r
465	UINT64 R5;\r
466	UINT64 R6;\r
467	UINT64 R7;\r
468	UINT64 Flags;\r
469	UINT64 ControlFlags;\r
470	UINT64 Ip;\r
471	} EFI_SYSTEM_CONTEXT_EBC;\r
472	\r
473	//\r
474	// Universal EFI_SYSTEM_CONTEXT definition\r
475	//\r
476	typedef union {\r
477	EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
478	EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
479	EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
480	EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
481	} EFI_SYSTEM_CONTEXT;\r
482	\r
483	//\r
484	// DebugSupport callback function prototypes\r
485	//\r
486	\r
487	/** \r
488	Registers and enables an exception callback function for the specified exception.\r
489	\r
490	@param ExceptionType Exception types in EBC, IA-32, X64, or IPF\r
491	@param SystemContext Exception content.\r
492	\r
493	**/\r
494	typedef\r
495	VOID\r
8b13229b	496	(*EFI_EXCEPTION_CALLBACK)(\r
d1f95000	497	IN EFI_EXCEPTION_TYPE ExceptionType,\r
	498	IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
	499	);\r
	500	\r
	501	/** \r
	502	Registers and enables the on-target debug agent's periodic entry point.\r
	503	\r
	504	@param SystemContext Exception content.\r
	505	\r
	506	**/\r
	507	typedef\r
	508	VOID\r
8b13229b	509	(*EFI_PERIODIC_CALLBACK)(\r
d1f95000	510	IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
	511	);\r
	512	\r
	513	//\r
	514	// Machine type definition\r
	515	//\r
	516	typedef enum {\r
	517	IsaIa32 = IMAGE_FILE_MACHINE_I386, // 0x014C\r
	518	IsaX64 = IMAGE_FILE_MACHINE_X64, // 0x8664\r
	519	IsaIpf = IMAGE_FILE_MACHINE_IA64, // 0x0200\r
	520	IsaEbc = IMAGE_FILE_MACHINE_EBC // 0x0EBC\r
	521	} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
	522	\r
	523	\r
	524	//\r
	525	// DebugSupport member function definitions\r
	526	//\r
	527	\r
	528	/** \r
	529	Returns the maximum value that may be used for the ProcessorIndex parameter in\r
	530	RegisterPeriodicCallback() and RegisterExceptionCallback(). \r
	531	\r
	532	@param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
	533	@param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported\r
	534	processor index is returned. \r
	535	\r
	536	@retval EFI_SUCCESS The function completed successfully. \r
	537	\r
	538	**/\r
	539	typedef\r
	540	EFI_STATUS\r
8b13229b	541	(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(\r
d1f95000	542	IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
	543	OUT UINTN *MaxProcessorIndex\r
	544	);\r
	545	\r
	546	/** \r
	547	Registers a function to be called back periodically in interrupt context.\r
	548	\r
	549	@param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
	550	@param ProcessorIndex Specifies which processor the callback function applies to.\r
	551	@param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main\r
	552	periodic entry point of the debug agent.\r
	553	\r
	554	@retval EFI_SUCCESS The function completed successfully. \r
	555	@retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
	556	function was previously registered. \r
	557	@retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback \r
	558	function. \r
	559	\r
	560	**/\r
	561	typedef\r
	562	EFI_STATUS\r
8b13229b	563	(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(\r
d1f95000	564	IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
	565	IN UINTN ProcessorIndex,\r
	566	IN EFI_PERIODIC_CALLBACK PeriodicCallback\r
	567	);\r
	568	\r
	569	/** \r
	570	Registers a function to be called when a given processor exception occurs.\r
	571	\r
	572	@param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
	573	@param ProcessorIndex Specifies which processor the callback function applies to.\r
	574	@param PeriodicCallback A pointer to a function of type EXCEPTION_CALLBACK that is called\r
	575	when the processor exception specified by ExceptionType occurs. \r
	576	@param ExceptionType Specifies which processor exception to hook. \r
	577	\r
	578	@retval EFI_SUCCESS The function completed successfully. \r
	579	@retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
	580	function was previously registered. \r
	581	@retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback \r
	582	function. \r
	583	\r
	584	**/\r
	585	typedef\r
	586	EFI_STATUS\r
8b13229b	587	(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(\r
d1f95000	588	IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
	589	IN UINTN ProcessorIndex,\r
	590	IN EFI_EXCEPTION_CALLBACK ExceptionCallback,\r
	591	IN EFI_EXCEPTION_TYPE ExceptionType\r
	592	);\r
	593	\r
	594	/** \r
	595	Invalidates processor instruction cache for a memory range. Subsequent execution in this range\r
	596	causes a fresh memory fetch to retrieve code to be executed. \r
	597	\r
	598	@param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
	599	@param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.\r
	600	@param Start Specifies the physical base of the memory range to be invalidated. \r
	601	@param Length Specifies the minimum number of bytes in the processor's instruction\r
	602	cache to invalidate. \r
	603	\r
	604	@retval EFI_SUCCESS The function completed successfully. \r
	605	\r
	606	**/\r
	607	typedef\r
	608	EFI_STATUS\r
8b13229b	609	(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(\r
d1f95000	610	IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
	611	IN UINTN ProcessorIndex,\r
	612	IN VOID *Start,\r
	613	IN UINT64 Length\r
	614	);\r
	615	\r
	616	//\r
	617	// DebugSupport protocol definition\r
	618	//\r
4ca9b6c4 LG	619	/**\r
	620	@par Protocol Description:\r
	621	This protocol provides the services to allow the debug agent to register \r
	622	callback functions that are called either periodically or when specific \r
	623	processor exceptions occur.\r
	624	\r
	625	@param Isa\r
	626	Declares the processor architecture for this instance of the EFI\r
	627	Debug Support protocol.\r
	628	\r
	629	@param GetMaximumProcessorIndex\r
	630	Returns the maximum processor index value that may be used.\r
	631	\r
	632	@param RegisterPeriodicCallback\r
	633	Registers a callback function that will be invoked periodically\r
	634	and asynchronously to the execution of EFI.\r
	635	\r
	636	@param RegisterExceptionCallback\r
	637	Registers a callback function that will be called each time the\r
	638	specified processor exception occurs.\r
	639	\r
	640	@param InvalidateInstructionCache\r
	641	Invalidate the instruction cache of the processor. This is required\r
	642	by processor architectures where instruction and data caches are\r
	643	not coherent when instructions in the code under debug has been\r
	644	modified by the debug agent.\r
	645	**/\r
d1f95000	646	struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r
	647	EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
	648	EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
	649	EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
	650	EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r
	651	EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r
	652	};\r
	653	\r
	654	extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
	655	\r
	656	#endif \r