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MdePkg/Include: RISC-V definitions.
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d1f95000 1/** @file\r
b4319afb 2 DebugSupport protocol and supporting definitions as defined in the UEFI2.4\r
d1f95000 3 specification.\r
4\r
5 The DebugSupport protocol is used by source level debuggers to abstract the\r
6 processor and handle context save and restore operations.\r
7\r
9095d37b 8Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
b4319afb 9Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
d3abb40d 10Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
b4319afb 11\r
9344f092 12SPDX-License-Identifier: BSD-2-Clause-Patent\r
d1f95000 13\r
d1f95000 14**/\r
15\r
16#ifndef __DEBUG_SUPPORT_H__\r
17#define __DEBUG_SUPPORT_H__\r
18\r
19#include <IndustryStandard/PeImage.h>\r
20\r
21typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r
22\r
99e8ed21 23///\r
af2dc6a7 24/// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}.\r
99e8ed21 25///\r
d1f95000 26#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r
27 { \\r
28 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \\r
29 }\r
30\r
99e8ed21 31///\r
9319d2c2
LG		 32/// Processor exception to be hooked.\r
33/// All exception types for IA32, X64, Itanium and EBC processors are defined.\r
99e8ed21 34///\r
d1f95000 35typedef INTN EFI_EXCEPTION_TYPE;\r
36\r
9319d2c2 37///\r
af2dc6a7 38/// IA-32 processor exception types.\r
9319d2c2 39///\r
d1f95000 40#define EXCEPT_IA32_DIVIDE_ERROR 0\r
41#define EXCEPT_IA32_DEBUG 1\r
42#define EXCEPT_IA32_NMI 2\r
43#define EXCEPT_IA32_BREAKPOINT 3\r
44#define EXCEPT_IA32_OVERFLOW 4\r
45#define EXCEPT_IA32_BOUND 5\r
46#define EXCEPT_IA32_INVALID_OPCODE 6\r
47#define EXCEPT_IA32_DOUBLE_FAULT 8\r
48#define EXCEPT_IA32_INVALID_TSS 10\r
49#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
50#define EXCEPT_IA32_STACK_FAULT 12\r
51#define EXCEPT_IA32_GP_FAULT 13\r
52#define EXCEPT_IA32_PAGE_FAULT 14\r
53#define EXCEPT_IA32_FP_ERROR 16\r
54#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
55#define EXCEPT_IA32_MACHINE_CHECK 18\r
56#define EXCEPT_IA32_SIMD 19\r
57\r
8b6c989b 58///\r
af2dc6a7 59/// FXSAVE_STATE.\r
60/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
8b6c989b 61///\r
d1f95000 62typedef struct {\r
63 UINT16 Fcw;\r
64 UINT16 Fsw;\r
65 UINT16 Ftw;\r
66 UINT16 Opcode;\r
67 UINT32 Eip;\r
68 UINT16 Cs;\r
69 UINT16 Reserved1;\r
70 UINT32 DataOffset;\r
71 UINT16 Ds;\r
72 UINT8 Reserved2[10];\r
d1f95000 73 UINT8 St0Mm0[10], Reserved3[6];\r
74 UINT8 St1Mm1[10], Reserved4[6];\r
75 UINT8 St2Mm2[10], Reserved5[6];\r
76 UINT8 St3Mm3[10], Reserved6[6];\r
77 UINT8 St4Mm4[10], Reserved7[6];\r
78 UINT8 St5Mm5[10], Reserved8[6];\r
79 UINT8 St6Mm6[10], Reserved9[6];\r
80 UINT8 St7Mm7[10], Reserved10[6];\r
81 UINT8 Xmm0[16];\r
82 UINT8 Xmm1[16];\r
83 UINT8 Xmm2[16];\r
84 UINT8 Xmm3[16];\r
85 UINT8 Xmm4[16];\r
86 UINT8 Xmm5[16];\r
87 UINT8 Xmm6[16];\r
88 UINT8 Xmm7[16];\r
89 UINT8 Reserved11[14 * 16];\r
90} EFI_FX_SAVE_STATE_IA32;\r
d1f95000 91\r
9319d2c2 92///\r
af2dc6a7 93/// IA-32 processor context definition.\r
9319d2c2 94///\r
d1f95000 95typedef struct {\r
96 UINT32 ExceptionData;\r
d1f95000 97 EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
d1f95000 98 UINT32 Dr0;\r
99 UINT32 Dr1;\r
100 UINT32 Dr2;\r
101 UINT32 Dr3;\r
102 UINT32 Dr6;\r
103 UINT32 Dr7;\r
104 UINT32 Cr0;\r
105 UINT32 Cr1; /* Reserved */\r
106 UINT32 Cr2;\r
107 UINT32 Cr3;\r
108 UINT32 Cr4;\r
109 UINT32 Eflags;\r
110 UINT32 Ldtr;\r
111 UINT32 Tr;\r
112 UINT32 Gdtr[2];\r
113 UINT32 Idtr[2];\r
114 UINT32 Eip;\r
115 UINT32 Gs;\r
116 UINT32 Fs;\r
117 UINT32 Es;\r
118 UINT32 Ds;\r
119 UINT32 Cs;\r
120 UINT32 Ss;\r
121 UINT32 Edi;\r
122 UINT32 Esi;\r
123 UINT32 Ebp;\r
124 UINT32 Esp;\r
125 UINT32 Ebx;\r
126 UINT32 Edx;\r
127 UINT32 Ecx;\r
128 UINT32 Eax;\r
129} EFI_SYSTEM_CONTEXT_IA32;\r
130\r
9319d2c2 131///\r
af2dc6a7 132/// x64 processor exception types.\r
9319d2c2 133///\r
d1f95000 134#define EXCEPT_X64_DIVIDE_ERROR 0\r
135#define EXCEPT_X64_DEBUG 1\r
136#define EXCEPT_X64_NMI 2\r
137#define EXCEPT_X64_BREAKPOINT 3\r
138#define EXCEPT_X64_OVERFLOW 4\r
139#define EXCEPT_X64_BOUND 5\r
140#define EXCEPT_X64_INVALID_OPCODE 6\r
141#define EXCEPT_X64_DOUBLE_FAULT 8\r
142#define EXCEPT_X64_INVALID_TSS 10\r
143#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
144#define EXCEPT_X64_STACK_FAULT 12\r
145#define EXCEPT_X64_GP_FAULT 13\r
146#define EXCEPT_X64_PAGE_FAULT 14\r
147#define EXCEPT_X64_FP_ERROR 16\r
148#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
149#define EXCEPT_X64_MACHINE_CHECK 18\r
150#define EXCEPT_X64_SIMD 19\r
151\r
8b6c989b 152///\r
af2dc6a7 153/// FXSAVE_STATE.\r
154/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
8b6c989b 155///\r
d1f95000 156typedef struct {\r
157 UINT16 Fcw;\r
158 UINT16 Fsw;\r
159 UINT16 Ftw;\r
160 UINT16 Opcode;\r
161 UINT64 Rip;\r
162 UINT64 DataOffset;\r
163 UINT8 Reserved1[8];\r
164 UINT8 St0Mm0[10], Reserved2[6];\r
165 UINT8 St1Mm1[10], Reserved3[6];\r
166 UINT8 St2Mm2[10], Reserved4[6];\r
167 UINT8 St3Mm3[10], Reserved5[6];\r
168 UINT8 St4Mm4[10], Reserved6[6];\r
169 UINT8 St5Mm5[10], Reserved7[6];\r
170 UINT8 St6Mm6[10], Reserved8[6];\r
171 UINT8 St7Mm7[10], Reserved9[6];\r
172 UINT8 Xmm0[16];\r
173 UINT8 Xmm1[16];\r
174 UINT8 Xmm2[16];\r
175 UINT8 Xmm3[16];\r
176 UINT8 Xmm4[16];\r
177 UINT8 Xmm5[16];\r
178 UINT8 Xmm6[16];\r
179 UINT8 Xmm7[16];\r
d1f95000 180 //\r
9095d37b 181 // NOTE: UEFI 2.0 spec definition as follows.\r
d1f95000 182 //\r
183 UINT8 Reserved11[14 * 16];\r
d1f95000 184} EFI_FX_SAVE_STATE_X64;\r
185\r
9319d2c2 186///\r
af2dc6a7 187/// x64 processor context definition.\r
9319d2c2 188///\r
d1f95000 189typedef struct {\r
190 UINT64 ExceptionData;\r
191 EFI_FX_SAVE_STATE_X64 FxSaveState;\r
192 UINT64 Dr0;\r
193 UINT64 Dr1;\r
194 UINT64 Dr2;\r
195 UINT64 Dr3;\r
196 UINT64 Dr6;\r
197 UINT64 Dr7;\r
198 UINT64 Cr0;\r
199 UINT64 Cr1; /* Reserved */\r
200 UINT64 Cr2;\r
201 UINT64 Cr3;\r
202 UINT64 Cr4;\r
203 UINT64 Cr8;\r
204 UINT64 Rflags;\r
205 UINT64 Ldtr;\r
206 UINT64 Tr;\r
207 UINT64 Gdtr[2];\r
208 UINT64 Idtr[2];\r
209 UINT64 Rip;\r
210 UINT64 Gs;\r
211 UINT64 Fs;\r
212 UINT64 Es;\r
213 UINT64 Ds;\r
214 UINT64 Cs;\r
215 UINT64 Ss;\r
216 UINT64 Rdi;\r
217 UINT64 Rsi;\r
218 UINT64 Rbp;\r
219 UINT64 Rsp;\r
220 UINT64 Rbx;\r
221 UINT64 Rdx;\r
222 UINT64 Rcx;\r
223 UINT64 Rax;\r
224 UINT64 R8;\r
225 UINT64 R9;\r
226 UINT64 R10;\r
227 UINT64 R11;\r
228 UINT64 R12;\r
229 UINT64 R13;\r
230 UINT64 R14;\r
231 UINT64 R15;\r
232} EFI_SYSTEM_CONTEXT_X64;\r
233\r
9319d2c2 234///\r
af2dc6a7 235/// Itanium Processor Family Exception types.\r
9319d2c2 236///\r
d1f95000 237#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
238#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
239#define EXCEPT_IPF_DATA_TLB 2\r
240#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r
241#define EXCEPT_IPF_ALT_DATA_TLB 4\r
242#define EXCEPT_IPF_DATA_NESTED_TLB 5\r
243#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
244#define EXCEPT_IPF_DATA_KEY_MISSED 7\r
245#define EXCEPT_IPF_DIRTY_BIT 8\r
246#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
247#define EXCEPT_IPF_DATA_ACCESS_BIT 10\r
248#define EXCEPT_IPF_BREAKPOINT 11\r
249#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r
250//\r
251// 13 - 19 reserved\r
252//\r
253#define EXCEPT_IPF_PAGE_NOT_PRESENT 20\r
254#define EXCEPT_IPF_KEY_PERMISSION 21\r
255#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22\r
256#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23\r
257#define EXCEPT_IPF_GENERAL_EXCEPTION 24\r
258#define EXCEPT_IPF_DISABLED_FP_REGISTER 25\r
259#define EXCEPT_IPF_NAT_CONSUMPTION 26\r
260#define EXCEPT_IPF_SPECULATION 27\r
261//\r
262// 28 reserved\r
263//\r
264#define EXCEPT_IPF_DEBUG 29\r
265#define EXCEPT_IPF_UNALIGNED_REFERENCE 30\r
266#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31\r
267#define EXCEPT_IPF_FP_FAULT 32\r
268#define EXCEPT_IPF_FP_TRAP 33\r
269#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34\r
270#define EXCEPT_IPF_TAKEN_BRANCH 35\r
271#define EXCEPT_IPF_SINGLE_STEP 36\r
272//\r
273// 37 - 44 reserved\r
274//\r
275#define EXCEPT_IPF_IA32_EXCEPTION 45\r
276#define EXCEPT_IPF_IA32_INTERCEPT 46\r
277#define EXCEPT_IPF_IA32_INTERRUPT 47\r
278\r
8b6c989b 279///\r
af2dc6a7 280/// IPF processor context definition.\r
8b6c989b 281///\r
d1f95000 282typedef struct {\r
283 //\r
284 // The first reserved field is necessary to preserve alignment for the correct\r
630b4187 285 // bits in UNAT and to insure F2 is 16 byte aligned.\r
d1f95000 286 //\r
287 UINT64 Reserved;\r
288 UINT64 R1;\r
289 UINT64 R2;\r
290 UINT64 R3;\r
291 UINT64 R4;\r
292 UINT64 R5;\r
293 UINT64 R6;\r
294 UINT64 R7;\r
295 UINT64 R8;\r
296 UINT64 R9;\r
297 UINT64 R10;\r
298 UINT64 R11;\r
299 UINT64 R12;\r
300 UINT64 R13;\r
301 UINT64 R14;\r
302 UINT64 R15;\r
303 UINT64 R16;\r
304 UINT64 R17;\r
305 UINT64 R18;\r
306 UINT64 R19;\r
307 UINT64 R20;\r
308 UINT64 R21;\r
309 UINT64 R22;\r
310 UINT64 R23;\r
311 UINT64 R24;\r
312 UINT64 R25;\r
313 UINT64 R26;\r
314 UINT64 R27;\r
315 UINT64 R28;\r
316 UINT64 R29;\r
317 UINT64 R30;\r
318 UINT64 R31;\r
319\r
320 UINT64 F2[2];\r
321 UINT64 F3[2];\r
322 UINT64 F4[2];\r
323 UINT64 F5[2];\r
324 UINT64 F6[2];\r
325 UINT64 F7[2];\r
326 UINT64 F8[2];\r
327 UINT64 F9[2];\r
328 UINT64 F10[2];\r
329 UINT64 F11[2];\r
330 UINT64 F12[2];\r
331 UINT64 F13[2];\r
332 UINT64 F14[2];\r
333 UINT64 F15[2];\r
334 UINT64 F16[2];\r
335 UINT64 F17[2];\r
336 UINT64 F18[2];\r
337 UINT64 F19[2];\r
338 UINT64 F20[2];\r
339 UINT64 F21[2];\r
340 UINT64 F22[2];\r
341 UINT64 F23[2];\r
342 UINT64 F24[2];\r
343 UINT64 F25[2];\r
344 UINT64 F26[2];\r
345 UINT64 F27[2];\r
346 UINT64 F28[2];\r
347 UINT64 F29[2];\r
348 UINT64 F30[2];\r
349 UINT64 F31[2];\r
350\r
351 UINT64 Pr;\r
352\r
353 UINT64 B0;\r
354 UINT64 B1;\r
355 UINT64 B2;\r
356 UINT64 B3;\r
357 UINT64 B4;\r
358 UINT64 B5;\r
359 UINT64 B6;\r
360 UINT64 B7;\r
361\r
362 //\r
363 // application registers\r
364 //\r
365 UINT64 ArRsc;\r
366 UINT64 ArBsp;\r
367 UINT64 ArBspstore;\r
368 UINT64 ArRnat;\r
369\r
370 UINT64 ArFcr;\r
371\r
372 UINT64 ArEflag;\r
373 UINT64 ArCsd;\r
374 UINT64 ArSsd;\r
375 UINT64 ArCflg;\r
376 UINT64 ArFsr;\r
377 UINT64 ArFir;\r
378 UINT64 ArFdr;\r
379\r
380 UINT64 ArCcv;\r
381\r
382 UINT64 ArUnat;\r
383\r
384 UINT64 ArFpsr;\r
385\r
386 UINT64 ArPfs;\r
387 UINT64 ArLc;\r
388 UINT64 ArEc;\r
389\r
390 //\r
391 // control registers\r
392 //\r
393 UINT64 CrDcr;\r
394 UINT64 CrItm;\r
395 UINT64 CrIva;\r
396 UINT64 CrPta;\r
397 UINT64 CrIpsr;\r
398 UINT64 CrIsr;\r
399 UINT64 CrIip;\r
400 UINT64 CrIfa;\r
401 UINT64 CrItir;\r
402 UINT64 CrIipa;\r
403 UINT64 CrIfs;\r
404 UINT64 CrIim;\r
405 UINT64 CrIha;\r
406\r
407 //\r
408 // debug registers\r
409 //\r
410 UINT64 Dbr0;\r
411 UINT64 Dbr1;\r
412 UINT64 Dbr2;\r
413 UINT64 Dbr3;\r
414 UINT64 Dbr4;\r
415 UINT64 Dbr5;\r
416 UINT64 Dbr6;\r
417 UINT64 Dbr7;\r
418\r
419 UINT64 Ibr0;\r
420 UINT64 Ibr1;\r
421 UINT64 Ibr2;\r
422 UINT64 Ibr3;\r
423 UINT64 Ibr4;\r
424 UINT64 Ibr5;\r
425 UINT64 Ibr6;\r
426 UINT64 Ibr7;\r
427\r
428 //\r
429 // virtual registers - nat bits for R1-R31\r
430 //\r
431 UINT64 IntNat;\r
432\r
433} EFI_SYSTEM_CONTEXT_IPF;\r
434\r
9319d2c2 435///\r
af2dc6a7 436/// EBC processor exception types.\r
9319d2c2 437///\r
d1f95000 438#define EXCEPT_EBC_UNDEFINED 0\r
439#define EXCEPT_EBC_DIVIDE_ERROR 1\r
440#define EXCEPT_EBC_DEBUG 2\r
441#define EXCEPT_EBC_BREAKPOINT 3\r
442#define EXCEPT_EBC_OVERFLOW 4\r
af2dc6a7 443#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.\r
d1f95000 444#define EXCEPT_EBC_STACK_FAULT 6\r
445#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
af2dc6a7 446#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.\r
447#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.\r
448#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.\r
99e8ed21 449///\r
450/// For coding convenience, define the maximum valid EBC exception.\r
451///\r
d1f95000 452#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
453\r
99e8ed21 454///\r
af2dc6a7 455/// EBC processor context definition.\r
99e8ed21 456///\r
d1f95000 457typedef struct {\r
458 UINT64 R0;\r
459 UINT64 R1;\r
460 UINT64 R2;\r
461 UINT64 R3;\r
462 UINT64 R4;\r
463 UINT64 R5;\r
464 UINT64 R6;\r
465 UINT64 R7;\r
466 UINT64 Flags;\r
467 UINT64 ControlFlags;\r
468 UINT64 Ip;\r
469} EFI_SYSTEM_CONTEXT_EBC;\r
470\r
ebd04fc2 471\r
472\r
473///\r
af2dc6a7 474/// ARM processor exception types.\r
ebd04fc2 475///\r
476#define EXCEPT_ARM_RESET 0\r
477#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1\r
478#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2\r
479#define EXCEPT_ARM_PREFETCH_ABORT 3\r
480#define EXCEPT_ARM_DATA_ABORT 4\r
481#define EXCEPT_ARM_RESERVED 5\r
482#define EXCEPT_ARM_IRQ 6\r
483#define EXCEPT_ARM_FIQ 7\r
484\r
485///\r
486/// For coding convenience, define the maximum valid ARM exception.\r
487///\r
488#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ\r
489\r
490///\r
af2dc6a7 491/// ARM processor context definition.\r
ebd04fc2 492///\r
493typedef struct {\r
494 UINT32 R0;\r
495 UINT32 R1;\r
496 UINT32 R2;\r
497 UINT32 R3;\r
498 UINT32 R4;\r
499 UINT32 R5;\r
500 UINT32 R6;\r
501 UINT32 R7;\r
502 UINT32 R8;\r
503 UINT32 R9;\r
504 UINT32 R10;\r
505 UINT32 R11;\r
506 UINT32 R12;\r
507 UINT32 SP;\r
508 UINT32 LR;\r
509 UINT32 PC;\r
510 UINT32 CPSR;\r
511 UINT32 DFSR;\r
512 UINT32 DFAR;\r
513 UINT32 IFSR;\r
514 UINT32 IFAR;\r
515} EFI_SYSTEM_CONTEXT_ARM;\r
516\r
b4319afb
HL		 517\r
518///\r
519/// AARCH64 processor exception types.\r
520///\r
521#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0\r
522#define EXCEPT_AARCH64_IRQ 1\r
523#define EXCEPT_AARCH64_FIQ 2\r
524#define EXCEPT_AARCH64_SERROR 3\r
525\r
526///\r
527/// For coding convenience, define the maximum valid ARM exception.\r
528///\r
529#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR\r
530\r
531typedef struct {\r
532 // General Purpose Registers\r
533 UINT64 X0;\r
534 UINT64 X1;\r
535 UINT64 X2;\r
536 UINT64 X3;\r
537 UINT64 X4;\r
538 UINT64 X5;\r
539 UINT64 X6;\r
540 UINT64 X7;\r
541 UINT64 X8;\r
542 UINT64 X9;\r
543 UINT64 X10;\r
544 UINT64 X11;\r
545 UINT64 X12;\r
546 UINT64 X13;\r
547 UINT64 X14;\r
548 UINT64 X15;\r
549 UINT64 X16;\r
550 UINT64 X17;\r
551 UINT64 X18;\r
552 UINT64 X19;\r
553 UINT64 X20;\r
554 UINT64 X21;\r
555 UINT64 X22;\r
556 UINT64 X23;\r
557 UINT64 X24;\r
558 UINT64 X25;\r
559 UINT64 X26;\r
560 UINT64 X27;\r
561 UINT64 X28;\r
562 UINT64 FP; // x29 - Frame pointer\r
563 UINT64 LR; // x30 - Link Register\r
564 UINT64 SP; // x31 - Stack pointer\r
565\r
566 // FP/SIMD Registers\r
567 UINT64 V0[2];\r
568 UINT64 V1[2];\r
569 UINT64 V2[2];\r
570 UINT64 V3[2];\r
571 UINT64 V4[2];\r
572 UINT64 V5[2];\r
573 UINT64 V6[2];\r
574 UINT64 V7[2];\r
575 UINT64 V8[2];\r
576 UINT64 V9[2];\r
577 UINT64 V10[2];\r
578 UINT64 V11[2];\r
579 UINT64 V12[2];\r
580 UINT64 V13[2];\r
581 UINT64 V14[2];\r
582 UINT64 V15[2];\r
583 UINT64 V16[2];\r
584 UINT64 V17[2];\r
585 UINT64 V18[2];\r
586 UINT64 V19[2];\r
587 UINT64 V20[2];\r
588 UINT64 V21[2];\r
589 UINT64 V22[2];\r
590 UINT64 V23[2];\r
591 UINT64 V24[2];\r
592 UINT64 V25[2];\r
593 UINT64 V26[2];\r
594 UINT64 V27[2];\r
595 UINT64 V28[2];\r
596 UINT64 V29[2];\r
597 UINT64 V30[2];\r
598 UINT64 V31[2];\r
599\r
600 UINT64 ELR; // Exception Link Register\r
601 UINT64 SPSR; // Saved Processor Status Register\r
602 UINT64 FPSR; // Floating Point Status Register\r
603 UINT64 ESR; // Exception syndrome register\r
604 UINT64 FAR; // Fault Address Register\r
605} EFI_SYSTEM_CONTEXT_AARCH64;\r
606\r
d3abb40d
AC		 607///\r
608/// RISC-V processor exception types.\r
609///\r
610#define EXCEPT_RISCV_INST_MISALIGNED 0\r
611#define EXCEPT_RISCV_INST_ACCESS_FAULT 1\r
612#define EXCEPT_RISCV_ILLEGAL_INST 2\r
613#define EXCEPT_RISCV_BREAKPOINT 3\r
614#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4\r
615#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5\r
616#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6\r
617#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7\r
618#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8\r
619#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9\r
620#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10\r
621#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11\r
622\r
623#define EXCEPT_RISCV_SOFTWARE_INT 0x0\r
624#define EXCEPT_RISCV_TIMER_INT 0x1\r
625\r
626typedef struct {\r
627 UINT64 X0;\r
628 UINT64 X1;\r
629 UINT64 X2;\r
630 UINT64 X3;\r
631 UINT64 X4;\r
632 UINT64 X5;\r
633 UINT64 X6;\r
634 UINT64 X7;\r
635 UINT64 X8;\r
636 UINT64 X9;\r
637 UINT64 X10;\r
638 UINT64 X11;\r
639 UINT64 X12;\r
640 UINT64 X13;\r
641 UINT64 X14;\r
642 UINT64 X15;\r
643 UINT64 X16;\r
644 UINT64 X17;\r
645 UINT64 X18;\r
646 UINT64 X19;\r
647 UINT64 X20;\r
648 UINT64 X21;\r
649 UINT64 X22;\r
650 UINT64 X23;\r
651 UINT64 X24;\r
652 UINT64 X25;\r
653 UINT64 X26;\r
654 UINT64 X27;\r
655 UINT64 X28;\r
656 UINT64 X29;\r
657 UINT64 X30;\r
658 UINT64 X31;\r
659} EFI_SYSTEM_CONTEXT_RISCV64;\r
b4319afb 660\r
ebd04fc2 661///\r
af2dc6a7 662/// Universal EFI_SYSTEM_CONTEXT definition.\r
ebd04fc2 663///\r
d1f95000 664typedef union {\r
665 EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
666 EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
667 EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
668 EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
ebd04fc2 669 EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;\r
b4319afb 670 EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;\r
d3abb40d 671 EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;\r
d1f95000 672} EFI_SYSTEM_CONTEXT;\r
673\r
674//\r
675// DebugSupport callback function prototypes\r
676//\r
677\r
9095d37b 678/**\r
d1f95000 679 Registers and enables an exception callback function for the specified exception.\r
9095d37b 680\r
af2dc6a7 681 @param ExceptionType Exception types in EBC, IA-32, x64, or IPF.\r
d1f95000 682 @param SystemContext Exception content.\r
9095d37b 683\r
d1f95000 684**/\r
685typedef\r
686VOID\r
6d3ea23f 687(EFIAPI *EFI_EXCEPTION_CALLBACK)(\r
d1f95000 688 IN EFI_EXCEPTION_TYPE ExceptionType,\r
689 IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
690 );\r
691\r
9095d37b 692/**\r
d1f95000 693 Registers and enables the on-target debug agent's periodic entry point.\r
9095d37b 694\r
d1f95000 695 @param SystemContext Exception content.\r
9095d37b 696\r
d1f95000 697**/\r
698typedef\r
699VOID\r
6d3ea23f 700(EFIAPI *EFI_PERIODIC_CALLBACK)(\r
d1f95000 701 IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
702 );\r
703\r
8b6c989b 704///\r
705/// Machine type definition\r
706///\r
d1f95000 707typedef enum {\r
05e3c7cc 708 IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r
709 IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r
710 IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r
ebd04fc2 711 IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC\r
b4319afb
HL		 712 IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2\r
713 IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64\r
d1f95000 714} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
715\r
716\r
717//\r
718// DebugSupport member function definitions\r
719//\r
720\r
9095d37b 721/**\r
d1f95000 722 Returns the maximum value that may be used for the ProcessorIndex parameter in\r
9095d37b
LG		 723 RegisterPeriodicCallback() and RegisterExceptionCallback().\r
724\r
d1f95000 725 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
726 @param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported\r
9095d37b
LG		 727 processor index is returned.\r
728\r
729 @retval EFI_SUCCESS The function completed successfully.\r
730\r
d1f95000 731**/\r
732typedef\r
733EFI_STATUS\r
8b13229b 734(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(\r
d1f95000 735 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
736 OUT UINTN *MaxProcessorIndex\r
737 );\r
738\r
9095d37b 739/**\r
d1f95000 740 Registers a function to be called back periodically in interrupt context.\r
9095d37b 741\r
d1f95000 742 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
743 @param ProcessorIndex Specifies which processor the callback function applies to.\r
744 @param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main\r
745 periodic entry point of the debug agent.\r
9095d37b
LG		 746\r
747 @retval EFI_SUCCESS The function completed successfully.\r
d1f95000 748 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
9095d37b
LG		 749 function was previously registered.\r
750 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback\r
751 function.\r
752\r
d1f95000 753**/\r
754typedef\r
755EFI_STATUS\r
8b13229b 756(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(\r
d1f95000 757 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
758 IN UINTN ProcessorIndex,\r
759 IN EFI_PERIODIC_CALLBACK PeriodicCallback\r
760 );\r
761\r
9095d37b 762/**\r
d1f95000 763 Registers a function to be called when a given processor exception occurs.\r
9095d37b 764\r
d1f95000 765 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
766 @param ProcessorIndex Specifies which processor the callback function applies to.\r
89df7f9d 767 @param ExceptionCallback A pointer to a function of type EXCEPTION_CALLBACK that is called\r
9095d37b
LG		 768 when the processor exception specified by ExceptionType occurs.\r
769 @param ExceptionType Specifies which processor exception to hook.\r
770\r
771 @retval EFI_SUCCESS The function completed successfully.\r
d1f95000 772 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
9095d37b
LG		 773 function was previously registered.\r
774 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback\r
775 function.\r
776\r
d1f95000 777**/\r
778typedef\r
779EFI_STATUS\r
8b13229b 780(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(\r
d1f95000 781 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
782 IN UINTN ProcessorIndex,\r
783 IN EFI_EXCEPTION_CALLBACK ExceptionCallback,\r
784 IN EFI_EXCEPTION_TYPE ExceptionType\r
785 );\r
786\r
9095d37b 787/**\r
d1f95000 788 Invalidates processor instruction cache for a memory range. Subsequent execution in this range\r
9095d37b
LG		 789 causes a fresh memory fetch to retrieve code to be executed.\r
790\r
d1f95000 791 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
792 @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.\r
9095d37b 793 @param Start Specifies the physical base of the memory range to be invalidated.\r
d1f95000 794 @param Length Specifies the minimum number of bytes in the processor's instruction\r
9095d37b
LG		 795 cache to invalidate.\r
796\r
797 @retval EFI_SUCCESS The function completed successfully.\r
798\r
d1f95000 799**/\r
800typedef\r
801EFI_STATUS\r
8b13229b 802(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(\r
d1f95000 803 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
804 IN UINTN ProcessorIndex,\r
805 IN VOID *Start,\r
806 IN UINT64 Length\r
807 );\r
808\r
44717a39 809///\r
9095d37b
LG		 810/// This protocol provides the services to allow the debug agent to register\r
811/// callback functions that are called either periodically or when specific\r
44717a39 812/// processor exceptions occur.\r
813///\r
d1f95000 814struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r
44717a39 815 ///\r
816 /// Declares the processor architecture for this instance of the EFI Debug Support protocol.\r
817 ///\r
d1f95000 818 EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
819 EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
820 EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
821 EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r
822 EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r
823};\r
824\r
825extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
826\r
9095d37b 827#endif\r
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