projects / mirror_edk2.git / blame
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1 | /** @file\r |
| 2 | I2C Host Protocol as defined in the PI 1.3 specification.\r | |
| 3 | \r | |
| 4 | This protocol provides callers with the ability to do I/O transactions \r | |
| 5 | to all of the devices on the I2C bus.\r | |
| 6 | \r | |
| 1d956501 | 7 | Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r |
| 4006b0b5 EL |
8 | This program and the accompanying materials \r |
| 9 | are licensed and made available under the terms and conditions of the BSD License \r | |
| 10 | which accompanies this distribution. The full text of the license may be found at \r | |
| 11 | http://opensource.org/licenses/bsd-license.php \r | |
| 12 | \r | |
| 13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
| 14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
| 15 | \r | |
| 16 | @par Revision Reference:\r | |
| 17 | This protocol is from PI Version 1.3.\r | |
| 18 | \r | |
| 19 | **/\r | |
| 20 | \r | |
| 21 | #ifndef __I2C_HOST_H__\r | |
| 22 | #define __I2C_HOST_H__\r | |
| 23 | \r | |
| 24 | #include <Pi/PiI2c.h>\r | |
| 25 | \r | |
| 26 | #define EFI_I2C_HOST_PROTOCOL_GUID { 0xa5aab9e3, 0xc727, 0x48cd, { 0x8b, 0xbf, 0x42, 0x72, 0x33, 0x85, 0x49, 0x48 }}\r | |
| 27 | \r | |
| 28 | ///\r | |
| 29 | /// I2C Host Protocol\r | |
| 30 | ///\r | |
| 31 | /// The I2C bus driver uses the services of the EFI_I2C_HOST_PROTOCOL\r | |
| 32 | /// to produce an instance of the EFI_I2C_IO_PROTOCOL for each I2C\r | |
| 33 | /// device on an I2C bus.\r | |
| 34 | ///\r | |
| 35 | /// The EFI_I2C_HOST_PROTOCOL exposes an asynchronous interface to\r | |
| 36 | /// callers to perform transactions to any device on the I2C bus.\r | |
| 37 | /// Internally, the I2C host protocol manages the flow of the I2C\r | |
| 38 | /// transactions to the host controller, keeping them in FIFO order.\r | |
| 39 | /// Prior to each transaction, the I2C host protocol ensures that the\r | |
| 40 | /// switches and multiplexers are properly configured. The I2C host\r | |
| 41 | /// protocol then starts the transaction on the host controller using\r | |
| 42 | /// the EFI_I2C_MASTER_PROTOCOL.\r | |
| 43 | ///\r | |
| 44 | typedef struct _EFI_I2C_HOST_PROTOCOL EFI_I2C_HOST_PROTOCOL;\r | |
| 45 | \r | |
| 46 | \r | |
| 47 | /**\r | |
| 48 | Queue an I2C transaction for execution on the I2C controller.\r | |
| 49 | \r | |
| 50 | This routine must be called at or below TPL_NOTIFY. For\r | |
| 51 | synchronous requests this routine must be called at or below\r | |
| 52 | TPL_CALLBACK.\r | |
| 53 | \r | |
| 54 | The I2C host protocol uses the concept of I2C bus configurations\r | |
| 55 | to describe the I2C bus. An I2C bus configuration is defined as\r | |
| 56 | a unique setting of the multiplexers and switches in the I2C bus\r | |
| 57 | which enable access to one or more I2C devices. When using a\r | |
| 58 | switch to divide a bus, due to bus frequency differences, the\r | |
| 59 | I2C bus configuration management protocol defines an I2C bus\r | |
| 60 | configuration for the I2C devices on each side of the switch.\r | |
| 61 | When using a multiplexer, the I2C bus configuration management\r | |
| 62 | defines an I2C bus configuration for each of the selector values\r | |
| 63 | required to control the multiplexer. See Figure 1 in the I2C -bus\r | |
| 64 | specification and user manual for a complex I2C bus configuration.\r | |
| 65 | \r | |
| 66 | The I2C host protocol processes all transactions in FIFO order.\r | |
| 67 | Prior to performing the transaction, the I2C host protocol calls\r | |
| 68 | EnableI2cBusConfiguration to reconfigure the switches and\r | |
| 69 | multiplexers in the I2C bus enabling access to the specified I2C\r | |
| 70 | device. The EnableI2cBusConfiguration also selects the I2C bus\r | |
| 71 | frequency for the I2C device. After the I2C bus is configured,\r | |
| 72 | the I2C host protocol calls the I2C master protocol to start the\r | |
| 73 | I2C transaction.\r | |
| 74 | \r | |
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75 | When Event is NULL, QueueRequest() operates synchronously and\r |
| 76 | returns the I2C completion status as its return value.\r | |
| 77 | \r | |
| 78 | When Event is not NULL, QueueRequest() synchronously returns\r | |
| 79 | EFI_SUCCESS indicating that the asynchronously I2C transaction was\r | |
| 80 | queued. The values above are returned in the buffer pointed to by\r | |
| 81 | I2cStatus upon the completion of the I2C transaction when I2cStatus\r | |
| 82 | is not NULL.\r | |
| 83 | \r | |
| 84 | @param[in] This Pointer to an EFI_I2C_HOST_PROTOCOL structure.\r | |
| 85 | @param[in] I2cBusConfiguration I2C bus configuration to access the I2C\r | |
| 86 | device\r | |
| 87 | @param[in] SlaveAddress Address of the device on the I2C bus. Set\r | |
| 88 | the I2C_ADDRESSING_10_BIT when using 10-bit\r | |
| 89 | addresses, clear this bit for 7-bit addressing.\r | |
| 90 | Bits 0-6 are used for 7-bit I2C slave addresses\r | |
| 91 | and bits 0-9 are used for 10-bit I2C slave\r | |
| 92 | addresses.\r | |
| 93 | @param[in] Event Event to signal for asynchronous transactions,\r | |
| 94 | NULL for synchronous transactions\r | |
| 95 | @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure\r | |
| 96 | describing the I2C transaction\r | |
| 97 | @param[out] I2cStatus Optional buffer to receive the I2C transaction\r | |
| 98 | completion status\r | |
| 99 | \r | |
| 100 | @retval EFI_SUCCESS The asynchronous transaction was successfully\r | |
| 101 | queued when Event is not NULL.\r | |
| 102 | @retval EFI_SUCCESS The transaction completed successfully when\r | |
| 103 | Event is NULL.\r | |
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104 | @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is\r |
| 105 | too large.\r | |
| 106 | @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the\r | |
| 107 | transaction.\r | |
| 108 | @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r | |
| 109 | @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter\r | |
| 110 | @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value\r | |
| 111 | @retval EFI_NO_RESPONSE The I2C device is not responding to the slave\r | |
| 112 | address. EFI_DEVICE_ERROR will be returned\r | |
| 113 | if the controller cannot distinguish when the\r | |
| 114 | NACK occurred.\r | |
| 115 | @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction\r | |
| 116 | @retval EFI_UNSUPPORTED The controller does not support the requested\r | |
| 117 | transaction.\r | |
| 118 | \r | |
| 119 | **/\r | |
| 120 | typedef\r | |
| 121 | EFI_STATUS\r | |
| 122 | (EFIAPI *EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST) (\r | |
| 123 | IN CONST EFI_I2C_HOST_PROTOCOL *This,\r | |
| 124 | IN UINTN I2cBusConfiguration,\r | |
| 125 | IN UINTN SlaveAddress,\r | |
| 126 | IN EFI_EVENT Event OPTIONAL,\r | |
| 127 | IN EFI_I2C_REQUEST_PACKET *RequestPacket,\r | |
| 128 | OUT EFI_STATUS *I2cStatus OPTIONAL\r | |
| 129 | );\r | |
| 130 | \r | |
| 131 | ///\r | |
| 132 | /// I2C Host Protocol\r | |
| 133 | ///\r | |
| 134 | struct _EFI_I2C_HOST_PROTOCOL {\r | |
| 135 | ///\r | |
| 136 | /// Queue an I2C transaction for execution on the I2C bus\r | |
| 137 | ///\r | |
| 138 | EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST QueueRequest;\r | |
| 139 | \r | |
| 140 | ///\r | |
| 141 | /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure\r | |
| 142 | /// containing the capabilities of the I2C host controller.\r | |
| 143 | ///\r | |
| 144 | CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r | |
| 145 | };\r | |
| 146 | \r | |
| 147 | ///\r | |
| 148 | /// Reference to variable defined in the .DEC file\r | |
| 149 | ///\r | |
| 150 | extern EFI_GUID gEfiI2cHostProtocolGuid;\r | |
| 151 | \r | |
| 152 | #endif // __I2C_HOST_H__\r |