]> git.proxmox.com Git - mirror_edk2.git/blame - MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h
MdePkg FirmwareManagement.h: Fix typo EFI_SECURITY_VIOLATIO
[mirror_edk2.git] / MdePkg / Include / Protocol / PciHostBridgeResourceAllocation.h
CommitLineData
73c31a3d 1/** @file\r
2 This file declares PCI Host Bridge Resource Allocation Protocol which \r
3 provides the basic interfaces to abstract a PCI host bridge resource allocation. \r
4 This protocol is mandatory if the system includes PCI devices.\r
5 \r
9df063a0 6Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
af2dc6a7 7This program and the accompanying materials are licensed and made available under \r
8the terms and conditions of the BSD License that accompanies this distribution. \r
9The full text of the license may be found at\r
10http://opensource.org/licenses/bsd-license.php. \r
11 \r
12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
73c31a3d 14\r
15 @par Revision Reference:\r
16 This Protocol is defined in UEFI Platform Initialization Specification 1.2 \r
af2dc6a7 17 Volume 5: Standards.\r
73c31a3d 18 \r
19**/\r
20\r
21#ifndef _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_\r
22#define _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_\r
23\r
24//\r
25// This file must be included because EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
26// uses EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS\r
27//\r
28#include <Protocol/PciRootBridgeIo.h>\r
29\r
30///\r
af2dc6a7 31/// Global ID for the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
73c31a3d 32///\r
33#define EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GUID \\r
34 { \\r
35 0xCF8034BE, 0x6768, 0x4d8b, {0xB7,0x39,0x7C,0xCE,0x68,0x3A,0x9F,0xBE } \\r
36 }\r
37\r
38///\r
af2dc6a7 39/// Forward declaration for EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
73c31a3d 40///\r
41typedef struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL;\r
42\r
43/// If this bit is set, then the PCI Root Bridge does not\r
44/// support separate windows for Non-prefetchable and Prefetchable\r
45/// memory. A PCI bus driver needs to include requests for Prefetchable\r
46/// memory in the Non-prefetchable memory pool.\r
47///\r
48#define EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM 1\r
49\r
50///\r
51/// If this bit is set, then the PCI Root Bridge supports\r
52/// 64 bit memory windows. If this bit is not set,\r
53/// the PCI bus driver needs to include requests for 64 bit\r
54/// memory address in the corresponding 32 bit memory pool.\r
55///\r
56#define EFI_PCI_HOST_BRIDGE_MEM64_DECODE 2\r
57\r
58///\r
59/// A UINT64 value that contains the status of a PCI resource requested \r
60/// in the Configuration parameter returned by GetProposedResources()\r
61/// The legal values are EFI_RESOURCE_SATISFIED and EFI_RESOURCE_NOT_SATISFIED\r
62///\r
63typedef UINT64 EFI_RESOURCE_ALLOCATION_STATUS;\r
64\r
65///\r
66/// The request of this resource type could be fulfilled. Used in the \r
67/// Configuration parameter returned by GetProposedResources() to identify\r
68/// a PCI resources request that can be satisfied.\r
69///\r
70#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
71\r
72///\r
73/// The request of this resource type could not be fulfilled for its\r
74/// absence in the host bridge resource pool. Used in the Configuration parameter \r
75/// returned by GetProposedResources() to identify a PCI resources request that\r
76/// can not be satisfied.\r
77///\r
78#define EFI_RESOURCE_NOT_SATISFIED 0xFFFFFFFFFFFFFFFFULL\r
79\r
80///\r
af2dc6a7 81/// This enum is used to specify the phase of the PCI enumaeration process.\r
73c31a3d 82///\r
83typedef enum {\r
84 ///\r
85 /// Reset the host bridge PCI apertures and internal data structures.\r
86 /// PCI enumerator should issue this notification before starting fresh\r
87 /// enumeration process. Enumeration cannot be restarted after sending\r
88 /// any other notification such as EfiPciHostBridgeBeginBusAllocation.\r
89 ///\r
90 EfiPciHostBridgeBeginEnumeration,\r
91\r
92 ///\r
93 /// The bus allocation phase is about to begin. No specific action\r
94 /// is required here. This notification can be used to perform any\r
95 /// chipset specific programming. \r
96 ///\r
97 EfiPciHostBridgeBeginBusAllocation,\r
98\r
99 ///\r
100 /// The bus allocation and bus programming phase is complete. No specific\r
101 /// action is required here. This notification can be used to perform any\r
102 /// chipset specific programming. \r
103 ///\r
104 EfiPciHostBridgeEndBusAllocation,\r
105 \r
106 ///\r
107 /// The resource allocation phase is about to begin.No specific action is\r
108 /// required here. This notification can be used to perform any chipset specific programming. \r
109 ///\r
110 EfiPciHostBridgeBeginResourceAllocation,\r
111 \r
112 ///\r
113 /// Allocate resources per previously submitted requests for all the PCI Root\r
114 /// Bridges. These resource settings are returned on the next call to\r
115 /// GetProposedResources(). \r
116 ///\r
117 EfiPciHostBridgeAllocateResources,\r
118 \r
119 ///\r
120 /// Program the Host Bridge hardware to decode previously allocated resources\r
121 /// (proposed resources) for all the PCI Root Bridges.\r
122 ///\r
123 EfiPciHostBridgeSetResources,\r
124 \r
125 ///\r
126 /// De-allocate previously allocated resources previously for all the PCI\r
127 /// Root Bridges and reset the I/O and memory apertures to initial state. \r
128 ///\r
129 EfiPciHostBridgeFreeResources,\r
130 \r
131 ///\r
132 /// The resource allocation phase is completed. No specific action is required\r
133 /// here. This notification can be used to perform any chipset specific programming. \r
134 ///\r
1f7ff5ab 135 EfiPciHostBridgeEndResourceAllocation,\r
136\r
137 ///\r
138 /// The Host Bridge Enumeration is completed. No specific action is required here.\r
139 /// This notification can be used to perform any chipset specific programming.\r
140 ///\r
141 EfiPciHostBridgeEndEnumeration,\r
142 EfiMaxPciHostBridgeEnumerationPhase\r
73c31a3d 143} EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE;\r
144\r
145///\r
146/// Definitions of 2 notification points.\r
147///\r
148typedef enum {\r
149 ///\r
150 /// This notification is only applicable to PCI-PCI bridges and\r
151 /// indicates that the PCI enumerator is about to begin enumerating\r
152 /// the bus behind the PCI-PCI Bridge. This notification is sent after\r
153 /// the primary bus number, the secondary bus number and the subordinate\r
154 /// bus number registers in the PCI-PCI Bridge are programmed to valid\r
155 /// (not necessary final) values\r
156 ///\r
157 EfiPciBeforeChildBusEnumeration,\r
158\r
159 ///\r
160 /// This notification is sent before the PCI enumerator probes BAR registers\r
161 /// for every valid PCI function. \r
162 ///\r
163 EfiPciBeforeResourceCollection\r
164} EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE;\r
165\r
166/**\r
167 These are the notifications from the PCI bus driver that it is about to enter a certain phase of the PCI \r
168 enumeration process.\r
169\r
af2dc6a7 170 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
73c31a3d 171 instance.\r
af2dc6a7 172 @param[in] Phase The phase during enumeration.\r
73c31a3d 173\r
174 @retval EFI_SUCCESS The notification was accepted without any errors.\r
175 @retval EFI_INVALID_PARAMETER The Phase is invalid.\r
176 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error \r
177 is valid for a Phase of EfiPciHostBridgeAllocateResources if \r
178 SubmitResources() has not been called for one or more \r
179 PCI root bridges before this call.\r
180 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid for \r
181 a Phase of EfiPciHostBridgeSetResources.\r
182 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
183 This error is valid for a Phase of EfiPciHostBridgeAllocateResources\r
184 if the previously submitted resource requests cannot be fulfilled or were only \r
185 partially fulfilled\r
186\r
187**/\r
188typedef\r
189EFI_STATUS\r
190(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE)(\r
191 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
192 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
193 );\r
194\r
195/**\r
196 Returns the device handle of the next PCI root bridge that is associated with this host bridge.\r
197\r
af2dc6a7 198 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
73c31a3d 199 instance.\r
200 @param[in,out] RootBridgeHandle Returns the device handle of the next PCI root bridge. On input, it holds the \r
201 RootBridgeHandle that was returned by the most recent call to \r
202 GetNextRootBridge(). If RootBridgeHandle is NULL on input, the handle \r
203 for the first PCI root bridge is returned.\r
204\r
205 @retval EFI_SUCCESS The requested attribute information was returned.\r
206 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was returned \r
207 on a previous call to GetNextRootBridge().\r
208 @retval EFI_NOT_FOUND There are no more PCI root bridge device handles.\r
209\r
210**/\r
211typedef\r
212EFI_STATUS\r
213(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE)(\r
214 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
215 IN OUT EFI_HANDLE *RootBridgeHandle\r
216 );\r
217\r
218/**\r
219 Returns the allocation attributes of a PCI root bridge.\r
220\r
af2dc6a7 221 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
73c31a3d 222 instance.\r
223 @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested.\r
224 @param[out] Attribute The pointer to attributes of the PCI root bridge.\r
225\r
226 @retval EFI_SUCCESS The requested attribute information was returned.\r
227 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
228 @retval EFI_INVALID_PARAMETER Attributes is NULL.\r
229\r
230**/\r
231typedef\r
232EFI_STATUS\r
233(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES)(\r
234 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
235 IN EFI_HANDLE RootBridgeHandle,\r
236 OUT UINT64 *Attributes\r
237 );\r
238\r
239/**\r
240 Sets up the specified PCI root bridge for the bus enumeration process.\r
241\r
af2dc6a7 242 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
73c31a3d 243 instance.\r
244 @param[in] RootBridgeHandle The PCI root bridge to be set up.\r
af2dc6a7 245 @param[out] Configuration The pointer to the pointer to the PCI bus resource descriptor.\r
73c31a3d 246\r
247 @retval EFI_SUCCESS The PCI root bridge was set up and the bus range was returned in \r
248 Configuration.\r
249 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
250 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
251 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
252\r
253**/\r
254typedef\r
255EFI_STATUS\r
256(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION)(\r
257 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
258 IN EFI_HANDLE RootBridgeHandle,\r
259 OUT VOID **Configuration\r
260 );\r
261\r
262/**\r
263 Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
264\r
af2dc6a7 265 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
73c31a3d 266 instance. \r
267 @param[in] RootBridgeHandle The PCI root bridge whose bus range is to be programmed.\r
af2dc6a7 268 @param[in] Configuration The pointer to the PCI bus resource descriptor.\r
73c31a3d 269\r
270 @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r
271 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
272 @retval EFI_INVALID_PARAMETER Configuration is NULL\r
273 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0) \r
274 resource descriptor.\r
275 @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource\r
276 descriptor.\r
277 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI (2.0 & 3.0) resource \r
278 descriptors other than bus descriptors.\r
279 @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource \r
280 descriptors.\r
281 @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r
282 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r
283 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
284\r
285**/\r
286typedef\r
287EFI_STATUS\r
288(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS)(\r
289 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
290 IN EFI_HANDLE RootBridgeHandle,\r
291 IN VOID *Configuration\r
292 );\r
293\r
294/**\r
295 Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
296\r
af2dc6a7 297 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
73c31a3d 298 instance.\r
299 @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being \r
300 submitted.\r
301 @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r
302\r
303 @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were \r
304 accepted.\r
305 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
306 @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
307 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0) \r
308 resource descriptor.\r
309 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource \r
310 types that are not supported by this PCI root bridge. This error will \r
311 happen if the caller did not combine resources according to \r
312 Attributes that were returned by GetAllocAttributes().\r
313 @retval EFI_INVALID_PARAMETER "Address Range Maximum" is invalid.\r
314 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r
315 @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r
316 \r
317**/\r
318typedef\r
319EFI_STATUS\r
320(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES)(\r
321 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
322 IN EFI_HANDLE RootBridgeHandle,\r
323 IN VOID *Configuration\r
324 );\r
325\r
326/**\r
327 Returns the proposed resource settings for the specified PCI root bridge.\r
328\r
af2dc6a7 329 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
73c31a3d 330 instance.\r
331 @param[in] RootBridgeHandle The PCI root bridge handle.\r
332 @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
333\r
334 @retval EFI_SUCCESS The requested parameters were returned.\r
335 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
336 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
337 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
338\r
339**/\r
340typedef\r
341EFI_STATUS\r
342(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES)(\r
343 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
344 IN EFI_HANDLE RootBridgeHandle,\r
345 OUT VOID **Configuration\r
346 );\r
347\r
348/**\r
349 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various \r
350 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual \r
351 PCI controllers before enumeration.\r
352\r
af2dc6a7 353 @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
73c31a3d 354 @param[in] RootBridgeHandle The associated PCI root bridge handle.\r
355 @param[in] PciAddress The address of the PCI device on the PCI bus.\r
356 @param[in] Phase The phase of the PCI device enumeration.\r
357\r
358 @retval EFI_SUCCESS The requested parameters were returned.\r
359 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
360 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in \r
361 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
362 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator \r
363 should not enumerate this device, including its child devices if it is \r
364 a PCI-to-PCI bridge.\r
365\r
366**/\r
367typedef\r
368EFI_STATUS\r
369(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER)(\r
370 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
371 IN EFI_HANDLE RootBridgeHandle,\r
372 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
373 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
374 );\r
375\r
376///\r
377/// Provides the basic interfaces to abstract a PCI host bridge resource allocation.\r
378///\r
379struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL {\r
380 ///\r
381 /// The notification from the PCI bus enumerator that it is about to enter\r
382 /// a certain phase during the enumeration process.\r
383 ///\r
384 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE NotifyPhase;\r
385 \r
386 ///\r
387 /// Retrieves the device handle for the next PCI root bridge that is produced by the\r
388 /// host bridge to which this instance of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is attached. \r
389 ///\r
390 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE GetNextRootBridge;\r
391 \r
392 ///\r
393 /// Retrieves the allocation-related attributes of a PCI root bridge.\r
394 ///\r
395 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES GetAllocAttributes;\r
396 \r
397 ///\r
398 /// Sets up a PCI root bridge for bus enumeration.\r
399 ///\r
400 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION StartBusEnumeration;\r
401 \r
402 ///\r
403 /// Sets up the PCI root bridge so that it decodes a specific range of bus numbers.\r
404 ///\r
405 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS SetBusNumbers;\r
406 \r
407 ///\r
408 /// Submits the resource requirements for the specified PCI root bridge.\r
409 ///\r
410 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES SubmitResources;\r
411 \r
412 ///\r
413 /// Returns the proposed resource assignment for the specified PCI root bridges.\r
414 ///\r
415 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES GetProposedResources;\r
416 \r
417 ///\r
418 /// Provides hooks from the PCI bus driver to every PCI controller\r
419 /// (device/function) at various stages of the PCI enumeration process that\r
420 /// allow the host bridge driver to preinitialize individual PCI controllers\r
421 /// before enumeration. \r
422 ///\r
423 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER PreprocessController;\r
424};\r
425\r
426extern EFI_GUID gEfiPciHostBridgeResourceAllocationProtocolGuid;\r
427\r
428#endif\r