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878ddf1f 1/** @file\r
2 EFI PCI I/O Protocol\r
3\r
4 Copyright (c) 2006, Intel Corporation \r
5 All rights reserved. This program and the accompanying materials \r
6 are licensed and made available under the terms and conditions of the BSD License \r
7 which accompanies this distribution. The full text of the license may be found at \r
8 http://opensource.org/licenses/bsd-license.php \r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12\r
13 Module Name: PciIo.h\r
14\r
15**/\r
16\r
17#ifndef __PCI_IO_H__\r
18#define __PCI_IO_H__\r
19\r
20//\r
21// Global ID for the PCI I/O Protocol\r
22//\r
23#define EFI_PCI_IO_PROTOCOL_GUID \\r
24 { \\r
25 0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r
26 }\r
27\r
28typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r
29\r
30//\r
31// Prototypes for the PCI I/O Protocol\r
32//\r
33typedef enum {\r
34 EfiPciIoWidthUint8 = 0,\r
35 EfiPciIoWidthUint16,\r
36 EfiPciIoWidthUint32,\r
37 EfiPciIoWidthUint64,\r
38 EfiPciIoWidthFifoUint8,\r
39 EfiPciIoWidthFifoUint16,\r
40 EfiPciIoWidthFifoUint32,\r
41 EfiPciIoWidthFifoUint64,\r
42 EfiPciIoWidthFillUint8,\r
43 EfiPciIoWidthFillUint16,\r
44 EfiPciIoWidthFillUint32,\r
45 EfiPciIoWidthFillUint64,\r
46 EfiPciIoWidthMaximum\r
47} EFI_PCI_IO_PROTOCOL_WIDTH;\r
48\r
49//\r
50// Complete PCI address generater\r
51//\r
52#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff // Special BAR that passes a memory or I/O cycle through unchanged\r
53#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f // All the following I/O and Memory cycles\r
54#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 // I/O cycles 0x0000-0x00FF (10 bit decode)\r
55#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 // I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
56#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
57#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 // MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
58#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
59#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 // I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
60#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 // I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
61#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 // Map a memory range so write are combined\r
62#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 // Enable the I/O decode bit in the PCI Config Header\r
63#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 // Enable the Memory decode bit in the PCI Config Header\r
64#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 // Enable the DMA bit in the PCI Config Header\r
65#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 // Map a memory range so all r/w accesses are cached\r
66#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 // Disable a memory range\r
67#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 // Clear for an add-in PCI Device\r
68#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 // Clear for a physical PCI Option ROM accessed through ROM BAR\r
69#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 // Clear for PCI controllers that can not genrate a DAC\r
70#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 // I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
71#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
72#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x30000 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
73\r
74#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
75#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
76\r
77//\r
78// *******************************************************\r
79// EFI_PCI_IO_PROTOCOL_OPERATION\r
80// *******************************************************\r
81//\r
82typedef enum {\r
83 EfiPciIoOperationBusMasterRead,\r
84 EfiPciIoOperationBusMasterWrite,\r
85 EfiPciIoOperationBusMasterCommonBuffer,\r
86 EfiPciIoOperationMaximum\r
87} EFI_PCI_IO_PROTOCOL_OPERATION;\r
88\r
89//\r
90// *******************************************************\r
91// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION\r
92// *******************************************************\r
93//\r
94typedef enum {\r
95 EfiPciIoAttributeOperationGet,\r
96 EfiPciIoAttributeOperationSet,\r
97 EfiPciIoAttributeOperationEnable,\r
98 EfiPciIoAttributeOperationDisable,\r
99 EfiPciIoAttributeOperationSupported,\r
100 EfiPciIoAttributeOperationMaximum\r
101} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r
102\r
103/** \r
104 Reads from the memory space of a PCI controller. Returns when either the polling exit criteria is\r
105 satisfied or after a defined duration. \r
106 \r
107 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
108 @param Width Signifies the width of the memory or I/O operations.\r
109 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
110 base address for the memory operation to perform. \r
111 @param Offset The offset within the selected BAR to start the memory operation.\r
112 @param Mask Mask used for the polling criteria.\r
113 @param Value The comparison value used for the polling exit criteria.\r
114 @param Delay The number of 100 ns units to poll.\r
115 @param Result Pointer to the last value read from the memory location.\r
116 \r
117 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
118 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
119 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
120 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
121 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
122 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
123 \r
124**/\r
125typedef\r
126EFI_STATUS\r
127(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM) (\r
128 IN EFI_PCI_IO_PROTOCOL *This,\r
129 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
130 IN UINT8 BarIndex,\r
131 IN UINT64 Offset,\r
132 IN UINT64 Mask,\r
133 IN UINT64 Value,\r
134 IN UINT64 Delay,\r
135 OUT UINT64 *Result\r
136 );\r
137\r
138/** \r
139 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
140 \r
141 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
142 @param Width Signifies the width of the memory or I/O operations.\r
143 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
144 base address for the memory or I/O operation to perform. \r
145 @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
146 @param Count The number of memory or I/O operations to perform.\r
147 @param Buffer For read operations, the destination buffer to store the results. For write\r
148 operations, the source buffer to write data from. \r
149 \r
150 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
151 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
152 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
153 valid for the PCI BAR specified by BarIndex. \r
154 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
155 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
156 \r
157**/\r
158typedef\r
159EFI_STATUS\r
160(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM) (\r
161 IN EFI_PCI_IO_PROTOCOL *This,\r
162 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
163 IN UINT8 BarIndex,\r
164 IN UINT64 Offset,\r
165 IN UINTN Count,\r
166 IN OUT VOID *Buffer\r
167 );\r
168\r
169typedef struct {\r
170 EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r
171 EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r
172} EFI_PCI_IO_PROTOCOL_ACCESS;\r
173\r
174/** \r
175 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
176 \r
177 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
178 @param Width Signifies the width of the memory operations.\r
179 @param Offset The offset within the PCI configuration space for the PCI controller.\r
180 @param Count The number of PCI configuration operations to perform.\r
181 @param Buffer For read operations, the destination buffer to store the results. For write\r
182 operations, the source buffer to write data from.\r
183 \r
184 \r
185 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
186 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
187 valid for the PCI configuration header of the PCI controller.\r
188 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
189 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r
190 \r
191**/\r
192typedef\r
193EFI_STATUS\r
194(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG) (\r
195 IN EFI_PCI_IO_PROTOCOL *This,\r
196 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
197 IN UINT32 Offset,\r
198 IN UINTN Count,\r
199 IN OUT VOID *Buffer\r
200 );\r
201\r
202typedef struct {\r
203 EFI_PCI_IO_PROTOCOL_CONFIG Read;\r
204 EFI_PCI_IO_PROTOCOL_CONFIG Write;\r
205} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
206\r
207/** \r
208 Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
209 memory space.\r
210 \r
211 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
212 @param Width Signifies the width of the memory operations.\r
213 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
214 base address for the memory operation to perform. \r
215 @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
216 start the memory writes for the copy operation. \r
217 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
218 base address for the memory operation to perform. \r
219 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
220 the memory reads for the copy operation. \r
221 @param Count The number of memory operations to perform. Bytes moved is Width\r
222 size * Count, starting at DestOffset and SrcOffset. \r
223 \r
224 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
225 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
226 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
227 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
228 is not valid for the PCI BAR specified by DestBarIndex. \r
229 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
230 not valid for the PCI BAR specified by SrcBarIndex. \r
231 @retval EFI_INVALID_PARAMETER Width is invalid.\r
232 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
233 \r
234**/\r
235typedef\r
236EFI_STATUS\r
237(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM) (\r
238 IN EFI_PCI_IO_PROTOCOL *This,\r
239 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
240 IN UINT8 DestBarIndex,\r
241 IN UINT64 DestOffset,\r
242 IN UINT8 SrcBarIndex,\r
243 IN UINT64 SrcOffset,\r
244 IN UINTN Count\r
245 );\r
246\r
247/** \r
511710d6 248 Provides the PCI controller-Cspecific addresses needed to access system memory.\r
878ddf1f 249 \r
250 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
251 @param Operation Indicates if the bus master is going to read or write to system memory.\r
252 @param HostAddress The system memory address to map to the PCI controller.\r
253 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
254 that were mapped. \r
255 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
256 access the hosts HostAddress. \r
257 @param Mapping A resulting value to pass to Unmap().\r
258 \r
259 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
260 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. \r
261 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
262 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
263 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
264 \r
265**/\r
266typedef\r
267EFI_STATUS\r
268(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP) (\r
269 IN EFI_PCI_IO_PROTOCOL *This,\r
270 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
271 IN VOID *HostAddress,\r
272 IN OUT UINTN *NumberOfBytes,\r
273 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
274 OUT VOID **Mapping\r
275 );\r
276\r
277/** \r
278 Completes the Map() operation and releases any corresponding resources.\r
279 \r
280 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
281 @param Mapping The mapping value returned from Map().\r
282 \r
283 @retval EFI_SUCCESS The range was unmapped.\r
284 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
285 \r
286**/\r
287typedef\r
288EFI_STATUS\r
289(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP) (\r
290 IN EFI_PCI_IO_PROTOCOL *This,\r
291 IN VOID *Mapping\r
292 );\r
293\r
294/** \r
295 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
296 mapping. \r
297 \r
298 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
299 @param Type This parameter is not used and must be ignored.\r
300 @param MemoryType The type of memory to allocate, EfiBootServicesData or\r
301 EfiRuntimeServicesData. \r
302 @param Pages The number of pages to allocate. \r
303 @param HostAddress A pointer to store the base system memory address of the\r
304 allocated range. \r
305 @param Attributes The requested bit mask of attributes for the allocated range.\r
306 \r
307 @retval EFI_SUCCESS The requested memory pages were allocated.\r
308 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
309 MEMORY_WRITE_COMBINE and MEMORY_CACHED. \r
310 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
311 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. \r
312 \r
313**/\r
314typedef\r
315EFI_STATUS\r
316(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER) (\r
317 IN EFI_PCI_IO_PROTOCOL *This,\r
318 IN EFI_ALLOCATE_TYPE Type,\r
319 IN EFI_MEMORY_TYPE MemoryType,\r
320 IN UINTN Pages,\r
321 OUT VOID **HostAddress,\r
322 IN UINT64 Attributes\r
323 );\r
324\r
325/** \r
326 Frees memory that was allocated with AllocateBuffer().\r
327 \r
328 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
329 @param Pages The number of pages to free. \r
330 @param HostAddress The base system memory address of the allocated range. \r
331 \r
332 @retval EFI_SUCCESS The requested memory pages were freed.\r
333 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
334 was not allocated with AllocateBuffer().\r
335 \r
336**/\r
337typedef\r
338EFI_STATUS\r
339(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER) (\r
340 IN EFI_PCI_IO_PROTOCOL *This,\r
341 IN UINTN Pages,\r
342 IN VOID *HostAddress\r
343 );\r
344\r
345/** \r
346 Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
347 \r
348 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
349 \r
350 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
351 bridge to system memory. \r
352 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
353 host bridge due to a hardware error. \r
354 \r
355**/\r
356typedef\r
357EFI_STATUS\r
358(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH) (\r
359 IN EFI_PCI_IO_PROTOCOL *This\r
360 );\r
361\r
362/** \r
511710d6 363 Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
878ddf1f 364 \r
365 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
511710d6 366 @param SegmentNumber The PCI controller's current PCI segment number.\r
367 @param BusNumber The PCI controller's current PCI bus number.\r
368 @param DeviceNumber The PCI controller's current PCI device number.\r
369 @param FunctionNumber The PCI controller's current PCI function number.\r
878ddf1f 370 \r
371 @retval EFI_SUCCESS The PCI controller location was returned. \r
372 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
373 \r
374**/\r
375typedef\r
376EFI_STATUS\r
377(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION) (\r
378 IN EFI_PCI_IO_PROTOCOL *This,\r
379 OUT UINTN *SegmentNumber,\r
380 OUT UINTN *BusNumber,\r
381 OUT UINTN *DeviceNumber,\r
382 OUT UINTN *FunctionNumber\r
383 );\r
384\r
385/** \r
386 Performs an operation on the attributes that this PCI controller supports. The operations include\r
387 getting the set of supported attributes, retrieving the current attributes, setting the current \r
388 attributes, enabling attributes, and disabling attributes. \r
389 \r
390 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
391 @param Operation The operation to perform on the attributes for this PCI controller.\r
392 @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
393 operations. \r
394 @param Result A pointer to the result mask of attributes that are returned for the Get\r
395 and Supported operations. \r
396 \r
397 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
398 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
399 @retval EFI_UNSUPPORTED one or more of the bits set in \r
400 Attributes are not supported by this PCI controller or one of\r
401 its parent bridges when Operation is Set, Enable or Disable.\r
402 \r
403**/\r
404typedef\r
405EFI_STATUS\r
406(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES) (\r
407 IN EFI_PCI_IO_PROTOCOL *This,\r
408 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
409 IN UINT64 Attributes,\r
410 OUT UINT64 *Result OPTIONAL\r
411 );\r
412\r
413/** \r
414 Gets the attributes that this PCI controller supports setting on a BAR using\r
415 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
416 \r
417 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
418 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
419 base address for resource range. The legal range for this field is 0..5.\r
420 @param Supports A pointer to the mask of attributes that this PCI controller supports\r
421 setting for this BAR with SetBarAttributes(). \r
422 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r
423 configuration of this BAR of the PCI controller. \r
424 \r
425 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI \r
426 controller supports are returned in Supports. If Resources \r
427 is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r
428 controller is currently using are returned in Resources. \r
429 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
430 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
431 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
432 Resources. \r
433 \r
434**/\r
435typedef\r
436EFI_STATUS\r
437(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES) (\r
438 IN EFI_PCI_IO_PROTOCOL *This,\r
439 IN UINT8 BarIndex,\r
440 OUT UINT64 *Supports, OPTIONAL\r
441 OUT VOID **Resources OPTIONAL\r
442 );\r
443\r
444/** \r
445 Sets the attributes for a range of a BAR on a PCI controller.\r
446 \r
447 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
448 @param Attributes The mask of attributes to set for the resource range specified by\r
449 BarIndex, Offset, and Length. \r
450 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
451 base address for resource range. The legal range for this field is 0..5.\r
452 @param Offset A pointer to the BAR relative base address of the resource range to be\r
453 modified by the attributes specified by Attributes. \r
454 @param Length A pointer to the length of the resource range to be modified by the\r
455 attributes specified by Attributes. \r
456 \r
457 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource \r
458 range specified by BarIndex, Offset, and Length were \r
459 set on the PCI controller, and the actual resource range is returned\r
460 in Offset and Length. \r
461 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
462 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
463 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
464 resource range specified by BarIndex, Offset, and \r
465 Length. \r
466 \r
467**/\r
468typedef\r
469EFI_STATUS\r
470(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES) (\r
471 IN EFI_PCI_IO_PROTOCOL *This,\r
472 IN UINT64 Attributes,\r
473 IN UINT8 BarIndex,\r
474 IN OUT UINT64 *Offset,\r
475 IN OUT UINT64 *Length\r
476 );\r
477\r
478//\r
479// Interface structure for the PCI I/O Protocol\r
480//\r
481struct _EFI_PCI_IO_PROTOCOL {\r
482 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
483 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
484 EFI_PCI_IO_PROTOCOL_ACCESS Mem;\r
485 EFI_PCI_IO_PROTOCOL_ACCESS Io;\r
486 EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;\r
487 EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem;\r
488 EFI_PCI_IO_PROTOCOL_MAP Map;\r
489 EFI_PCI_IO_PROTOCOL_UNMAP Unmap;\r
490 EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
491 EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
492 EFI_PCI_IO_PROTOCOL_FLUSH Flush;\r
493 EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation;\r
494 EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;\r
495 EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;\r
496 EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;\r
497 UINT64 RomSize;\r
498 VOID *RomImage;\r
499};\r
500\r
501extern EFI_GUID gEfiPciIoProtocolGuid;\r
502\r
503#endif\r
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