[mirror_edk2.git] / MdePkg / Include / Protocol / PciIo.h

/** @file\r
  EFI PCI I/O Protocol\r
\r
  Copyright (c) 2006, Intel Corporation                                                         \r
  All rights reserved. This program and the accompanying materials                          \r
  are licensed and made available under the terms and conditions of the BSD License         \r
  which accompanies this distribution.  The full text of the license may be found at        \r
  http://opensource.org/licenses/bsd-license.php                                            \r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
  Module Name:  PciIo.h\r
\r
**/\r
\r
#ifndef __PCI_IO_H__\r
#define __PCI_IO_H__\r
\r
//\r
// Global ID for the PCI I/O Protocol\r
//\r
#define EFI_PCI_IO_PROTOCOL_GUID \\r
  { \\r
    0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r
  }\r
\r
typedef struct _EFI_PCI_IO_PROTOCOL  EFI_PCI_IO_PROTOCOL;\r
\r
//\r
// Prototypes for the PCI I/O Protocol\r
//\r
typedef enum {\r
  EfiPciIoWidthUint8      = 0,\r
  EfiPciIoWidthUint16,\r
  EfiPciIoWidthUint32,\r
  EfiPciIoWidthUint64,\r
  EfiPciIoWidthFifoUint8,\r
  EfiPciIoWidthFifoUint16,\r
  EfiPciIoWidthFifoUint32,\r
  EfiPciIoWidthFifoUint64,\r
  EfiPciIoWidthFillUint8,\r
  EfiPciIoWidthFillUint16,\r
  EfiPciIoWidthFillUint32,\r
  EfiPciIoWidthFillUint64,\r
  EfiPciIoWidthMaximum\r
} EFI_PCI_IO_PROTOCOL_WIDTH;\r
\r
//\r
// Complete PCI address generater\r
//\r
#define EFI_PCI_IO_PASS_THROUGH_BAR               0xff    // Special BAR that passes a memory or I/O cycle through unchanged\r
#define EFI_PCI_IO_ATTRIBUTE_MASK                 0x077f  // All the following I/O and Memory cycles\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO   0x0001  // I/O cycles 0x0000-0x00FF (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_IO               0x0002  // I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO       0x0004  // I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY           0x0008  // MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_IO               0x0010  // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO       0x0020  // I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO     0x0040  // I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080  // Map a memory range so write are combined\r
#define EFI_PCI_IO_ATTRIBUTE_IO                   0x0100  // Enable the I/O decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY               0x0200  // Enable the Memory decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER           0x0400  // Enable the DMA bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED        0x0800  // Map a memory range so all r/w accesses are cached\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE       0x1000  // Disable a memory range\r
#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE      0x2000  // Clear for an add-in PCI Device\r
#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM         0x4000  // Clear for a physical PCI Option ROM accessed through ROM BAR\r
#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE   0x8000  // Clear for PCI controllers that can not genrate a DAC\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16            0x10000 // I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16    0x20000 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16            0x30000 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
\r
#define EFI_PCI_DEVICE_ENABLE                     (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
#define EFI_VGA_DEVICE_ENABLE                     (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
\r
//\r
// *******************************************************\r
// EFI_PCI_IO_PROTOCOL_OPERATION\r
// *******************************************************\r
//\r
typedef enum {\r
  EfiPciIoOperationBusMasterRead,\r
  EfiPciIoOperationBusMasterWrite,\r
  EfiPciIoOperationBusMasterCommonBuffer,\r
  EfiPciIoOperationMaximum\r
} EFI_PCI_IO_PROTOCOL_OPERATION;\r
\r
//\r
// *******************************************************\r
// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION\r
// *******************************************************\r
//\r
typedef enum {\r
  EfiPciIoAttributeOperationGet,\r
  EfiPciIoAttributeOperationSet,\r
  EfiPciIoAttributeOperationEnable,\r
  EfiPciIoAttributeOperationDisable,\r
  EfiPciIoAttributeOperationSupported,\r
  EfiPciIoAttributeOperationMaximum\r
} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r
\r
/**                                                                 \r
  Reads from the memory space of a PCI controller. Returns when either the polling exit criteria is\r
  satisfied or after a defined duration.                                                           \r
          \r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Width                 Signifies the width of the memory or I/O operations.\r
  @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the\r
                                base address for the memory operation to perform.                   \r
  @param  Offset                The offset within the selected BAR to start the memory operation.\r
  @param  Mask                  Mask used for the polling criteria.\r
  @param  Value                 The comparison value used for the polling exit criteria.\r
  @param  Delay                 The number of 100 ns units to poll.\r
  @param  Result                Pointer to the last value read from the memory location.\r
                                \r
  @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.\r
  @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.\r
  @retval EFI_UNSUPPORTED       Offset is not valid for the BarIndex of this PCI controller.\r
  @retval EFI_TIMEOUT           Delay expired before a match occurred.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
                                   \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM) (\r
  IN EFI_PCI_IO_PROTOCOL           *This,\r
  IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN  UINT8                        BarIndex,\r
  IN  UINT64                       Offset,\r
  IN  UINT64                       Mask,\r
  IN  UINT64                       Value,\r
  IN  UINT64                       Delay,\r
  OUT UINT64                       *Result\r
  );\r
\r
/**                                                                 \r
  Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
          \r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Width                 Signifies the width of the memory or I/O operations.\r
  @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the\r
                                base address for the memory or I/O operation to perform.                    \r
  @param  Offset                The offset within the selected BAR to start the memory or I/O operation.                                \r
  @param  Count                 The number of memory or I/O operations to perform.\r
  @param  Buffer                For read operations, the destination buffer to store the results. For write\r
                                operations, the source buffer to write data from.                          \r
  \r
  @retval EFI_SUCCESS           The data was read from or written to the PCI controller.\r
  @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.\r
  @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not\r
                                valid for the PCI BAR specified by BarIndex.                  \r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
                                   \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM) (\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT8                        BarIndex,\r
  IN     UINT64                       Offset,\r
  IN     UINTN                        Count,\r
  IN OUT VOID                         *Buffer\r
  );\r
\r
typedef struct {\r
  EFI_PCI_IO_PROTOCOL_IO_MEM  Read;\r
  EFI_PCI_IO_PROTOCOL_IO_MEM  Write;\r
} EFI_PCI_IO_PROTOCOL_ACCESS;\r
\r
/**                                                                 \r
  Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
            \r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.  \r
  @param  Width                 Signifies the width of the memory operations.\r
  @param  Offset                The offset within the PCI configuration space for the PCI controller.\r
  @param  Count                 The number of PCI configuration operations to perform.\r
  @param  Buffer                For read operations, the destination buffer to store the results. For write\r
                                operations, the source buffer to write data from.\r
  \r
                                  \r
  @retval EFI_SUCCESS           The data was read from or written to the PCI controller.\r
  @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not\r
                                valid for the PCI configuration header of the PCI controller.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.                                 \r
  @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.                                \r
                                     \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG) (\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT32                       Offset,\r
  IN     UINTN                        Count,\r
  IN OUT VOID                         *Buffer\r
  );\r
\r
typedef struct {\r
  EFI_PCI_IO_PROTOCOL_CONFIG  Read;\r
  EFI_PCI_IO_PROTOCOL_CONFIG  Write;\r
} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
\r
/**                                                                 \r
  Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
  memory space.\r
            \r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Width                 Signifies the width of the memory operations.\r
  @param  DestBarIndex          The BAR index in the standard PCI Configuration header to use as the\r
                                base address for the memory operation to perform.                   \r
  @param  DestOffset            The destination offset within the BAR specified by DestBarIndex to\r
                                start the memory writes for the copy operation.                   \r
  @param  SrcBarIndex           The BAR index in the standard PCI Configuration header to use as the\r
                                base address for the memory operation to perform.                   \r
  @param  SrcOffset             The source offset within the BAR specified by SrcBarIndex to start\r
                                the memory reads for the copy operation.                          \r
  @param  Count                 The number of memory operations to perform. Bytes moved is Width\r
                                size * Count, starting at DestOffset and SrcOffset.             \r
                                \r
  @retval EFI_SUCCESS           The data was copied from one memory region to another memory region.\r
  @retval EFI_UNSUPPORTED       DestBarIndex not valid for this PCI controller.\r
  @retval EFI_UNSUPPORTED       SrcBarIndex not valid for this PCI controller.\r
  @retval EFI_UNSUPPORTED       The address range specified by DestOffset, Width, and Count\r
                                is not valid for the PCI BAR specified by DestBarIndex.    \r
  @retval EFI_UNSUPPORTED       The address range specified by SrcOffset, Width, and Count is\r
                                not valid for the PCI BAR specified by SrcBarIndex.          \r
  @retval EFI_INVALID_PARAMETER Width is invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
                                   \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM) (\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT8                        DestBarIndex,\r
  IN     UINT64                       DestOffset,\r
  IN     UINT8                        SrcBarIndex,\r
  IN     UINT64                       SrcOffset,\r
  IN     UINTN                        Count\r
  );\r
\r
/**                                                                 \r
Commit	Line	Data
878ddf1f	1	/** @file\r
	2	EFI PCI I/O Protocol\r
	3	\r
	4	Copyright (c) 2006, Intel Corporation \r
	5	All rights reserved. This program and the accompanying materials \r
	6	are licensed and made available under the terms and conditions of the BSD License \r
	7	which accompanies this distribution. The full text of the license may be found at \r
	8	http://opensource.org/licenses/bsd-license.php \r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	\r
	13	Module Name: PciIo.h\r
	14	\r
	15	**/\r
	16	\r
	17	#ifndef __PCI_IO_H__\r
	18	#define __PCI_IO_H__\r
	19	\r
	20	//\r
	21	// Global ID for the PCI I/O Protocol\r
	22	//\r
	23	#define EFI_PCI_IO_PROTOCOL_GUID \\r
	24	{ \\r
	25	0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r
	26	}\r
	27	\r
	28	typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r
	29	\r
	30	//\r
	31	// Prototypes for the PCI I/O Protocol\r
	32	//\r
	33	typedef enum {\r
	34	EfiPciIoWidthUint8 = 0,\r
	35	EfiPciIoWidthUint16,\r
	36	EfiPciIoWidthUint32,\r
	37	EfiPciIoWidthUint64,\r
	38	EfiPciIoWidthFifoUint8,\r
	39	EfiPciIoWidthFifoUint16,\r
	40	EfiPciIoWidthFifoUint32,\r
	41	EfiPciIoWidthFifoUint64,\r
	42	EfiPciIoWidthFillUint8,\r
	43	EfiPciIoWidthFillUint16,\r
	44	EfiPciIoWidthFillUint32,\r
	45	EfiPciIoWidthFillUint64,\r
	46	EfiPciIoWidthMaximum\r
	47	} EFI_PCI_IO_PROTOCOL_WIDTH;\r
	48	\r
	49	//\r
	50	// Complete PCI address generater\r
	51	//\r
	52	#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff // Special BAR that passes a memory or I/O cycle through unchanged\r
	53	#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f // All the following I/O and Memory cycles\r
	54	#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 // I/O cycles 0x0000-0x00FF (10 bit decode)\r
	55	#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 // I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
	56	#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
	57	#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 // MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
	58	#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
	59	#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 // I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
	60	#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 // I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
	61	#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 // Map a memory range so write are combined\r
	62	#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 // Enable the I/O decode bit in the PCI Config Header\r
	63	#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 // Enable the Memory decode bit in the PCI Config Header\r
	64	#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 // Enable the DMA bit in the PCI Config Header\r
65	#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 // Map a memory range so all r/w accesses are cached\r
66	#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 // Disable a memory range\r
67	#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 // Clear for an add-in PCI Device\r
68	#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 // Clear for a physical PCI Option ROM accessed through ROM BAR\r
69	#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 // Clear for PCI controllers that can not genrate a DAC\r
70	#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 // I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
71	#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
72	#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x30000 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
73	\r
74	#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO \| EFI_PCI_IO_ATTRIBUTE_MEMORY \| EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
75	#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO \| EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY \| EFI_PCI_IO_ATTRIBUTE_VGA_IO \| EFI_PCI_IO_ATTRIBUTE_IO)\r
76	\r
77	//\r
78	// *******************************************************\r
79	// EFI_PCI_IO_PROTOCOL_OPERATION\r
80	// *******************************************************\r
81	//\r
82	typedef enum {\r
83	EfiPciIoOperationBusMasterRead,\r
84	EfiPciIoOperationBusMasterWrite,\r
85	EfiPciIoOperationBusMasterCommonBuffer,\r
86	EfiPciIoOperationMaximum\r
87	} EFI_PCI_IO_PROTOCOL_OPERATION;\r
88	\r
89	//\r
90	// *******************************************************\r
91	// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION\r
92	// *******************************************************\r
93	//\r
94	typedef enum {\r
95	EfiPciIoAttributeOperationGet,\r
96	EfiPciIoAttributeOperationSet,\r
97	EfiPciIoAttributeOperationEnable,\r
98	EfiPciIoAttributeOperationDisable,\r
99	EfiPciIoAttributeOperationSupported,\r
100	EfiPciIoAttributeOperationMaximum\r
101	} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r
102	\r
103	/** \r
104	Reads from the memory space of a PCI controller. Returns when either the polling exit criteria is\r
105	satisfied or after a defined duration. \r
106	\r
107	@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
108	@param Width Signifies the width of the memory or I/O operations.\r
109	@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
110	base address for the memory operation to perform. \r
111	@param Offset The offset within the selected BAR to start the memory operation.\r
112	@param Mask Mask used for the polling criteria.\r
113	@param Value The comparison value used for the polling exit criteria.\r
114	@param Delay The number of 100 ns units to poll.\r
115	@param Result Pointer to the last value read from the memory location.\r
116	\r
117	@retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
118	@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
119	@retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
120	@retval EFI_TIMEOUT Delay expired before a match occurred.\r
121	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
122	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
123	\r
124	**/\r
125	typedef\r
126	EFI_STATUS\r
127	(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM) (\r
128	IN EFI_PCI_IO_PROTOCOL *This,\r
129	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
130	IN UINT8 BarIndex,\r
131	IN UINT64 Offset,\r
132	IN UINT64 Mask,\r
133	IN UINT64 Value,\r
134	IN UINT64 Delay,\r
135	OUT UINT64 *Result\r
136	);\r
137	\r
138	/** \r
139	Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
140	\r
141	@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
142	@param Width Signifies the width of the memory or I/O operations.\r
143	@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
144	base address for the memory or I/O operation to perform. \r
145	@param Offset The offset within the selected BAR to start the memory or I/O operation. \r
146	@param Count The number of memory or I/O operations to perform.\r
147	@param Buffer For read operations, the destination buffer to store the results. For write\r
148	operations, the source buffer to write data from. \r
149	\r
150	@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
151	@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
152	@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
153	valid for the PCI BAR specified by BarIndex. \r
154	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
155	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
156	\r
157	**/\r
158	typedef\r
159	EFI_STATUS\r
160	(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM) (\r
161	IN EFI_PCI_IO_PROTOCOL *This,\r
162	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
163	IN UINT8 BarIndex,\r
164	IN UINT64 Offset,\r
165	IN UINTN Count,\r
166	IN OUT VOID *Buffer\r
167	);\r
168	\r
169	typedef struct {\r
170	EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r
171	EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r
172	} EFI_PCI_IO_PROTOCOL_ACCESS;\r
173	\r
174	/** \r
175	Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
176	\r
177	@param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
178	@param Width Signifies the width of the memory operations.\r
179	@param Offset The offset within the PCI configuration space for the PCI controller.\r
180	@param Count The number of PCI configuration operations to perform.\r
181	@param Buffer For read operations, the destination buffer to store the results. For write\r
182	operations, the source buffer to write data from.\r
183	\r
184	\r
185	@retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
186	@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
187	valid for the PCI configuration header of the PCI controller.\r
188	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
189	@retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r
190	\r
191	**/\r
192	typedef\r
193	EFI_STATUS\r
194	(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG) (\r
195	IN EFI_PCI_IO_PROTOCOL *This,\r
196	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
197	IN UINT32 Offset,\r
198	IN UINTN Count,\r
199	IN OUT VOID *Buffer\r
200	);\r
201	\r
202	typedef struct {\r
203	EFI_PCI_IO_PROTOCOL_CONFIG Read;\r
204	EFI_PCI_IO_PROTOCOL_CONFIG Write;\r
205	} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
206	\r
207	/** \r
208	Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
209	memory space.\r
210	\r
211	@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
212	@param Width Signifies the width of the memory operations.\r
213	@param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
214	base address for the memory operation to perform. \r
215	@param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
216	start the memory writes for the copy operation. \r
217	@param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
218	base address for the memory operation to perform. \r
219	@param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
220	the memory reads for the copy operation. \r
221	@param Count The number of memory operations to perform. Bytes moved is Width\r
222	size * Count, starting at DestOffset and SrcOffset. \r
223	\r
224	@retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
225	@retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
226	@retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
227	@retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
228	is not valid for the PCI BAR specified by DestBarIndex. \r
229	@retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
230	not valid for the PCI BAR specified by SrcBarIndex. \r
231	@retval EFI_INVALID_PARAMETER Width is invalid.\r
232	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
233	\r
234	**/\r
235	typedef\r
236	EFI_STATUS\r
237	(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM) (\r
238	IN EFI_PCI_IO_PROTOCOL *This,\r
239	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
240	IN UINT8 DestBarIndex,\r
241	IN UINT64 DestOffset,\r
242	IN UINT8 SrcBarIndex,\r
243	IN UINT64 SrcOffset,\r
244	IN UINTN Count\r
245	);\r
246	\r
247	/** \r
248