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add a error macro to prevent this file from included for now #error "UEFI 2.1 HII...
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d1f95000 1/** @file\r
2 EFI PCI I/O Protocol\r
3\r
4 Copyright (c) 2006, Intel Corporation \r
5 All rights reserved. This program and the accompanying materials \r
6 are licensed and made available under the terms and conditions of the BSD License \r
7 which accompanies this distribution. The full text of the license may be found at \r
8 http://opensource.org/licenses/bsd-license.php \r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12\r
d1f95000 13**/\r
14\r
15#ifndef __PCI_IO_H__\r
16#define __PCI_IO_H__\r
17\r
18//\r
19// Global ID for the PCI I/O Protocol\r
20//\r
21#define EFI_PCI_IO_PROTOCOL_GUID \\r
22 { \\r
23 0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r
24 }\r
25\r
26typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r
27\r
28//\r
29// Prototypes for the PCI I/O Protocol\r
30//\r
31typedef enum {\r
32 EfiPciIoWidthUint8 = 0,\r
33 EfiPciIoWidthUint16,\r
34 EfiPciIoWidthUint32,\r
35 EfiPciIoWidthUint64,\r
36 EfiPciIoWidthFifoUint8,\r
37 EfiPciIoWidthFifoUint16,\r
38 EfiPciIoWidthFifoUint32,\r
39 EfiPciIoWidthFifoUint64,\r
40 EfiPciIoWidthFillUint8,\r
41 EfiPciIoWidthFillUint16,\r
42 EfiPciIoWidthFillUint32,\r
43 EfiPciIoWidthFillUint64,\r
44 EfiPciIoWidthMaximum\r
45} EFI_PCI_IO_PROTOCOL_WIDTH;\r
46\r
47//\r
48// Complete PCI address generater\r
49//\r
50#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff // Special BAR that passes a memory or I/O cycle through unchanged\r
51#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f // All the following I/O and Memory cycles\r
52#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 // I/O cycles 0x0000-0x00FF (10 bit decode)\r
53#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 // I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
54#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
55#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 // MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
56#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
57#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 // I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
58#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 // I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
59#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 // Map a memory range so write are combined\r
60#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 // Enable the I/O decode bit in the PCI Config Header\r
61#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 // Enable the Memory decode bit in the PCI Config Header\r
62#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 // Enable the DMA bit in the PCI Config Header\r
63#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 // Map a memory range so all r/w accesses are cached\r
64#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 // Disable a memory range\r
65#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 // Clear for an add-in PCI Device\r
66#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 // Clear for a physical PCI Option ROM accessed through ROM BAR\r
67#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 // Clear for PCI controllers that can not genrate a DAC\r
68#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 // I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
69#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
70#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x30000 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
71\r
72#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
73#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
74\r
75//\r
76// *******************************************************\r
77// EFI_PCI_IO_PROTOCOL_OPERATION\r
78// *******************************************************\r
79//\r
80typedef enum {\r
81 EfiPciIoOperationBusMasterRead,\r
82 EfiPciIoOperationBusMasterWrite,\r
83 EfiPciIoOperationBusMasterCommonBuffer,\r
84 EfiPciIoOperationMaximum\r
85} EFI_PCI_IO_PROTOCOL_OPERATION;\r
86\r
87//\r
88// *******************************************************\r
89// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION\r
90// *******************************************************\r
91//\r
92typedef enum {\r
93 EfiPciIoAttributeOperationGet,\r
94 EfiPciIoAttributeOperationSet,\r
95 EfiPciIoAttributeOperationEnable,\r
96 EfiPciIoAttributeOperationDisable,\r
97 EfiPciIoAttributeOperationSupported,\r
98 EfiPciIoAttributeOperationMaximum\r
99} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r
100\r
101/** \r
102 Reads from the memory space of a PCI controller. Returns when either the polling exit criteria is\r
103 satisfied or after a defined duration. \r
104 \r
105 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
106 @param Width Signifies the width of the memory or I/O operations.\r
107 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
108 base address for the memory operation to perform. \r
109 @param Offset The offset within the selected BAR to start the memory operation.\r
110 @param Mask Mask used for the polling criteria.\r
111 @param Value The comparison value used for the polling exit criteria.\r
112 @param Delay The number of 100 ns units to poll.\r
113 @param Result Pointer to the last value read from the memory location.\r
114 \r
115 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
116 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
117 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
118 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
119 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
120 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
121 \r
122**/\r
123typedef\r
124EFI_STATUS\r
125(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM) (\r
126 IN EFI_PCI_IO_PROTOCOL *This,\r
127 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
128 IN UINT8 BarIndex,\r
129 IN UINT64 Offset,\r
130 IN UINT64 Mask,\r
131 IN UINT64 Value,\r
132 IN UINT64 Delay,\r
133 OUT UINT64 *Result\r
134 );\r
135\r
136/** \r
137 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
138 \r
139 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
140 @param Width Signifies the width of the memory or I/O operations.\r
141 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
142 base address for the memory or I/O operation to perform. \r
143 @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
144 @param Count The number of memory or I/O operations to perform.\r
145 @param Buffer For read operations, the destination buffer to store the results. For write\r
146 operations, the source buffer to write data from. \r
147 \r
148 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
149 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
150 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
151 valid for the PCI BAR specified by BarIndex. \r
152 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
153 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
154 \r
155**/\r
156typedef\r
157EFI_STATUS\r
158(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM) (\r
159 IN EFI_PCI_IO_PROTOCOL *This,\r
160 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
161 IN UINT8 BarIndex,\r
162 IN UINT64 Offset,\r
163 IN UINTN Count,\r
164 IN OUT VOID *Buffer\r
165 );\r
166\r
167typedef struct {\r
168 EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r
169 EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r
170} EFI_PCI_IO_PROTOCOL_ACCESS;\r
171\r
172/** \r
173 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
174 \r
175 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
176 @param Width Signifies the width of the memory operations.\r
177 @param Offset The offset within the PCI configuration space for the PCI controller.\r
178 @param Count The number of PCI configuration operations to perform.\r
179 @param Buffer For read operations, the destination buffer to store the results. For write\r
180 operations, the source buffer to write data from.\r
181 \r
182 \r
183 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
184 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
185 valid for the PCI configuration header of the PCI controller.\r
186 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
187 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r
188 \r
189**/\r
190typedef\r
191EFI_STATUS\r
192(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG) (\r
193 IN EFI_PCI_IO_PROTOCOL *This,\r
194 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
195 IN UINT32 Offset,\r
196 IN UINTN Count,\r
197 IN OUT VOID *Buffer\r
198 );\r
199\r
200typedef struct {\r
201 EFI_PCI_IO_PROTOCOL_CONFIG Read;\r
202 EFI_PCI_IO_PROTOCOL_CONFIG Write;\r
203} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
204\r
205/** \r
206 Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
207 memory space.\r
208 \r
209 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
210 @param Width Signifies the width of the memory operations.\r
211 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
212 base address for the memory operation to perform. \r
213 @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
214 start the memory writes for the copy operation. \r
215 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
216 base address for the memory operation to perform. \r
217 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
218 the memory reads for the copy operation. \r
219 @param Count The number of memory operations to perform. Bytes moved is Width\r
220 size * Count, starting at DestOffset and SrcOffset. \r
221 \r
222 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
223 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
224 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
225 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
226 is not valid for the PCI BAR specified by DestBarIndex. \r
227 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
228 not valid for the PCI BAR specified by SrcBarIndex. \r
229 @retval EFI_INVALID_PARAMETER Width is invalid.\r
230 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
231 \r
232**/\r
233typedef\r
234EFI_STATUS\r
235(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM) (\r
236 IN EFI_PCI_IO_PROTOCOL *This,\r
237 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
238 IN UINT8 DestBarIndex,\r
239 IN UINT64 DestOffset,\r
240 IN UINT8 SrcBarIndex,\r
241 IN UINT64 SrcOffset,\r
242 IN UINTN Count\r
243 );\r
244\r
245/** \r
246 Provides the PCI controller-Cspecific addresses needed to access system memory.\r
247 \r
248 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
249 @param Operation Indicates if the bus master is going to read or write to system memory.\r
250 @param HostAddress The system memory address to map to the PCI controller.\r
251 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
252 that were mapped. \r
253 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
254 access the hosts HostAddress. \r
255 @param Mapping A resulting value to pass to Unmap().\r
256 \r
257 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
258 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. \r
259 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
260 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
261 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
262 \r
263**/\r
264typedef\r
265EFI_STATUS\r
266(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP) (\r
267 IN EFI_PCI_IO_PROTOCOL *This,\r
268 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
269 IN VOID *HostAddress,\r
270 IN OUT UINTN *NumberOfBytes,\r
271 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
272 OUT VOID **Mapping\r
273 );\r
274\r
275/** \r
276 Completes the Map() operation and releases any corresponding resources.\r
277 \r
278 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
279 @param Mapping The mapping value returned from Map().\r
280 \r
281 @retval EFI_SUCCESS The range was unmapped.\r
282 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
283 \r
284**/\r
285typedef\r
286EFI_STATUS\r
287(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP) (\r
288 IN EFI_PCI_IO_PROTOCOL *This,\r
289 IN VOID *Mapping\r
290 );\r
291\r
292/** \r
293 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
294 mapping. \r
295 \r
296 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
297 @param Type This parameter is not used and must be ignored.\r
298 @param MemoryType The type of memory to allocate, EfiBootServicesData or\r
299 EfiRuntimeServicesData. \r
300 @param Pages The number of pages to allocate. \r
301 @param HostAddress A pointer to store the base system memory address of the\r
302 allocated range. \r
303 @param Attributes The requested bit mask of attributes for the allocated range.\r
304 \r
305 @retval EFI_SUCCESS The requested memory pages were allocated.\r
306 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
307 MEMORY_WRITE_COMBINE and MEMORY_CACHED. \r
308 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
309 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. \r
310 \r
311**/\r
312typedef\r
313EFI_STATUS\r
314(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER) (\r
315 IN EFI_PCI_IO_PROTOCOL *This,\r
316 IN EFI_ALLOCATE_TYPE Type,\r
317 IN EFI_MEMORY_TYPE MemoryType,\r
318 IN UINTN Pages,\r
319 OUT VOID **HostAddress,\r
320 IN UINT64 Attributes\r
321 );\r
322\r
323/** \r
324 Frees memory that was allocated with AllocateBuffer().\r
325 \r
326 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
327 @param Pages The number of pages to free. \r
328 @param HostAddress The base system memory address of the allocated range. \r
329 \r
330 @retval EFI_SUCCESS The requested memory pages were freed.\r
331 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
332 was not allocated with AllocateBuffer().\r
333 \r
334**/\r
335typedef\r
336EFI_STATUS\r
337(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER) (\r
338 IN EFI_PCI_IO_PROTOCOL *This,\r
339 IN UINTN Pages,\r
340 IN VOID *HostAddress\r
341 );\r
342\r
343/** \r
344 Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
345 \r
346 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
347 \r
348 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
349 bridge to system memory. \r
350 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
351 host bridge due to a hardware error. \r
352 \r
353**/\r
354typedef\r
355EFI_STATUS\r
356(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH) (\r
357 IN EFI_PCI_IO_PROTOCOL *This\r
358 );\r
359\r
360/** \r
361 Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
362 \r
363 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
364 @param SegmentNumber The PCI controller's current PCI segment number.\r
365 @param BusNumber The PCI controller's current PCI bus number.\r
366 @param DeviceNumber The PCI controller's current PCI device number.\r
367 @param FunctionNumber The PCI controller's current PCI function number.\r
368 \r
369 @retval EFI_SUCCESS The PCI controller location was returned. \r
370 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
371 \r
372**/\r
373typedef\r
374EFI_STATUS\r
375(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION) (\r
376 IN EFI_PCI_IO_PROTOCOL *This,\r
377 OUT UINTN *SegmentNumber,\r
378 OUT UINTN *BusNumber,\r
379 OUT UINTN *DeviceNumber,\r
380 OUT UINTN *FunctionNumber\r
381 );\r
382\r
383/** \r
384 Performs an operation on the attributes that this PCI controller supports. The operations include\r
385 getting the set of supported attributes, retrieving the current attributes, setting the current \r
386 attributes, enabling attributes, and disabling attributes. \r
387 \r
388 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
389 @param Operation The operation to perform on the attributes for this PCI controller.\r
390 @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
391 operations. \r
392 @param Result A pointer to the result mask of attributes that are returned for the Get\r
393 and Supported operations. \r
394 \r
395 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
396 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
397 @retval EFI_UNSUPPORTED one or more of the bits set in \r
398 Attributes are not supported by this PCI controller or one of\r
399 its parent bridges when Operation is Set, Enable or Disable.\r
400 \r
401**/\r
402typedef\r
403EFI_STATUS\r
404(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES) (\r
405 IN EFI_PCI_IO_PROTOCOL *This,\r
406 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
407 IN UINT64 Attributes,\r
408 OUT UINT64 *Result OPTIONAL\r
409 );\r
410\r
411/** \r
412 Gets the attributes that this PCI controller supports setting on a BAR using\r
413 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
414 \r
415 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
416 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
417 base address for resource range. The legal range for this field is 0..5.\r
418 @param Supports A pointer to the mask of attributes that this PCI controller supports\r
419 setting for this BAR with SetBarAttributes(). \r
420 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r
421 configuration of this BAR of the PCI controller. \r
422 \r
423 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI \r
424 controller supports are returned in Supports. If Resources \r
425 is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r
426 controller is currently using are returned in Resources. \r
427 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
428 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
429 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
430 Resources. \r
431 \r
432**/\r
433typedef\r
434EFI_STATUS\r
435(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES) (\r
436 IN EFI_PCI_IO_PROTOCOL *This,\r
437 IN UINT8 BarIndex,\r
438 OUT UINT64 *Supports, OPTIONAL\r
439 OUT VOID **Resources OPTIONAL\r
440 );\r
441\r
442/** \r
443 Sets the attributes for a range of a BAR on a PCI controller.\r
444 \r
445 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
446 @param Attributes The mask of attributes to set for the resource range specified by\r
447 BarIndex, Offset, and Length. \r
448 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
449 base address for resource range. The legal range for this field is 0..5.\r
450 @param Offset A pointer to the BAR relative base address of the resource range to be\r
451 modified by the attributes specified by Attributes. \r
452 @param Length A pointer to the length of the resource range to be modified by the\r
453 attributes specified by Attributes. \r
454 \r
455 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource \r
456 range specified by BarIndex, Offset, and Length were \r
457 set on the PCI controller, and the actual resource range is returned\r
458 in Offset and Length. \r
459 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
460 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
461 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
462 resource range specified by BarIndex, Offset, and \r
463 Length. \r
464 \r
465**/\r
466typedef\r
467EFI_STATUS\r
468(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES) (\r
469 IN EFI_PCI_IO_PROTOCOL *This,\r
470 IN UINT64 Attributes,\r
471 IN UINT8 BarIndex,\r
472 IN OUT UINT64 *Offset,\r
473 IN OUT UINT64 *Length\r
474 );\r
475\r
476//\r
477// Interface structure for the PCI I/O Protocol\r
478//\r
479struct _EFI_PCI_IO_PROTOCOL {\r
480 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
481 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
482 EFI_PCI_IO_PROTOCOL_ACCESS Mem;\r
483 EFI_PCI_IO_PROTOCOL_ACCESS Io;\r
484 EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;\r
485 EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem;\r
486 EFI_PCI_IO_PROTOCOL_MAP Map;\r
487 EFI_PCI_IO_PROTOCOL_UNMAP Unmap;\r
488 EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
489 EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
490 EFI_PCI_IO_PROTOCOL_FLUSH Flush;\r
491 EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation;\r
492 EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;\r
493 EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;\r
494 EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;\r
495 UINT64 RomSize;\r
496 VOID *RomImage;\r
497};\r
498\r
499extern EFI_GUID gEfiPciIoProtocolGuid;\r
500\r
501#endif\r
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