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d1f95000 1/** @file\r
4ca9b6c4
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2 EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration, \r
3 and DMA interfaces that a driver uses to access its PCI controller.\r
d1f95000 4\r
51312091 5 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
9df063a0 6 This program and the accompanying materials \r
d1f95000 7 are licensed and made available under the terms and conditions of the BSD License \r
8 which accompanies this distribution. The full text of the license may be found at \r
9 http://opensource.org/licenses/bsd-license.php \r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
13\r
d1f95000 14**/\r
15\r
16#ifndef __PCI_IO_H__\r
17#define __PCI_IO_H__\r
18\r
99e8ed21 19///\r
20/// Global ID for the PCI I/O Protocol\r
21///\r
d1f95000 22#define EFI_PCI_IO_PROTOCOL_GUID \\r
23 { \\r
24 0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r
25 }\r
26\r
27typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r
28\r
99e8ed21 29///\r
9319d2c2
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30/// *******************************************************\r
31/// EFI_PCI_IO_PROTOCOL_WIDTH\r
32/// *******************************************************\r
99e8ed21 33///\r
d1f95000 34typedef enum {\r
35 EfiPciIoWidthUint8 = 0,\r
36 EfiPciIoWidthUint16,\r
37 EfiPciIoWidthUint32,\r
38 EfiPciIoWidthUint64,\r
39 EfiPciIoWidthFifoUint8,\r
40 EfiPciIoWidthFifoUint16,\r
41 EfiPciIoWidthFifoUint32,\r
42 EfiPciIoWidthFifoUint64,\r
43 EfiPciIoWidthFillUint8,\r
44 EfiPciIoWidthFillUint16,\r
45 EfiPciIoWidthFillUint32,\r
46 EfiPciIoWidthFillUint64,\r
47 EfiPciIoWidthMaximum\r
48} EFI_PCI_IO_PROTOCOL_WIDTH;\r
49\r
50//\r
51// Complete PCI address generater\r
52//\r
cce6f7aa 53#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged\r
54#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles\r
55#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode)\r
56#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
57#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
58#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
59#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
60#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
61#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
630b4187 62#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined\r
cce6f7aa 63#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header\r
64#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header\r
65#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header\r
66#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached\r
67#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range\r
68#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device\r
69#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR\r
70#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC\r
71#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
72#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
e0ee9d93 73#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
d1f95000 74\r
75#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
76#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
77\r
99e8ed21 78///\r
79/// *******************************************************\r
80/// EFI_PCI_IO_PROTOCOL_OPERATION\r
81/// *******************************************************\r
82///\r
d1f95000 83typedef enum {\r
992f22b9
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84 ///\r
85 /// A read operation from system memory by a bus master.\r
86 ///\r
d1f95000 87 EfiPciIoOperationBusMasterRead,\r
992f22b9
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88 ///\r
89 /// A write operation from system memory by a bus master.\r
90 ///\r
d1f95000 91 EfiPciIoOperationBusMasterWrite,\r
992f22b9
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92 ///\r
93 /// Provides both read and write access to system memory by both the processor and a\r
1bf79370 94 /// bus master. The buffer is coherent from both the processor's and the bus master's point of view.\r
992f22b9 95 ///\r
d1f95000 96 EfiPciIoOperationBusMasterCommonBuffer,\r
97 EfiPciIoOperationMaximum\r
98} EFI_PCI_IO_PROTOCOL_OPERATION;\r
99\r
99e8ed21 100///\r
101/// *******************************************************\r
102/// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION\r
103/// *******************************************************\r
104///\r
d1f95000 105typedef enum {\r
992f22b9 106 ///\r
1bf79370 107 /// Retrieve the PCI controller's current attributes, and return them in Result.\r
992f22b9 108 ///\r
d1f95000 109 EfiPciIoAttributeOperationGet,\r
992f22b9 110 ///\r
1bf79370 111 /// Set the PCI controller's current attributes to Attributes.\r
992f22b9 112 ///\r
d1f95000 113 EfiPciIoAttributeOperationSet,\r
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114 ///\r
115 /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller.\r
116 ///\r
d1f95000 117 EfiPciIoAttributeOperationEnable,\r
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118 ///\r
119 /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller.\r
120 ///\r
d1f95000 121 EfiPciIoAttributeOperationDisable,\r
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122 ///\r
123 /// Retrieve the PCI controller's supported attributes, and return them in Result.\r
124 ///\r
d1f95000 125 EfiPciIoAttributeOperationSupported,\r
126 EfiPciIoAttributeOperationMaximum\r
127} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r
128\r
129/** \r
630b4187 130 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
d1f95000 131 satisfied or after a defined duration. \r
132 \r
133 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
134 @param Width Signifies the width of the memory or I/O operations.\r
135 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
136 base address for the memory operation to perform. \r
137 @param Offset The offset within the selected BAR to start the memory operation.\r
138 @param Mask Mask used for the polling criteria.\r
139 @param Value The comparison value used for the polling exit criteria.\r
140 @param Delay The number of 100 ns units to poll.\r
141 @param Result Pointer to the last value read from the memory location.\r
142 \r
143 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
144 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
145 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
146 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
147 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
148 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
149 \r
150**/\r
151typedef\r
152EFI_STATUS\r
8b13229b 153(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM)(\r
d1f95000 154 IN EFI_PCI_IO_PROTOCOL *This,\r
155 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
156 IN UINT8 BarIndex,\r
157 IN UINT64 Offset,\r
158 IN UINT64 Mask,\r
159 IN UINT64 Value,\r
160 IN UINT64 Delay,\r
161 OUT UINT64 *Result\r
162 );\r
163\r
164/** \r
165 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
166 \r
167 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
168 @param Width Signifies the width of the memory or I/O operations.\r
169 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
170 base address for the memory or I/O operation to perform. \r
171 @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
172 @param Count The number of memory or I/O operations to perform.\r
173 @param Buffer For read operations, the destination buffer to store the results. For write\r
174 operations, the source buffer to write data from. \r
175 \r
176 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
177 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
178 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
179 valid for the PCI BAR specified by BarIndex. \r
180 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
181 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
182 \r
183**/\r
184typedef\r
185EFI_STATUS\r
8b13229b 186(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM)(\r
d1f95000 187 IN EFI_PCI_IO_PROTOCOL *This,\r
188 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
189 IN UINT8 BarIndex,\r
190 IN UINT64 Offset,\r
191 IN UINTN Count,\r
192 IN OUT VOID *Buffer\r
193 );\r
194\r
195typedef struct {\r
992f22b9
LG
196 ///\r
197 /// Read PCI controller registers in the PCI memory or I/O space.\r
198 ///\r
d1f95000 199 EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r
992f22b9
LG
200 ///\r
201 /// Write PCI controller registers in the PCI memory or I/O space.\r
202 ///\r
d1f95000 203 EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r
204} EFI_PCI_IO_PROTOCOL_ACCESS;\r
205\r
206/** \r
207 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
208 \r
209 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
210 @param Width Signifies the width of the memory operations.\r
211 @param Offset The offset within the PCI configuration space for the PCI controller.\r
212 @param Count The number of PCI configuration operations to perform.\r
213 @param Buffer For read operations, the destination buffer to store the results. For write\r
214 operations, the source buffer to write data from.\r
215 \r
216 \r
217 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
218 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
219 valid for the PCI configuration header of the PCI controller.\r
220 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
221 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r
222 \r
223**/\r
224typedef\r
225EFI_STATUS\r
8b13229b 226(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG)(\r
d1f95000 227 IN EFI_PCI_IO_PROTOCOL *This,\r
228 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
229 IN UINT32 Offset,\r
230 IN UINTN Count,\r
231 IN OUT VOID *Buffer\r
232 );\r
233\r
234typedef struct {\r
992f22b9
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235 ///\r
236 /// Read PCI controller registers in PCI configuration space.\r
237 ///\r
d1f95000 238 EFI_PCI_IO_PROTOCOL_CONFIG Read;\r
992f22b9
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239 ///\r
240 /// Write PCI controller registers in PCI configuration space.\r
241 ///\r
d1f95000 242 EFI_PCI_IO_PROTOCOL_CONFIG Write;\r
243} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
244\r
245/** \r
246 Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
247 memory space.\r
248 \r
249 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
250 @param Width Signifies the width of the memory operations.\r
251 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
252 base address for the memory operation to perform. \r
253 @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
254 start the memory writes for the copy operation. \r
255 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
256 base address for the memory operation to perform. \r
257 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
258 the memory reads for the copy operation. \r
259 @param Count The number of memory operations to perform. Bytes moved is Width\r
260 size * Count, starting at DestOffset and SrcOffset. \r
261 \r
262 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
263 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
264 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
265 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
266 is not valid for the PCI BAR specified by DestBarIndex. \r
267 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
268 not valid for the PCI BAR specified by SrcBarIndex. \r
269 @retval EFI_INVALID_PARAMETER Width is invalid.\r
270 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
271 \r
272**/\r
273typedef\r
274EFI_STATUS\r
8b13229b 275(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM)(\r
d1f95000 276 IN EFI_PCI_IO_PROTOCOL *This,\r
277 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
278 IN UINT8 DestBarIndex,\r
279 IN UINT64 DestOffset,\r
280 IN UINT8 SrcBarIndex,\r
281 IN UINT64 SrcOffset,\r
282 IN UINTN Count\r
283 );\r
284\r
285/** \r
630b4187 286 Provides the PCI controller-specific addresses needed to access system memory.\r
d1f95000 287 \r
288 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
289 @param Operation Indicates if the bus master is going to read or write to system memory.\r
290 @param HostAddress The system memory address to map to the PCI controller.\r
291 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
292 that were mapped. \r
293 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
294 access the hosts HostAddress. \r
295 @param Mapping A resulting value to pass to Unmap().\r
296 \r
297 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
298 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. \r
299 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
300 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
301 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
302 \r
303**/\r
304typedef\r
305EFI_STATUS\r
8b13229b 306(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP)(\r
d1f95000 307 IN EFI_PCI_IO_PROTOCOL *This,\r
308 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
309 IN VOID *HostAddress,\r
310 IN OUT UINTN *NumberOfBytes,\r
311 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
312 OUT VOID **Mapping\r
313 );\r
314\r
315/** \r
316 Completes the Map() operation and releases any corresponding resources.\r
317 \r
318 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
319 @param Mapping The mapping value returned from Map().\r
320 \r
321 @retval EFI_SUCCESS The range was unmapped.\r
322 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
323 \r
324**/\r
325typedef\r
326EFI_STATUS\r
8b13229b 327(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP)(\r
d1f95000 328 IN EFI_PCI_IO_PROTOCOL *This,\r
329 IN VOID *Mapping\r
330 );\r
331\r
332/** \r
333 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
595ba42d 334 or EfiPciOperationBusMasterCommonBuffer64 mapping.\r
d1f95000 335 \r
336 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
337 @param Type This parameter is not used and must be ignored.\r
338 @param MemoryType The type of memory to allocate, EfiBootServicesData or\r
339 EfiRuntimeServicesData. \r
340 @param Pages The number of pages to allocate. \r
341 @param HostAddress A pointer to store the base system memory address of the\r
342 allocated range. \r
343 @param Attributes The requested bit mask of attributes for the allocated range.\r
344 \r
345 @retval EFI_SUCCESS The requested memory pages were allocated.\r
346 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
595ba42d 347 MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE.\r
d1f95000 348 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
349 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. \r
350 \r
351**/\r
352typedef\r
353EFI_STATUS\r
8b13229b 354(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER)(\r
d1f95000 355 IN EFI_PCI_IO_PROTOCOL *This,\r
356 IN EFI_ALLOCATE_TYPE Type,\r
357 IN EFI_MEMORY_TYPE MemoryType,\r
358 IN UINTN Pages,\r
359 OUT VOID **HostAddress,\r
360 IN UINT64 Attributes\r
361 );\r
362\r
363/** \r
364 Frees memory that was allocated with AllocateBuffer().\r
365 \r
366 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
367 @param Pages The number of pages to free. \r
368 @param HostAddress The base system memory address of the allocated range. \r
369 \r
370 @retval EFI_SUCCESS The requested memory pages were freed.\r
371 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
372 was not allocated with AllocateBuffer().\r
373 \r
374**/\r
375typedef\r
376EFI_STATUS\r
8b13229b 377(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER)(\r
d1f95000 378 IN EFI_PCI_IO_PROTOCOL *This,\r
379 IN UINTN Pages,\r
380 IN VOID *HostAddress\r
381 );\r
382\r
383/** \r
384 Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
385 \r
386 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
387 \r
388 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
389 bridge to system memory. \r
390 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
391 host bridge due to a hardware error. \r
392 \r
393**/\r
394typedef\r
395EFI_STATUS\r
8b13229b 396(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH)(\r
d1f95000 397 IN EFI_PCI_IO_PROTOCOL *This\r
398 );\r
399\r
400/** \r
401 Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
402 \r
403 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
404 @param SegmentNumber The PCI controller's current PCI segment number.\r
405 @param BusNumber The PCI controller's current PCI bus number.\r
406 @param DeviceNumber The PCI controller's current PCI device number.\r
407 @param FunctionNumber The PCI controller's current PCI function number.\r
408 \r
409 @retval EFI_SUCCESS The PCI controller location was returned. \r
410 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
411 \r
412**/\r
413typedef\r
414EFI_STATUS\r
8b13229b 415(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION)(\r
d1f95000 416 IN EFI_PCI_IO_PROTOCOL *This,\r
417 OUT UINTN *SegmentNumber,\r
418 OUT UINTN *BusNumber,\r
419 OUT UINTN *DeviceNumber,\r
420 OUT UINTN *FunctionNumber\r
421 );\r
422\r
423/** \r
424 Performs an operation on the attributes that this PCI controller supports. The operations include\r
425 getting the set of supported attributes, retrieving the current attributes, setting the current \r
426 attributes, enabling attributes, and disabling attributes. \r
427 \r
428 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
429 @param Operation The operation to perform on the attributes for this PCI controller.\r
430 @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
431 operations. \r
432 @param Result A pointer to the result mask of attributes that are returned for the Get\r
433 and Supported operations. \r
434 \r
435 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
436 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
437 @retval EFI_UNSUPPORTED one or more of the bits set in \r
438 Attributes are not supported by this PCI controller or one of\r
439 its parent bridges when Operation is Set, Enable or Disable.\r
440 \r
441**/\r
442typedef\r
443EFI_STATUS\r
8b13229b 444(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES)(\r
d1f95000 445 IN EFI_PCI_IO_PROTOCOL *This,\r
446 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
447 IN UINT64 Attributes,\r
448 OUT UINT64 *Result OPTIONAL\r
449 );\r
450\r
51312091 451/**\r
d1f95000 452 Gets the attributes that this PCI controller supports setting on a BAR using\r
453 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
51312091
DB
454\r
455 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
d1f95000 456 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
457 base address for resource range. The legal range for this field is 0..5.\r
458 @param Supports A pointer to the mask of attributes that this PCI controller supports\r
51312091
DB
459 setting for this BAR with SetBarAttributes().\r
460 @param Resources A pointer to the resource descriptors that describe the current\r
461 configuration of this BAR of the PCI controller.\r
d1f95000 462 \r
51312091
DB
463 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r
464 controller supports are returned in Supports. If Resources\r
465 is not NULL, then the resource descriptors that the PCI\r
466 controller is currently using are returned in Resources.\r
d1f95000 467 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
468 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
469 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
51312091 470 Resources.\r
d1f95000 471**/\r
472typedef\r
473EFI_STATUS\r
8b13229b 474(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES)(\r
d1f95000 475 IN EFI_PCI_IO_PROTOCOL *This,\r
476 IN UINT8 BarIndex,\r
477 OUT UINT64 *Supports, OPTIONAL\r
478 OUT VOID **Resources OPTIONAL\r
479 );\r
480\r
481/** \r
482 Sets the attributes for a range of a BAR on a PCI controller.\r
483 \r
484 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
485 @param Attributes The mask of attributes to set for the resource range specified by\r
486 BarIndex, Offset, and Length. \r
487 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
488 base address for resource range. The legal range for this field is 0..5.\r
489 @param Offset A pointer to the BAR relative base address of the resource range to be\r
490 modified by the attributes specified by Attributes. \r
491 @param Length A pointer to the length of the resource range to be modified by the\r
492 attributes specified by Attributes. \r
493 \r
494 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource \r
495 range specified by BarIndex, Offset, and Length were \r
496 set on the PCI controller, and the actual resource range is returned\r
497 in Offset and Length. \r
498 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
499 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
500 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
501 resource range specified by BarIndex, Offset, and \r
502 Length. \r
503 \r
504**/\r
505typedef\r
506EFI_STATUS\r
8b13229b 507(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES)(\r
d1f95000 508 IN EFI_PCI_IO_PROTOCOL *This,\r
509 IN UINT64 Attributes,\r
510 IN UINT8 BarIndex,\r
511 IN OUT UINT64 *Offset,\r
512 IN OUT UINT64 *Length\r
513 );\r
514\r
44717a39 515///\r
516/// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration, \r
630b4187 517/// and DMA interfaces used to abstract accesses to PCI controllers. \r
44717a39 518/// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus. \r
519/// A device driver that wishes to manage a PCI controller in a system will have to \r
520/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller. \r
521///\r
d1f95000 522struct _EFI_PCI_IO_PROTOCOL {\r
523 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
524 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
525 EFI_PCI_IO_PROTOCOL_ACCESS Mem;\r
526 EFI_PCI_IO_PROTOCOL_ACCESS Io;\r
527 EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;\r
528 EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem;\r
529 EFI_PCI_IO_PROTOCOL_MAP Map;\r
530 EFI_PCI_IO_PROTOCOL_UNMAP Unmap;\r
531 EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
532 EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
533 EFI_PCI_IO_PROTOCOL_FLUSH Flush;\r
534 EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation;\r
535 EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;\r
536 EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;\r
537 EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;\r
cce6f7aa 538 \r
539 ///\r
540 /// The size, in bytes, of the ROM image.\r
541 ///\r
d1f95000 542 UINT64 RomSize;\r
cce6f7aa 543\r
544 ///\r
545 /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible \r
546 /// for allocating memory for the ROM image, and copying the contents of the ROM to memory. \r
547 /// The contents of this buffer are either from the PCI option ROM that can be accessed \r
548 /// through the ROM BAR of the PCI controller, or it is from a platform-specific location. \r
549 /// The Attributes() function can be used to determine from which of these two sources \r
550 /// the RomImage buffer was initialized.\r
551 /// \r
d1f95000 552 VOID *RomImage;\r
553};\r
554\r
555extern EFI_GUID gEfiPciIoProtocolGuid;\r
556\r
557#endif\r