MdePkg/Include/Protocol/Tls.h: pack structures from the TLS RFC

[mirror_edk2.git] / MdePkg / Include / Protocol / PciPlatform.h

/** @file\r
  This file declares PlatfromOpRom protocols that provide the interface between \r
  the PCI bus driver/PCI Host Bridge Resource Allocation driver and a platform-specific \r
  driver to describe the unique features of a platform. \r
  This protocol is optional.\r
  \r
Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials are licensed and made available under \r
the terms and conditions of the BSD License that accompanies this distribution.  \r
The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php.                                          \r
    \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
  @par Revision Reference:\r
  This Protocol is defined in UEFI Platform Initialization Specification 1.2 \r
  Volume 5: Standards\r
\r
**/\r
\r
#ifndef _PCI_PLATFORM_H_\r
#define _PCI_PLATFORM_H_\r
\r
///\r
/// This file must be included because the EFI_PCI_PLATFORM_PROTOCOL uses\r
/// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE.\r
///\r
#include <Protocol/PciHostBridgeResourceAllocation.h>\r
\r
///\r
/// Global ID for the EFI_PCI_PLATFORM_PROTOCOL.\r
///\r
#define EFI_PCI_PLATFORM_PROTOCOL_GUID \\r
  { \\r
    0x7d75280, 0x27d4, 0x4d69, {0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41} \\r
  }\r
\r
///\r
/// Forward declaration for EFI_PCI_PLATFORM_PROTOCOL.\r
///\r
typedef struct _EFI_PCI_PLATFORM_PROTOCOL EFI_PCI_PLATFORM_PROTOCOL;\r
\r
///\r
/// EFI_PCI_PLATFORM_POLICY that is a bitmask with the following legal combinations:\r
///   - EFI_RESERVE_NONE_IO_ALIAS:<BR>\r
///       Does not set aside either ISA or VGA I/O resources during PCI\r
///       enumeration. By using this selection, the platform indicates that it does\r
///       not want to support a PCI device that requires ISA or legacy VGA\r
///       resources. If a PCI device driver asks for these resources, the request\r
///       will be turned down.\r
///   - EFI_RESERVE_ISA_IO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:<BR>\r
///       Sets aside the ISA I/O range and all the aliases during PCI\r
///       enumeration. VGA I/O ranges and aliases are included in ISA alias\r
///       ranges. In this scheme, seventy-five percent of the I/O space remains unused.\r
///       By using this selection, the platform indicates that it wants to support\r
///       PCI devices that require the following, at the cost of wasted I/O space:\r
///       ISA range and its aliases\r
///       Legacy VGA range and its aliases\r
///       The PCI bus driver will not allocate I/O addresses out of the ISA I/O\r
///       range and its aliases. The following are the ISA I/O ranges:\r
///         - n100..n3FF\r
///         - n500..n7FF\r
///         - n900..nBFF\r
///         - nD00..nFFF\r
///\r
///       In this case, the PCI bus driver will ask the PCI host bridge driver for\r
///       larger I/O ranges. The PCI host bridge driver is not aware of the ISA\r
///       aliasing policy and merely attempts to allocate the requested ranges.\r
///       The first device that requests the legacy VGA range will get all the\r
///       legacy VGA range plus its aliased addresses forwarded to it. The first\r
///       device that requests the legacy ISA range will get all the legacy ISA\r
///       range, plus its aliased addresses, forwarded to it.\r
///   - EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:<BR>\r
///       Sets aside the ISA I/O range (0x100 - 0x3FF) during PCI enumeration\r
///       and the aliases of the VGA I/O ranges. By using this selection, the\r
///       platform indicates that it will support VGA devices that require VGA\r
///       ranges, including those that require VGA aliases. The platform further\r
///       wants to support non-VGA devices that ask for the ISA range (0x100 -\r
///       3FF), but not if it also asks for the ISA aliases. The PCI bus driver will\r
///       not allocate I/O addresses out of the legacy ISA I/O range (0x100 -\r
///       0x3FF) range or the aliases of the VGA I/O range. If a PCI device\r
///       driver asks for the ISA I/O ranges, including aliases, the request will be\r
///       turned down. The first device that requests the legacy VGA range will\r
///       get all the legacy VGA range plus its aliased addresses forwarded to\r
///       it. When the legacy VGA device asks for legacy VGA ranges and its\r
///       aliases, all the upstream PCI-to-PCI bridges must be set up to perform\r
///       10-bit decode on legacy VGA ranges. To prevent two bridges from\r
///       positively decoding the same address, all PCI-to-PCI bridges that are\r
///       peers to this bridge will have to be set up to not decode ISA aliased\r
///       ranges. In that case, all the devices behind the peer bridges can\r
///       occupy only I/O addresses that are not ISA aliases. This is a limitation\r
///       of PCI-to-PCI bridges and is described in the white paper PCI-to-PCI\r
///       Bridges and Card Bus Controllers on Windows 2000, Windows XP,\r
///       and Windows Server 2003. The PCI enumeration process must be\r
///       cognizant of this restriction.\r
///   - EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS:<BR>\r
///       Sets aside the ISA I/O range (0x100 - 0x3FF) during PCI enumeration.\r
///       VGA I/O ranges are included in the ISA range. By using this selection,\r
///       the platform indicates that it wants to support PCI devices that require\r
///       the ISA range and legacy VGA range, but it does not want to support\r
///       devices that require ISA alias ranges or VGA alias ranges. The PCI\r
///       bus driver will not allocate I/O addresses out of the legacy ISA I/O\r
///       range (0x100-0x3FF). If a PCI device driver asks for the ISA I/O\r
///       ranges, including aliases, the request will be turned down. By using\r
///       this selection, the platform indicates that it will support VGA devices\r
///       that require VGA ranges, but it will not support VGA devices that\r
///       require VGA aliases. To truly support 16-bit VGA decode, all the PCIto-\r
///       PCI bridges that are upstream to a VGA device, as well as\r
///       upstream to the parent PCI root bridge, must support 16-bit VGA I/O\r
///       decode. See the PCI-to-PCI Bridge Architecture Specification for\r
///       information regarding the 16-bit VGA decode support. This\r
///       requirement must hold true for every VGA device in the system. If any\r
///       of these bridges does not support 16-bit VGA decode, it will positively\r
///       decode all the aliases of the VGA I/O ranges and this selection must\r
///       be treated like EFI_RESERVE_ISA_IO_NO_ALIAS |\r
///       EFI_RESERVE_VGA_IO_ALIAS.\r
///\r
typedef UINT32  EFI_PCI_PLATFORM_POLICY;\r
\r
///\r
/// Does not set aside either ISA or VGA I/O resources during PCI\r
/// enumeration.\r
///\r
#define     EFI_RESERVE_NONE_IO_ALIAS        0x0000\r
\r
///\r
/// Sets aside ISA I/O range and all aliases:\r
///   - n100..n3FF\r
///   - n500..n7FF\r
///   - n900..nBFF\r
///   - nD00..nFFF.\r
///\r
#define     EFI_RESERVE_ISA_IO_ALIAS         0x0001\r
\r
///\r
/// Sets aside ISA I/O range 0x100-0x3FF.\r
///\r
#define     EFI_RESERVE_ISA_IO_NO_ALIAS      0x0002\r
\r
///\r
/// Sets aside VGA I/O ranges and all aliases.\r
///\r
#define     EFI_RESERVE_VGA_IO_ALIAS         0x0004\r
\r
///\r
/// Sets aside VGA I/O ranges\r
///\r
#define     EFI_RESERVE_VGA_IO_NO_ALIAS      0x0008\r
\r
///\r
/// EFI_PCI_EXECUTION_PHASE is used to call a platform protocol and execute\r
/// platform-specific code.\r
///\r
typedef enum {\r
  ///\r
  /// The phase that indicates the entry point to the PCI Bus Notify phase. This\r
  /// platform hook is called before the PCI bus driver calls the\r
  /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver.\r
  ///\r
  BeforePciHostBridge = 0,\r
  ///\r
  /// The phase that indicates the entry point to the PCI Bus Notify phase. This\r
  /// platform hook is called before the PCI bus driver calls the\r
  /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver.\r
  ///\r
  ChipsetEntry = 0,\r
  ///\r
  /// The phase that indicates the exit point to the Chipset Notify phase before\r
  /// returning to the PCI Bus Driver Notify phase. This platform hook is called after\r
  /// the PCI bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
  /// driver.\r
  ///\r
  AfterPciHostBridge = 1,\r
  ///\r
  /// The phase that indicates the exit point to the Chipset Notify phase before\r
  /// returning to the PCI Bus Driver Notify phase. This platform hook is called after\r
  /// the PCI bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
  /// driver.\r
  ///\r
  ChipsetExit = 1,\r
  MaximumChipsetPhase\r
} EFI_PCI_EXECUTION_PHASE;\r
\r
typedef EFI_PCI_EXECUTION_PHASE EFI_PCI_CHIPSET_EXECUTION_PHASE;\r
\r
/**\r
  The notification from the PCI bus enumerator to the platform that it is\r
  about to enter a certain phase during the enumeration process.\r
\r
  The PlatformNotify() function can be used to notify the platform driver so that\r
  it can perform platform-specific actions. No specific actions are required.\r
  Eight notification points are defined at this time. More synchronization points\r
  may be added as required in the future. The PCI bus driver calls the platform driver\r
  twice for every Phase-once before the PCI Host Bridge Resource Allocation Protocol\r
  driver is notified, and once after the PCI Host Bridge Resource Allocation Protocol\r
  driver has been notified.\r
  This member function may not perform any error checking on the input parameters. It\r
  also does not return any error codes. If this member function detects any error condition,\r
  it needs to handle those errors on its own because there is no way to surface any\r
  errors to the caller.\r
\r
  @param[in] This           The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
  @param[in] HostBridge     The handle of the host bridge controller.\r
  @param[in] Phase          The phase of the PCI bus enumeration.\r
  @param[in] ExecPhase      Defines the execution phase of the PCI chipset driver.\r
\r
  @retval EFI_SUCCESS   The function completed successfully.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_PLATFORM_PHASE_NOTIFY)(\r
  IN EFI_PCI_PLATFORM_PROTOCOL                      *This,\r
  IN EFI_HANDLE                                     HostBridge,\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE  Phase,\r
  IN EFI_PCI_EXECUTION_PHASE                        ExecPhase\r
  );\r
\r
/**\r
  The notification from the PCI bus enumerator to the platform for each PCI\r
  controller at several predefined points during PCI controller initialization.\r
\r
  The PlatformPrepController() function can be used to notify the platform driver so that\r
  it can perform platform-specific actions. No specific actions are required.\r
  Several notification points are defined at this time. More synchronization points may be\r
  added as required in the future. The PCI bus driver calls the platform driver twice for\r
  every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver\r
  is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has\r
  been notified.\r
  This member function may not perform any error checking on the input parameters. It also\r
  does not return any error codes. If this member function detects any error condition, it\r
  needs to handle those errors on its own because there is no way to surface any errors to\r
  the caller.\r
\r
  @param[in] This           The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
  @param[in] HostBridge     The associated PCI host bridge handle.\r
  @param[in] RootBridge     The associated PCI root bridge handle.\r
  @param[in] PciAddress     The address of the PCI device on the PCI bus.\r
  @param[in] Phase          The phase of the PCI controller enumeration.\r
  @param[in] ExecPhase      Defines the execution phase of the PCI chipset driver.\r
\r
  @retval EFI_SUCCESS   The function completed successfully.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER)(\r
  IN EFI_PCI_PLATFORM_PROTOCOL                     *This,\r
  IN EFI_HANDLE                                    HostBridge,\r
  IN EFI_HANDLE                                    RootBridge,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS   PciAddress,\r
  IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE  Phase,\r
  IN EFI_PCI_EXECUTION_PHASE                       ExecPhase\r
  );\r
\r
/**\r
  Retrieves the platform policy regarding enumeration.\r
\r
  The GetPlatformPolicy() function retrieves the platform policy regarding PCI\r
  enumeration. The PCI bus driver and the PCI Host Bridge Resource Allocation Protocol\r
  driver can call this member function to retrieve the policy.\r
\r
  @param[in]  This        The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
  @param[out] PciPolicy   The platform policy with respect to VGA and ISA aliasing.\r
\r
  @retval EFI_SUCCESS             The function completed successfully.\r
  @retval EFI_INVALID_PARAMETER   PciPolicy is NULL.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_PLATFORM_GET_PLATFORM_POLICY)(\r
  IN  CONST EFI_PCI_PLATFORM_PROTOCOL  *This,\r
  OUT       EFI_PCI_PLATFORM_POLICY    *PciPolicy\r
  );\r
\r
/**\r
  Gets the PCI device's option ROM from a platform-specific location.\r
\r
  The GetPciRom() function gets the PCI device's option ROM from a platform-specific location.\r
  The option ROM will be loaded into memory. This member function is used to return an image\r
  that is packaged as a PCI 2.2 option ROM. The image may contain both legacy and EFI option\r
  ROMs. See the UEFI 2.0 Specification for details. This member function can be used to return\r
  option ROM images for embedded controllers. Option ROMs for embedded controllers are typically\r
  stored in platform-specific storage, and this member function can retrieve it from that storage\r
  and return it to the PCI bus driver. The PCI bus driver will call this member function before\r
  scanning the ROM that is attached to any controller, which allows a platform to specify a ROM\r
  image that is different from the ROM image on a PCI card.\r
\r
  @param[in]  This        The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
  @param[in]  PciHandle   The handle of the PCI device.\r
  @param[out] RomImage    If the call succeeds, the pointer to the pointer to the option ROM image.\r
                          Otherwise, this field is undefined. The memory for RomImage is allocated\r
                          by EFI_PCI_PLATFORM_PROTOCOL.GetPciRom() using the EFI Boot Service AllocatePool().\r
                          It is the caller's responsibility to free the memory using the EFI Boot Service\r
                          FreePool(), when the caller is done with the option ROM.\r
  @param[out] RomSize     If the call succeeds, a pointer to the size of the option ROM size. Otherwise,\r
                          this field is undefined.\r
\r
  @retval EFI_SUCCESS            The option ROM was available for this device and loaded into memory.\r
  @retval EFI_NOT_FOUND          No option ROM was available for this device.\r
  @retval EFI_OUT_OF_RESOURCES   No memory was available to load the option ROM.\r
  @retval EFI_DEVICE_ERROR       An error occurred in obtaining the option ROM.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_PLATFORM_GET_PCI_ROM)(\r
  IN  CONST EFI_PCI_PLATFORM_PROTOCOL  *This,\r
  IN        EFI_HANDLE                 PciHandle,\r
  OUT       VOID                       **RomImage,\r
  OUT       UINTN                      *RomSize\r
  );\r
\r
///\r
/// This protocol provides the interface between the PCI bus driver/PCI Host\r
/// Bridge Resource Allocation driver and a platform-specific driver to describe\r
/// the unique features of a platform.\r
///\r
struct _EFI_PCI_PLATFORM_PROTOCOL {\r
  ///\r
  /// The notification from the PCI bus enumerator to the platform that it is about to \r
  /// enter a certain phase during the enumeration process.\r
  ///\r
  EFI_PCI_PLATFORM_PHASE_NOTIFY          PlatformNotify;\r
  ///\r
  /// The notification from the PCI bus enumerator to the platform for each PCI \r
  /// controller at several predefined points during PCI controller initialization.\r
  /// \r
  EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER PlatformPrepController;\r
  /// \r
  /// Retrieves the platform policy regarding enumeration.\r
  ///\r
  EFI_PCI_PLATFORM_GET_PLATFORM_POLICY   GetPlatformPolicy;\r
  ///\r
  /// Gets the PCI device's option ROM from a platform-specific location.\r
  ///\r
  EFI_PCI_PLATFORM_GET_PCI_ROM           GetPciRom;\r
};\r
\r
extern EFI_GUID   gEfiPciPlatformProtocolGuid;\r
\r
#endif\r