[mirror_edk2.git] / MdePkg / Include / Protocol / PciRootBridgeIo.h

/** @file\r
  PCI Root Bridge I/O protocol as defined in the UEFI 2.0 specification.\r
\r
  PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O, \r
  and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform \r
  defferent types of bus mastering DMA.\r
\r
  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials                          \r
  are licensed and made available under the terms and conditions of the BSD License         \r
  which accompanies this distribution.  The full text of the license may be found at        \r
  http://opensource.org/licenses/bsd-license.php                                            \r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
**/\r
\r
#ifndef __PCI_ROOT_BRIDGE_IO_H__\r
#define __PCI_ROOT_BRIDGE_IO_H__\r
\r
#include <Library/BaseLib.h>\r
\r
#define EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \\r
  { \\r
    0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
  }\r
\r
typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
\r
///\r
/// *******************************************************\r
/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH\r
/// *******************************************************\r
///\r
typedef enum {\r
  EfiPciWidthUint8,\r
  EfiPciWidthUint16,\r
  EfiPciWidthUint32,\r
  EfiPciWidthUint64,\r
  EfiPciWidthFifoUint8,\r
  EfiPciWidthFifoUint16,\r
  EfiPciWidthFifoUint32,\r
  EfiPciWidthFifoUint64,\r
  EfiPciWidthFillUint8,\r
  EfiPciWidthFillUint16,\r
  EfiPciWidthFillUint32,\r
  EfiPciWidthFillUint64,\r
  EfiPciWidthMaximum\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH;\r
\r
///\r
/// *******************************************************\r
/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION\r
/// *******************************************************\r
///\r
typedef enum {\r
  ///\r
  /// A read operation from system memory by a bus master that is not capable of producing\r
  /// PCI dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterRead,\r
  ///\r
  /// A write operation from system memory by a bus master that is not capable of producing\r
  /// PCI dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterWrite,\r
  ///\r
  /// Provides both read and write access to system memory by both the processor and a bus\r
  /// master that is not capable of producing PCI dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterCommonBuffer,\r
  ///\r
  /// A read operation from system memory by a bus master that is capable of producing PCI\r
  /// dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterRead64,\r
  ///\r
  /// A write operation to system memory by a bus master that is capable of producing PCI\r
  /// dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterWrite64,\r
  ///\r
  /// Provides both read and write access to system memory by both the processor and a bus\r
  /// master that is capable of producing PCI dual address cycles.\r
  ///\r
  EfiPciOperationBusMasterCommonBuffer64,\r
  EfiPciOperationMaximum\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;\r
\r
#define EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO          0x0001\r
#define EFI_PCI_ATTRIBUTE_ISA_IO                      0x0002\r
#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO              0x0004\r
#define EFI_PCI_ATTRIBUTE_VGA_MEMORY                  0x0008\r
#define EFI_PCI_ATTRIBUTE_VGA_IO                      0x0010\r
#define EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO              0x0020\r
#define EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO            0x0040\r
#define EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE        0x0080\r
#define EFI_PCI_ATTRIBUTE_MEMORY_CACHED               0x0800\r
#define EFI_PCI_ATTRIBUTE_MEMORY_DISABLE              0x1000\r
#define EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE          0x8000\r
#define EFI_PCI_ATTRIBUTE_ISA_IO_16                   0x10000\r
#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16           0x20000\r
#define EFI_PCI_ATTRIBUTE_VGA_IO_16                   0x40000\r
\r
#define EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER   (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED | EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE)\r
\r
#define EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER (~EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER)\r
\r
#define EFI_PCI_ADDRESS(bus, dev, func, reg) \\r
  (UINT64) ( \\r
  (((UINTN) bus) << 24) | \\r
  (((UINTN) dev) << 16) | \\r
  (((UINTN) func) << 8) | \\r
  (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))\r
\r
typedef struct {\r
  UINT8   Register;\r
  UINT8   Function;\r
  UINT8   Device;\r
  UINT8   Bus;\r
  UINT32  ExtendedRegister;\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS;\r
\r
/**                                                                 \r
  Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
  satisfied or after a defined duration.\r
          \r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Width                 Signifies the width of the memory or I/O operations.\r
  @param  Address               The base address of the memory or I/O operations.  \r
  @param  Mask                  Mask used for the polling criteria.\r
  @param  Value                 The comparison value used for the polling exit criteria.\r
  @param  Delay                 The number of 100 ns units to poll.\r
  @param  Result                Pointer to the last value read from the memory location.\r
                                \r
  @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.\r
  @retval EFI_TIMEOUT           Delay expired before a match occurred.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
                                   \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN  UINT64                                   Address,\r
  IN  UINT64                                   Mask,\r
  IN  UINT64                                   Value,\r
  IN  UINT64                                   Delay,\r
  OUT UINT64                                   *Result\r
  );\r
\r
/**                                                                 \r
  Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
          \r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Width                 Signifies the width of the memory operations.\r
  @param  Address               The base address of the memory operations.                                  \r
  @param  Count                 The number of memory operations to perform.\r
  @param  Buffer                For read operations, the destination buffer to store the results. For write\r
                                operations, the source buffer to write data from.                          \r
  \r
  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.  \r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
                                   \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT64                                   Address,\r
  IN     UINTN                                    Count,\r
  IN OUT VOID                                     *Buffer\r
  );\r
\r
typedef struct {\r
  ///\r
  /// Read PCI controller registers in the PCI root bridge memory space.\r
  ///\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Read;\r
  ///\r
  /// Write PCI controller registers in the PCI root bridge memory space.\r
  ///\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Write;\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;\r
\r
/**                                                                 \r
  Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
  root bridge memory space.                                                                       \r
            \r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
  @param  Width                 Signifies the width of the memory operations.\r
  @param  DestAddress           The destination address of the memory operation.                                \r
  @param  SrcAddress            The source address of the memory operation.                                \r
  @param  Count                 The number of memory operations to perform.    \r
                                \r
  @retval EFI_SUCCESS           The data was copied from one memory region to another memory region.  \r
  @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
                                   \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT64                                   DestAddress,\r
  IN     UINT64                                   SrcAddress,\r
  IN     UINTN                                    Count\r
  );\r
\r
/**                                                                 \r
  Provides the PCI controller-specific addresses required to access system memory from a\r
  DMA bus master.                                                                        \r
            \r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Operation             Indicates if the bus master is going to read or write to system memory.\r
  @param  HostAddress           The system memory address to map to the PCI controller.\r
  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes\r
                                that were mapped.                                                 \r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.                                        \r
  @param  Mapping               A resulting value to pass to Unmap().\r
                                  \r
  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.                                \r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.\r
                                   \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL                *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,\r
  IN     VOID                                       *HostAddress,\r
  IN OUT UINTN                                      *NumberOfBytes,\r
  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,\r
  OUT    VOID                                       **Mapping\r
  );\r
\r
/**                                                                 \r
  Completes the Map() operation and releases any corresponding resources.\r
            \r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Mapping               The mapping value returned from Map().\r
                                  \r
  @retval EFI_SUCCESS           The range was unmapped.\r
  @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.\r
                                   \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  IN  VOID                                     *Mapping\r
  );\r
\r
/**                                                                 \r
  Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
  EfiPciOperationBusMasterCommonBuffer64 mapping.                                 \r
            \r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Type                  This parameter is not used and must be ignored.\r
  @param  MemoryType            The type of memory to allocate, EfiBootServicesData or\r
                                EfiRuntimeServicesData.                               \r
  @param  Pages                 The number of pages to allocate.                                \r
  @param  HostAddress           A pointer to store the base system memory address of the\r
                                allocated range.                                        \r
  @param  Attributes            The requested bit mask of attributes for the allocated range.\r
                                  \r
  @retval EFI_SUCCESS           The requested memory pages were allocated.\r
  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are\r
                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.                     \r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.  \r
                                   \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     EFI_ALLOCATE_TYPE                        Type,\r
  IN     EFI_MEMORY_TYPE                          MemoryType,\r
  IN     UINTN                                    Pages,\r
  IN OUT VOID                                     **HostAddress,\r
  IN     UINT64                                   Attributes\r
  );\r
\r
/**                                                                 \r
  Frees memory that was allocated with AllocateBuffer().\r
            \r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Pages                 The number of pages to free.                                \r
  @param  HostAddress           The base system memory address of the allocated range.                                    \r
                                  \r
  @retval EFI_SUCCESS           The requested memory pages were freed.\r
  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
                                was not allocated with AllocateBuffer().\r
                                     \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  IN  UINTN                                    Pages,\r
  IN  VOID                                     *HostAddress\r
  );\r
\r
/**                                                                 \r
  Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
            \r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
                                  \r
  @retval EFI_SUCCESS           The PCI posted write transactions were flushed from the PCI host\r
                                bridge to system memory.                                        \r
  @retval EFI_DEVICE_ERROR      The PCI posted write transactions were not flushed from the PCI\r
                                host bridge due to a hardware error.                           \r
                                     \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This\r
  );\r
\r
/**                                                                 \r
  Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
  attributes that a PCI root bridge is currently using.                                    \r
            \r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Supports              A pointer to the mask of attributes that this PCI root bridge supports\r
                                setting with SetAttributes().                                         \r
  @param  Attributes            A pointer to the mask of attributes that this PCI root bridge is currently\r
                                using.                                                                      \r
                                \r
  @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI root     \r
                                bridge supports is returned in Supports. If Attributes is          \r
                                not NULL, then the attributes that the PCI root bridge is currently\r
                                using is returned in Attributes.                                   \r
  @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
                                \r
                                     \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This,\r
  OUT UINT64                                   *Supports,\r
  OUT UINT64                                   *Attributes\r
  );\r
\r
/**                                                                 \r
  Sets attributes for a resource range on a PCI root bridge.\r
            \r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Attributes            The mask of attributes to set.\r
  @param  ResourceBase          A pointer to the base address of the resource range to be modified by the\r
                                attributes specified by Attributes.\r
  @param  ResourceLength        A pointer to the length of the resource range to be modified by the\r
                                attributes specified by Attributes.                                                                                                              \r
                                \r
  @retval EFI_SUCCESS           The set of attributes specified by Attributes for the resource   \r
                                range specified by ResourceBase and ResourceLength               \r
                                were set on the PCI root bridge, and the actual resource range is\r
                                returned in ResuourceBase and ResourceLength.                    \r
  @retval EFI_UNSUPPORTED       A bit is set in Attributes that is not supported by the PCI Root\r
                                Bridge.                                                         \r
  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to set the attributes on the                              \r
                                resource range specified by BaseAddress and Length.        \r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                               \r
                                     \r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES)(\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN     UINT64                                   Attributes,\r
  IN OUT UINT64                                   *ResourceBase,\r
  IN OUT UINT64                                   *ResourceLength\r
  );\r
\r
/**                                                                 \r
  Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI\r
  resource descriptors.\r
            \r
  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Resources             A pointer to the resource descriptors that describe the current\r
                                configuration of this PCI root bridge.\r
\r
  @retval EFI_SUCCESS           The current configuration of this PCI root bridge was returned in\r
                                Resources.\r
  @retval EFI_UNSUPPORTED       The current configuration of this PCI root bridge could not be\r
                                retrieved.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION)(\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL          *This,\r
  OUT VOID                                     **Resources\r
  );\r
\r
///\r
/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are \r
/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. \r
///\r
struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {\r
  ///\r
  /// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
  ///\r
  EFI_HANDLE                                      ParentHandle;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM     PollMem;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM     PollIo;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS          Mem;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS          Io;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS          Pci;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM        CopyMem;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP             Map;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP           Unmap;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER     FreeBuffer;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH           Flush;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES  GetAttributes;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES  SetAttributes;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION   Configuration;\r
  \r
  ///\r
  /// The segment number that this PCI root bridge resides.\r
  ///\r
  UINT32                                          SegmentNumber;\r
};\r
\r
extern EFI_GUID gEfiPciRootBridgeIoProtocolGuid;\r
\r
#endif\r
Commit	Line	Data
d1f95000	1	/** @file\r
8a7d75b0	2	PCI Root Bridge I/O protocol as defined in the UEFI 2.0 specification.\r
d1f95000	3	\r
	4	PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O, \r
	5	and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform \r
630b4187	6	defferent types of bus mastering DMA.\r
d1f95000	7	\r
51312091	8	Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
9df063a0	9	This program and the accompanying materials \r
d1f95000	10	are licensed and made available under the terms and conditions of the BSD License \r
	11	which accompanies this distribution. The full text of the license may be found at \r
	12	http://opensource.org/licenses/bsd-license.php \r
	13	\r
	14	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	15	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	16	\r
d1f95000	17	**/\r
	18	\r
	19	#ifndef __PCI_ROOT_BRIDGE_IO_H__\r
	20	#define __PCI_ROOT_BRIDGE_IO_H__\r
	21	\r
2a5c4680	22	#include <Library/BaseLib.h>\r
2a5c4680	23	\r
d1f95000	24	#define EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \\r
	25	{ \\r
	26	0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
	27	}\r
	28	\r
	29	typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
	30	\r
9319d2c2 LG	31	///\r
	32	/// *******************************************************\r
	33	/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH\r
	34	/// *******************************************************\r
	35	///\r
d1f95000	36	typedef enum {\r
	37	EfiPciWidthUint8,\r
	38	EfiPciWidthUint16,\r
	39	EfiPciWidthUint32,\r
	40	EfiPciWidthUint64,\r
	41	EfiPciWidthFifoUint8,\r
	42	EfiPciWidthFifoUint16,\r
	43	EfiPciWidthFifoUint32,\r
	44	EfiPciWidthFifoUint64,\r
	45	EfiPciWidthFillUint8,\r
	46	EfiPciWidthFillUint16,\r
	47	EfiPciWidthFillUint32,\r
	48	EfiPciWidthFillUint64,\r
	49	EfiPciWidthMaximum\r
	50	} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH;\r
	51	\r
9319d2c2 LG	52	///\r
	53	/// *******************************************************\r
	54	/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION\r
	55	/// *******************************************************\r
	56	///\r
d1f95000	57	typedef enum {\r
9319d2c2 LG	58	///\r
	59	/// A read operation from system memory by a bus master that is not capable of producing\r
	60	/// PCI dual address cycles.\r
	61	///\r
d1f95000	62	EfiPciOperationBusMasterRead,\r
9319d2c2 LG	63	///\r
	64	/// A write operation from system memory by a bus master that is not capable of producing\r
	65	/// PCI dual address cycles.\r
	66	///\r
d1f95000	67	EfiPciOperationBusMasterWrite,\r
9319d2c2 LG	68	///\r
	69	/// Provides both read and write access to system memory by both the processor and a bus\r
	70	/// master that is not capable of producing PCI dual address cycles.\r
	71	///\r
d1f95000	72	EfiPciOperationBusMasterCommonBuffer,\r
9319d2c2 LG	73	///\r
	74	/// A read operation from system memory by a bus master that is capable of producing PCI\r
	75	/// dual address cycles.\r
	76	///\r
d1f95000	77	EfiPciOperationBusMasterRead64,\r
9319d2c2 LG	78	///\r
	79	/// A write operation to system memory by a bus master that is capable of producing PCI\r
	80	/// dual address cycles.\r
	81	///\r
d1f95000	82	EfiPciOperationBusMasterWrite64,\r
9319d2c2 LG	83	///\r
	84	/// Provides both read and write access to system memory by both the processor and a bus\r
	85	/// master that is capable of producing PCI dual address cycles.\r
	86	///\r
d1f95000	87	EfiPciOperationBusMasterCommonBuffer64,\r
	88	EfiPciOperationMaximum\r
	89	} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;\r
	90	\r
	91	#define EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001\r
	92	#define EFI_PCI_ATTRIBUTE_ISA_IO 0x0002\r
	93	#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO 0x0004\r
	94	#define EFI_PCI_ATTRIBUTE_VGA_MEMORY 0x0008\r
	95	#define EFI_PCI_ATTRIBUTE_VGA_IO 0x0010\r
	96	#define EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO 0x0020\r
	97	#define EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO 0x0040\r
	98	#define EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080\r
	99	#define EFI_PCI_ATTRIBUTE_MEMORY_CACHED 0x0800\r
	100	#define EFI_PCI_ATTRIBUTE_MEMORY_DISABLE 0x1000\r
	101	#define EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000\r
e0ee9d93	102	#define EFI_PCI_ATTRIBUTE_ISA_IO_16 0x10000\r
	103	#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000\r
	104	#define EFI_PCI_ATTRIBUTE_VGA_IO_16 0x40000\r
d1f95000	105	\r
	106	#define EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE \| EFI_PCI_ATTRIBUTE_MEMORY_CACHED \| EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE)\r
	107	\r
	108	#define EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER (~EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER)\r
	109	\r
	110	#define EFI_PCI_ADDRESS(bus, dev, func, reg) \\r
2a5c4680	111	(UINT64) ( \\r
	112	(((UINTN) bus) << 24) \| \\r
	113	(((UINTN) dev) << 16) \| \\r
	114	(((UINTN) func) << 8) \| \\r
	115	(((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))\r
d1f95000	116	\r
	117	typedef struct {\r
	118	UINT8 Register;\r
	119	UINT8 Function;\r
	120	UINT8 Device;\r
	121	UINT8 Bus;\r
	122	UINT32 ExtendedRegister;\r
	123	} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS;\r
	124	\r
	125	/** \r
	126	Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
	127	satisfied or after a defined duration.\r
	128	\r
	129	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	130	@param Width Signifies the width of the memory or I/O operations.\r
	131	@param Address The base address of the memory or I/O operations. \r
	132	@param Mask Mask used for the polling criteria.\r
	133	@param Value The comparison value used for the polling exit criteria.\r
	134	@param Delay The number of 100 ns units to poll.\r
	135	@param Result Pointer to the last value read from the memory location.\r
	136	\r
	137	@retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
	138	@retval EFI_TIMEOUT Delay expired before a match occurred.\r
	139	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	140	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	141	\r
	142	**/\r
	143	typedef\r
	144	EFI_STATUS\r
8b13229b	145	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM)(\r
d1f95000	146	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	147	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
	148	IN UINT64 Address,\r
	149	IN UINT64 Mask,\r
	150	IN UINT64 Value,\r
	151	IN UINT64 Delay,\r
	152	OUT UINT64 *Result\r
	153	);\r
	154	\r
	155	/** \r
	156	Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
	157	\r
	158	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	159	@param Width Signifies the width of the memory operations.\r
	160	@param Address The base address of the memory operations. \r
	161	@param Count The number of memory operations to perform.\r
	162	@param Buffer For read operations, the destination buffer to store the results. For write\r
	163	operations, the source buffer to write data from. \r
	164	\r
	165	@retval EFI_SUCCESS The data was read from or written to the PCI root bridge. \r
	166	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	167	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	168	\r
	169	**/\r
	170	typedef\r
	171	EFI_STATUS\r
8b13229b	172	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM)(\r
d1f95000	173	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	174	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
	175	IN UINT64 Address,\r
	176	IN UINTN Count,\r
	177	IN OUT VOID *Buffer\r
	178	);\r
	179	\r
	180	typedef struct {\r
992f22b9 LG	181	///\r
	182	/// Read PCI controller registers in the PCI root bridge memory space.\r
	183	///\r
d1f95000	184	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Read;\r
992f22b9 LG	185	///\r
	186	/// Write PCI controller registers in the PCI root bridge memory space.\r
	187	///\r
d1f95000	188	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Write;\r
	189	} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;\r
	190	\r
	191	/** \r
	192	Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
	193	root bridge memory space. \r
	194	\r
	195	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
	196	@param Width Signifies the width of the memory operations.\r
	197	@param DestAddress The destination address of the memory operation. \r
	198	@param SrcAddress The source address of the memory operation. \r
	199	@param Count The number of memory operations to perform. \r
	200	\r
	201	@retval EFI_SUCCESS The data was copied from one memory region to another memory region. \r
	202	@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
	203	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	204	\r
	205	**/\r
	206	typedef\r
	207	EFI_STATUS\r
8b13229b	208	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM)(\r
d1f95000	209	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	210	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
	211	IN UINT64 DestAddress,\r
	212	IN UINT64 SrcAddress,\r
	213	IN UINTN Count\r
	214	);\r
	215	\r
	216	/** \r
630b4187	217	Provides the PCI controller-specific addresses required to access system memory from a\r
d1f95000	218	DMA bus master. \r
	219	\r
	220	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	221	@param Operation Indicates if the bus master is going to read or write to system memory.\r
	222	@param HostAddress The system memory address to map to the PCI controller.\r
	223	@param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
	224	that were mapped. \r
	225	@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
	226	access the hosts HostAddress. \r
	227	@param Mapping A resulting value to pass to Unmap().\r
	228	\r
	229	@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
	230	@retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. \r
	231	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	232	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	233	@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
	234	\r
	235	**/\r
	236	typedef\r
	237	EFI_STATUS\r
8b13229b	238	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP)(\r
d1f95000	239	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	240	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
	241	IN VOID *HostAddress,\r
	242	IN OUT UINTN *NumberOfBytes,\r
	243	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
	244	OUT VOID **Mapping\r
	245	);\r
	246	\r
	247	/** \r
	248	Completes the Map() operation and releases any corresponding resources.\r
	249	\r
	250	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	251	@param Mapping The mapping value returned from Map().\r
	252	\r
	253	@retval EFI_SUCCESS The range was unmapped.\r
	254	@retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
	255	@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
	256	\r
	257	**/\r
	258	typedef\r
	259	EFI_STATUS\r
8b13229b	260	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP)(\r
d1f95000	261	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	262	IN VOID *Mapping\r
	263	);\r
	264	\r
	265	/** \r
	266	Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
	267	EfiPciOperationBusMasterCommonBuffer64 mapping. \r
	268	\r
	269	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	270	@param Type This parameter is not used and must be ignored.\r
	271	@param MemoryType The type of memory to allocate, EfiBootServicesData or\r
	272	EfiRuntimeServicesData. \r
	273	@param Pages The number of pages to allocate. \r
	274	@param HostAddress A pointer to store the base system memory address of the\r
	275	allocated range. \r
	276	@param Attributes The requested bit mask of attributes for the allocated range.\r
	277	\r
	278	@retval EFI_SUCCESS The requested memory pages were allocated.\r
	279	@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
	280	MEMORY_WRITE_COMBINE and MEMORY_CACHED. \r
	281	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	282	@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. \r
	283	\r
	284	**/\r
	285	typedef\r
	286	EFI_STATUS\r
8b13229b	287	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER)(\r
d1f95000	288	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	289	IN EFI_ALLOCATE_TYPE Type,\r
	290	IN EFI_MEMORY_TYPE MemoryType,\r
	291	IN UINTN Pages,\r
	292	IN OUT VOID **HostAddress,\r
	293	IN UINT64 Attributes\r
	294	);\r
	295	\r
	296	/** \r
	297	Frees memory that was allocated with AllocateBuffer().\r
	298	\r
	299	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	300	@param Pages The number of pages to free. \r
	301	@param HostAddress The base system memory address of the allocated range. \r
	302	\r
	303	@retval EFI_SUCCESS The requested memory pages were freed.\r
	304	@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
	305	was not allocated with AllocateBuffer().\r
	306	\r
	307	**/\r
	308	typedef\r
	309	EFI_STATUS\r
8b13229b	310	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER)(\r
d1f95000	311	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	312	IN UINTN Pages,\r
	313	IN VOID *HostAddress\r
	314	);\r
	315	\r
	316	/** \r
	317	Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
	318	\r
	319	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	320	\r
	321	@retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
	322	bridge to system memory. \r
	323	@retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
	324	host bridge due to a hardware error. \r
	325	\r
	326	**/\r
	327	typedef\r
	328	EFI_STATUS\r
8b13229b	329	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH)(\r
d1f95000	330	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
	331	);\r
	332	\r
	333	/** \r
	334	Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
	335	attributes that a PCI root bridge is currently using. \r
	336	\r
	337	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	338	@param Supports A pointer to the mask of attributes that this PCI root bridge supports\r
	339	setting with SetAttributes(). \r
	340	@param Attributes A pointer to the mask of attributes that this PCI root bridge is currently\r
	341	using. \r
	342	\r
	343	@retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root \r
	344	bridge supports is returned in Supports. If Attributes is \r
	345	not NULL, then the attributes that the PCI root bridge is currently\r
	346	using is returned in Attributes. \r
	347	@retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
	348	\r
	349	\r
	350	**/\r
	351	typedef\r
	352	EFI_STATUS\r
8b13229b	353	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES)(\r
d1f95000	354	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	355	OUT UINT64 *Supports,\r
	356	OUT UINT64 *Attributes\r
	357	);\r
	358	\r
	359	/** \r
	360	Sets attributes for a resource range on a PCI root bridge.\r
	361	\r
	362	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
	363	@param Attributes The mask of attributes to set.\r
	364	@param ResourceBase A pointer to the base address of the resource range to be modified by the\r
	365	attributes specified by Attributes.\r
	366	@param ResourceLength A pointer to the length of the resource range to be modified by the\r
	367	attributes specified by Attributes. \r
	368	\r
	369	@retval EFI_SUCCESS The set of attributes specified by Attributes for the resource \r
	370	range specified by ResourceBase and ResourceLength \r
	371	were set on the PCI root bridge, and the actual resource range is\r
	372	returned in ResuourceBase and ResourceLength. \r
	373	@retval EFI_UNSUPPORTED A bit is set in Attributes that is not supported by the PCI Root\r
	374	Bridge. \r
	375	@retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the \r
	376	resource range specified by BaseAddress and Length. \r
	377	@retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
	378	\r
	379	**/\r
	380	typedef\r
	381	EFI_STATUS\r
8b13229b	382	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES)(\r
d1f95000	383	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	384	IN UINT64 Attributes,\r
	385	IN OUT UINT64 *ResourceBase,\r
	386	IN OUT UINT64 *ResourceLength\r
	387	);\r
	388	\r
	389	/** \r
51312091 DB	390	Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI\r
51312091 DB	391	resource descriptors.\r
d1f95000	392	\r
d1f95000	393	@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
51312091 DB	394	@param Resources A pointer to the resource descriptors that describe the current\r
	395	configuration of this PCI root bridge.\r
	396	\r
d1f95000	397	@retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in\r
51312091	398	Resources.\r
d1f95000	399	@retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be\r
51312091 DB	400	retrieved.\r
51312091 DB	401	\r
d1f95000	402	**/\r
	403	typedef\r
	404	EFI_STATUS\r
8b13229b	405	(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION)(\r
d1f95000	406	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	407	OUT VOID **Resources\r
	408	);\r
	409	\r
44717a39	410	///\r
	411	/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are \r
	412	/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. \r
	413	///\r
d1f95000	414	struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {\r
cce6f7aa	415	///\r
	416	/// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
	417	///\r
d1f95000	418	EFI_HANDLE ParentHandle;\r
	419	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
	420	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
	421	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Mem;\r
	422	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Io;\r
	423	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Pci;\r
	424	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM CopyMem;\r
	425	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP Map;\r
	426	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP Unmap;\r
	427	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
	428	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
	429	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH Flush;\r
	430	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES GetAttributes;\r
	431	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES SetAttributes;\r
	432	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION Configuration;\r
cce6f7aa	433	\r
	434	///\r
	435	/// The segment number that this PCI root bridge resides.\r
	436	///\r
d1f95000	437	UINT32 SegmentNumber;\r
	438	};\r
	439	\r
	440	extern EFI_GUID gEfiPciRootBridgeIoProtocolGuid;\r
	441	\r
	442	#endif\r